Gabe Black 2d95f59ece arch,cpu: Separate printing and serialization of VecPredReg. ...

This is equivalent to what was done with VecReg recently.

Change-Id: I8e28c9796bf5cabd35a6bf5b89e55efcf9324d92
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/41999
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

2021-04-20 00:14:09 +00:00

..

arch

arch,cpu: Separate printing and serialization of VecPredReg.

2021-04-20 00:14:09 +00:00

base

base: Improve handling of thread IDs for remote GDB.

2021-04-20 00:11:19 +00:00

cpu

arch,cpu: Separate printing and serialization of VecPredReg.

2021-04-20 00:14:09 +00:00

dev

dev-arm: Turn flash1 into a CFI Flash Memory

2021-04-16 09:52:55 +00:00

doc

misc: Removed unneeded Doxygen pages

2020-04-25 01:08:38 +00:00

doxygen

base,misc: Add group definitions for newly tagged API in src/base

2020-09-08 22:29:43 +00:00

gpu-compute

gpu-compute: Topology and driver changes for dGPU

2021-04-15 16:41:11 +00:00

kern

misc: Fix remaining opening braces

2021-04-07 01:29:31 +00:00

learning_gem5

scons: Pull domain specific build setup out of SConstruct.

2021-04-03 01:18:17 +00:00

mem

arch,mem: Use szext instead of sext as appropriate.

2021-04-20 00:12:25 +00:00

proto

scons: Convert gem5_scons.Configure to a context manager.

2021-04-13 01:04:54 +00:00

python

python: Don't try setting the parent of null SimObject pointers.

2021-04-11 22:16:52 +00:00

sim

sim: Don't needlessly recreate ISA types in InstRecord.

2021-04-20 00:14:09 +00:00

systemc

systemc: Extend TlmBridges to 512 bits

2021-04-19 03:09:18 +00:00

unittest

misc: Fix coding style for class-opening braces

2021-03-19 20:57:24 +00:00

Doxyfile

misc: Update version to "DEVELOP-FOR-V21.1"

2021-03-26 18:21:34 +00:00

SConscript

scons: Allow declaring dependencies of tags

2021-04-19 13:44:11 +00:00