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gem5/src/arch/riscv
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Gabe Black 390a74f599 sim,arch: Collapse the ISA specific versions of m5Syscall. 
The x86 version doesn't do anything x86 specific, and so can be used
generically in sim/pseudo_inst.(hh|cc)

Jira Issue: https://gem5.atlassian.net/browse/GEM5-187

Change-Id: I46c2a7d326bd7a95daa8611888051c180e92e446
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23177
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
2019-12-10 23:58:14 +00:00
..
bare_metal
arch,base: Separate the idea of a memory image and object file.
2019-10-12 04:10:59 +00:00
insts
arch-riscv: Fix disassembling for atomic instructions
2019-11-25 01:26:08 +00:00
isa
arch-riscv: Fix disassembling of immediate for c.lui instruction
2019-12-01 01:48:24 +00:00
linux
arch,cpu,sim: Push syscall number determination up to processes.
2019-12-10 23:58:14 +00:00
decoder.cc
arch,cpu: Move endianness conversion of inst bytes into the ISA.
2019-11-02 00:01:52 +00:00
decoder.hh
arch: cpu: Make the ExtMachInst type a template argument in InstMap.
2018-03-27 10:57:54 +00:00
faults.cc
arch,cpu,sim: Push syscall number determination up to processes.
2019-12-10 23:58:14 +00:00
faults.hh
riscv: Get rid of some ISA specific register types.
2019-01-31 11:03:21 +00:00
idle_event.cc
arch: [Patch 1/5] Added RISC-V base instruction set RV64I
2016-11-30 17:10:28 -05:00
idle_event.hh
cpu: Create a PCEventScope class to abstract the scope of PCEvents.
2019-10-25 22:42:31 +00:00
interrupts.cc
arch: [Patch 1/5] Added RISC-V base instruction set RV64I
2016-11-30 17:10:28 -05:00
interrupts.hh
arch-riscv: Fix bug in serialize and unserialize of Interrutps
2019-11-22 09:13:08 +00:00
isa_traits.hh
arch: Get rid of the (Big|Little)EndianGuest namespaces.
2019-11-18 20:02:31 +00:00
isa.cc
arch: Make a base class for Interrupts.
2019-10-19 01:45:48 +00:00
isa.hh
riscv: Get rid of some ISA specific register types.
2019-01-31 11:03:21 +00:00
kernel_stats.hh
stats: Get rid of some kernel stats related cruft.
2017-09-11 04:58:38 +00:00
locked_mem.cc
riscv: fix AMO, LR and SC instructions
2019-02-08 15:27:04 +00:00
locked_mem.hh
riscv: fix AMO, LR and SC instructions
2019-02-08 15:27:04 +00:00
microcode_rom.hh
arch: [Patch 1/5] Added RISC-V base instruction set RV64I
2016-11-30 17:10:28 -05:00
mmapped_ipr.hh
arch: [Patch 1/5] Added RISC-V base instruction set RV64I
2016-11-30 17:10:28 -05:00
pagetable.cc
arch: [Patch 1/5] Added RISC-V base instruction set RV64I
2016-11-30 17:10:28 -05:00
pagetable.hh
misc: Rename misc.(hh|cc) to logging.(hh|cc)
2017-12-04 23:10:55 +00:00
pra_constants.hh
arch: [Patch 1/5] Added RISC-V base instruction set RV64I
2016-11-30 17:10:28 -05:00
process.cc
arch: Get rid of the now unused setSyscallArg.
2019-12-10 23:58:14 +00:00
process.hh
arch: Get rid of the now unused setSyscallArg.
2019-12-10 23:58:14 +00:00
pseudo_inst.hh
sim,arch: Collapse the ISA specific versions of m5Syscall.
2019-12-10 23:58:14 +00:00
registers.hh
arch-riscv: set MaxMiscDestRegs to 2
2019-12-08 15:17:51 +00:00
remote_gdb.cc
arch-riscv: fix GDB register cache
2019-08-23 23:13:40 +00:00
remote_gdb.hh
arch-riscv: fix GDB register cache
2019-08-23 23:13:40 +00:00
RiscvInterrupts.py
arch: Make a base class for Interrupts.
2019-10-19 01:45:48 +00:00
RiscvISA.py
arch: [Patch 1/5] Added RISC-V base instruction set RV64I
2016-11-30 17:10:28 -05:00
RiscvSystem.py
python: Don't assume SimObjects live in the global namespace
2019-02-12 09:43:00 +00:00
RiscvTLB.py
python: Don't assume SimObjects live in the global namespace
2019-02-12 09:43:00 +00:00
SConscript
arch-riscv: enable rudimentary fs simulation
2018-07-09 11:17:11 +00:00
SConsopts
arch: [Patch 1/5] Added RISC-V base instruction set RV64I
2016-11-30 17:10:28 -05:00
stacktrace.cc
arch: [Patch 1/5] Added RISC-V base instruction set RV64I
2016-11-30 17:10:28 -05:00
stacktrace.hh
arch: Stop using TheISA within the ISAs.
2019-04-30 18:52:13 +00:00
system.cc
arch: Get rid of the (Big|Little)EndianGuest namespaces.
2019-11-18 20:02:31 +00:00
system.hh
mips,riscv: Get rid of some Alpha cruft in these System classes.
2019-10-25 23:53:01 +00:00
tlb.cc
arch-riscv: enable rudimentary fs simulation
2018-07-09 11:17:11 +00:00
tlb.hh
misc: Using smart pointers for memory Requests
2018-06-11 16:55:30 +00:00
types.hh
arch-riscv: Enable support for riscv 32-bit in SE mode.
2019-02-07 01:48:08 +00:00
utility.cc
arch-riscv: enable rudimentary fs simulation
2018-07-09 11:17:11 +00:00
utility.hh
arch-riscv: enable rudimentary fs simulation
2018-07-09 11:17:11 +00:00
vtophys.hh
arch: [Patch 1/5] Added RISC-V base instruction set RV64I
2016-11-30 17:10:28 -05:00