Giacomo Travaglini 0fa5ed40c4 arch-arm: Correct mcrr,mrrc disassemble ...

This patch is fixing AArch32 mcrr,mrrc instruction disassemble by
printing the correct source/destination registers

Change-Id: I3fcffa0349aeee466e7c60ba4d1244824fb65d91
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/9501
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

2018-04-06 09:58:41 +00:00

..

arch

arch-arm: Correct mcrr,mrrc disassemble

2018-04-06 09:58:41 +00:00

base

base: Make bitunion output functions static/inline.

2018-03-30 19:22:46 +00:00

cpu

cpu: Remove ExtMachInst typedefs from the O3 CPU model.

2018-03-27 10:58:01 +00:00

dev

dev: Make sure the EtherTap device uses the right event queue.

2018-04-05 02:49:49 +00:00

doc

sim: Adding support for power models

2016-06-06 17:16:44 +01:00

doxygen

MEM: Put memory system document into doxygen

2012-09-25 11:49:41 -05:00

gpu-compute

hsail: Get rid of an inert private member of StorageSpace.

2018-03-22 19:46:54 +00:00

kern

sim-se: Add /sys/devices/system/cpu/online file

2018-03-15 20:45:34 +00:00

learning_gem5

learning_gem5: Add a simple Ruby protocol

2018-03-23 15:50:28 +00:00

mem

mem: Remove unused 'using namespace'

2018-04-06 08:38:06 +00:00

proto

cpu: Stop extracting inst_flags from the machInst.

2018-03-27 10:57:36 +00:00

python

scons: Switch from the print statement to the print function.

2018-03-06 23:39:01 +00:00

sim

sim-se: Fix fallthrough in prlimit

2018-03-15 20:45:34 +00:00

unittest

scons: Switch from the print statement to the print function.

2018-03-06 23:39:01 +00:00

Doxyfile

Doxygen: Update the version of the Doxyfile

2012-10-11 06:38:42 -04:00

SConscript

scons: Switch from the print statement to the print function.

2018-03-06 23:39:01 +00:00