cpu: Remove ExtMachInst typedefs from the O3 CPU model.

These typedefs aren't used, and they expose ISA specific types outside
the ISA implementations.

Change-Id: I64b9cec18d6f92765eebbdf8c8f1de15c0deba34
Reviewed-on: https://gem5-review.googlesource.com/9404
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>

src/cpu/o3/dyn_inst.hh

@@ -65,8 +65,6 @@ class BaseO3DynInst : public BaseDynInst<Impl>
 
     /** Binary machine instruction type. */
     typedef TheISA::MachInst MachInst;
-    /** Extended machine instruction type. */
-    typedef TheISA::ExtMachInst ExtMachInst;
     /** Register types. */
     typedef TheISA::IntReg   IntReg;
     typedef TheISA::FloatReg FloatReg;

src/cpu/o3/fetch.hh

@@ -83,7 +83,6 @@ class DefaultFetch
 
     /** Typedefs from ISA. */
     typedef TheISA::MachInst MachInst;
-    typedef TheISA::ExtMachInst ExtMachInst;
 
     class FetchTranslation : public BaseTLB::Translation
     {