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arch-arm: Correct mcrr,mrrc disassemble

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This patch is fixing AArch32 mcrr,mrrc instruction disassemble by
printing the correct source/destination registers

Change-Id: I3fcffa0349aeee466e7c60ba4d1244824fb65d91
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/9501
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
This commit is contained in:
Giacomo Travaglini
2018-03-27 14:23:28 +01:00
parent 906ef2f7cd
commit 0fa5ed40c4
1 changed files with 2 additions and 2 deletions
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4
src/arch/arm/insts/misc.cc
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@@ -153,7 +153,7 @@ MrrcOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
ss << ", ";
printIntReg(ss, dest2);
ss << ", ";
printIntReg(ss, op1);
printMiscReg(ss, op1);
return ss.str();
}
@@ -162,7 +162,7 @@ McrrOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
{
std::stringstream ss;
printMnemonic(ss);
printIntReg(ss, dest);
printMiscReg(ss, dest);
ss << ", ";
printIntReg(ss, op1);
ss << ", ";