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091f5150a9a5dc697af426b95b82ffde3e54f03f
gem5/src/mem
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Nikos Nikoleris 091f5150a9 mem-ruby: Fix MOESI_CMP_directory in ports order 
To avoid deadlocks ruby objects typically prioritize the handling of
responses to all other events. The order in which in_port statements
are written determine the order in which they are handled. This patch
fixes the order of in_order statements for the L2 cache in the
MOESI_CMP_directory.

Change-Id: I62248b0480a88ac2cd945425155f0961a1cf6cb1
Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/13595
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
2018-10-26 14:13:10 +00:00
..
cache
arch-arm: We add PRFM PST instruction for arm
2018-10-26 12:47:46 +00:00
probes
mem: Fill the new packet ID fields with master IDs when tracing packets.
2017-09-25 21:14:21 +00:00
protocol
mem-ruby: Fix MOESI_CMP_directory in ports order
2018-10-26 14:13:10 +00:00
qos
mem: Implement QoS Proportional Fair policy
2018-09-17 22:51:14 +00:00
ruby
mem-ruby: Fix a bug in MessageBuffer randomization
2018-09-24 21:06:38 +00:00
slicc
ruby: Revamp standalone SLICC script
2018-06-14 22:15:21 +00:00
abstract_mem.cc
mem: Explicitly specify the endianness in the abstract memory.
2018-10-18 07:47:31 +00:00
abstract_mem.hh
misc: Using smart pointers for memory Requests
2018-06-11 16:55:30 +00:00
AbstractMemory.py
cpu, mem, sim: Change how KVM maps memory
2016-08-22 11:41:05 -04:00
addr_mapper.cc
mem: Make cache terminology easier to understand
2015-12-31 09:32:58 -05:00
addr_mapper.hh
mem: Split port retry for all different packet classes
2015-03-02 04:00:35 -05:00
AddrMapper.py
sim: Include object header files in SWIG interfaces
2012-11-02 11:32:01 -05:00
bridge.cc
mem: Rename Packet::checkFunctional to trySatisfyFunctional
2018-07-23 11:57:50 +00:00
bridge.hh
mem: Rename Packet::checkFunctional to trySatisfyFunctional
2018-07-23 11:57:50 +00:00
Bridge.py
mem: Tidy up the bridge with const and additional checks
2013-06-27 05:49:49 -04:00
coherent_xbar.cc
mem: Rename Packet::checkFunctional to trySatisfyFunctional
2018-07-23 11:57:50 +00:00
coherent_xbar.hh
mem: Co-ordination of CMOs in the xbar
2017-12-05 11:47:01 +00:00
comm_monitor.cc
mem: Replace EventWrapper use with EventFunctionWrapper
2017-06-20 18:03:21 +00:00
comm_monitor.hh
mem: Replace EventWrapper use with EventFunctionWrapper
2017-06-20 18:03:21 +00:00
CommMonitor.py
mem: Move trace functionality from the CommMonitor to a probe
2015-08-04 10:29:13 +01:00
dram_ctrl.cc
mem: Make DRAMCtrl a QoS-aware Memory Controller
2018-09-07 13:16:20 +00:00
dram_ctrl.hh
mem: Make DRAMCtrl a QoS-aware Memory Controller
2018-09-07 13:16:20 +00:00
DRAMCtrl.py
mem: Make DRAMCtrl a QoS-aware Memory Controller
2018-09-07 13:16:20 +00:00
drampower.cc
mem: Remove unused 'using namespace'
2018-04-06 08:38:06 +00:00
drampower.hh
mem: Fix search-replace issues in DRAMPower wrapper license
2015-11-25 13:52:56 -05:00
dramsim2_wrapper.cc
misc: Rename misc.(hh|cc) to logging.(hh|cc)
2017-12-04 23:10:55 +00:00
dramsim2_wrapper.hh
mem: Add a wrapped DRAMSim2 memory controller
2014-02-18 05:50:53 -05:00
dramsim2.cc
mem: Rename Packet::checkFunctional to trySatisfyFunctional
2018-07-23 11:57:50 +00:00
dramsim2.hh
mem: Replace EventWrapper use with EventFunctionWrapper
2017-06-20 18:03:21 +00:00
DRAMSim2.py
mem: Add a wrapped DRAMSim2 memory controller
2014-02-18 05:50:53 -05:00
external_master.cc
sim,cpu,mem,arch: Introduced MasterInfo data structure
2018-04-27 16:00:28 +00:00
external_master.hh
mem: Standardize mem folder header guards
2018-02-06 10:26:27 +00:00
external_slave.cc
kvm, mem: Refactor some Event subclasses into lambdas
2017-07-12 20:07:05 +00:00
external_slave.hh
mem: Standardize mem folder header guards
2018-02-06 10:26:27 +00:00
ExternalMaster.py
misc: add a MasterId to the ExternalPort
2017-02-09 19:14:58 -05:00
ExternalSlave.py
mem: Add ExternalMaster and ExternalSlave ports
2014-10-16 05:49:56 -04:00
fs_translating_port_proxy.cc
mem: Remove unused 'using namespace'
2018-04-06 08:38:06 +00:00
fs_translating_port_proxy.hh
mem: Refactor port proxies to support secure accesses
2018-02-19 14:24:46 +00:00
hmc_controller.cc
style: [patch 1/22] use /r/3648/ to reorganize includes
2016-11-09 14:27:37 -06:00
hmc_controller.hh
mem: Standardize mem folder header guards
2018-02-06 10:26:27 +00:00
HMCController.py
mem: hmc: adds controller
2015-11-03 12:17:56 -06:00
mem_checker_monitor.cc
mem: Remove unused 'using namespace'
2018-04-06 08:38:06 +00:00
mem_checker_monitor.hh
mem: Split port retry for all different packet classes
2015-03-02 04:00:35 -05:00
mem_checker.cc
style: [patch 1/22] use /r/3648/ to reorganize includes
2016-11-09 14:27:37 -06:00
mem_checker.hh
misc: Rename misc.(hh|cc) to logging.(hh|cc)
2017-12-04 23:10:55 +00:00
mem_delay.cc
mem: Rename Packet::checkFunctional to trySatisfyFunctional
2018-07-23 11:57:50 +00:00
mem_delay.hh
mem: Rename Packet::checkFunctional to trySatisfyFunctional
2018-07-23 11:57:50 +00:00
mem_master.hh
sim,cpu,mem,arch: Introduced MasterInfo data structure
2018-04-27 16:00:28 +00:00
mem_object.cc
Port: Add protocol-agnostic ports in the port hierarchy
2012-10-15 08:12:35 -04:00
mem_object.hh
Port: Add protocol-agnostic ports in the port hierarchy
2012-10-15 08:12:35 -04:00
MemChecker.py
mem: Add MemChecker and MemCheckerMonitor
2014-12-23 09:31:17 -05:00
MemDelay.py
mem: Add a memory delay simulator
2018-06-28 16:12:53 +00:00
MemObject.py
sim: Include object header files in SWIG interfaces
2012-11-02 11:32:01 -05:00
mport.cc
MEM: Separate snoops and normal memory requests/responses
2012-04-14 05:45:07 -04:00
mport.hh
style: remove trailing whitespace
2016-02-06 17:21:18 -08:00
multi_level_page_table.hh
x86, mem: Rewrite the multilevel page table class.
2018-01-23 20:14:48 +00:00
noncoherent_xbar.cc
mem: Rename Packet::checkFunctional to trySatisfyFunctional
2018-07-23 11:57:50 +00:00
noncoherent_xbar.hh
sim: Decouple draining from the SimObject hierarchy
2015-07-07 09:51:05 +01:00
packet_access.hh
null: Stop specifying an endianness in isa_traits.hh.
2018-10-18 07:48:10 +00:00
packet_queue.cc
mem: Rename Packet::checkFunctional to trySatisfyFunctional
2018-07-23 11:57:50 +00:00
packet_queue.hh
mem: Rename Packet::checkFunctional to trySatisfyFunctional
2018-07-23 11:57:50 +00:00
packet.cc
arch-arm: We add PRFM PST instruction for arm
2018-10-26 12:47:46 +00:00
packet.hh
arch-arm: We add PRFM PST instruction for arm
2018-10-26 12:47:46 +00:00
page_table.cc
misc: Using smart pointers for memory Requests
2018-06-11 16:55:30 +00:00
page_table.hh
misc: Using smart pointers for memory Requests
2018-06-11 16:55:30 +00:00
physical.cc
mem: Use address range to find the right physical address
2018-06-19 14:24:25 +00:00
physical.hh
mem: Use the caching in the AddrRangeMap class in PhysicalMemory
2018-06-19 14:24:25 +00:00
port_proxy.cc
misc: Using smart pointers for memory Requests
2018-06-11 16:55:30 +00:00
port_proxy.hh
mem: Refactor port proxies to support secure accesses
2018-02-19 14:24:46 +00:00
port.cc
misc: Using smart pointers for memory Requests
2018-06-11 16:55:30 +00:00
port.hh
mem: Add function to check if the slave can receive a timing req
2017-12-05 11:47:01 +00:00
qport.hh
mem: Rename Packet::checkFunctional to trySatisfyFunctional
2018-07-23 11:57:50 +00:00
request.hh
arch-arm: We add PRFM PST instruction for arm
2018-10-26 12:47:46 +00:00
SConscript
mem: Add a QoS-aware Memory Controller type
2018-09-07 13:16:20 +00:00
se_translating_port_proxy.cc
mem: Refactor port proxies to support secure accesses
2018-02-19 14:24:46 +00:00
se_translating_port_proxy.hh
mem: Refactor port proxies to support secure accesses
2018-02-19 14:24:46 +00:00
serial_link.cc
mem: Rename Packet::checkFunctional to trySatisfyFunctional
2018-07-23 11:57:50 +00:00
serial_link.hh
mem: Rename Packet::checkFunctional to trySatisfyFunctional
2018-07-23 11:57:50 +00:00
SerialLink.py
mem: different HMC configuration
2016-07-01 09:45:21 -05:00
simple_mem.cc
mem: Rename Packet::checkFunctional to trySatisfyFunctional
2018-07-23 11:57:50 +00:00
simple_mem.hh
mem: Standardize mem folder header guards
2018-02-06 10:26:27 +00:00
SimpleMemory.py
mem: Add an internal packet queue in SimpleMemory
2013-08-19 03:52:25 -04:00
snoop_filter.cc
style: change C/C++ source permissions to noexec
2018-01-10 16:49:23 +00:00
snoop_filter.hh
style: change C/C++ source permissions to noexec
2018-01-10 16:49:23 +00:00
stack_dist_calc.cc
style: fix missing spaces in control statements
2016-02-06 17:21:19 -08:00
stack_dist_calc.hh
mem: Redesign the stack distance calculator as a probe
2015-08-04 10:29:13 +01:00
tport.cc
mem: Rename Packet::checkFunctional to trySatisfyFunctional
2018-07-23 11:57:50 +00:00
tport.hh
mem: Unify delayed packet deletion
2015-11-06 03:26:21 -05:00
xbar.cc
mem: Use address range to find the destination port in the xbar
2018-06-19 14:24:25 +00:00
xbar.hh
mem: Use address range to find the destination port in the xbar
2018-06-19 14:24:25 +00:00
XBar.py
mem: Add the notion of point of unification in the coherent xbar
2017-12-05 11:47:01 +00:00