Adrià Armejach fe7b18c2d7 arch-riscv: Make virtual method RISC-V private ...

* Prior commit defined a shared virtual method that is only used in
  RISC-V. This patch makes the method only visible to the RISC-V ISA.

Change-Id: Ie31e1e1e5933d7c3b9f5af0c20822d3a6a382eee
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/71818
Reviewed-by: Roger Chang <rogerycchang@google.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

2023-06-30 07:39:40 +00:00

..

arch

arch-riscv: Make virtual method RISC-V private

2023-06-30 07:39:40 +00:00

base

base: add Activate to enable log of particular targets

2023-05-16 09:02:38 +00:00

cpu

arch-riscv,cpu-minor: Add MinorDefaultVecFU for risc-v v-ext

2023-06-04 23:50:18 +00:00

dev

dev-amdgpu: Perform frame writes atomically

2023-06-29 19:56:49 +00:00

doc

…

doxygen

…

gpu-compute

configs,gpu-compute: Kernel dispatch-based exit events

2023-06-08 22:03:47 +00:00

kern

misc: Remove the FreeBSD namespace

2023-01-17 09:16:20 +00:00

learning_gem5

mem,arch-arm,mem-ruby,cpu: Remove use of deprecated base port owner

2023-02-03 06:11:45 +00:00

mem

mem: Support backdoor request in AddrMapper

2023-06-29 15:11:19 +00:00

proto

misc: Run pre-commit run on all files in repo

2022-08-24 21:47:07 +00:00

python

resources: Output error message in downloader.py

2023-06-28 16:19:59 +00:00

sim

base: Output link to common errors page

2023-05-26 04:42:25 +00:00

sst

mem,arch-arm,mem-ruby,cpu: Remove use of deprecated base port owner

2023-02-03 06:11:45 +00:00

systemc

misc: Use python f-strings for string formatting

2023-03-16 09:05:29 +00:00

Doxyfile

misc: Update version info for develop branch

2023-01-03 22:08:08 +00:00

SConscript

scons,stdlib: Remove deprecated 'distutils' module

2023-06-16 16:43:26 +00:00