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arch-riscv: Make virtual method RISC-V private

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* Prior commit defined a shared virtual method that is only used in
  RISC-V. This patch makes the method only visible to the RISC-V ISA.

Change-Id: Ie31e1e1e5933d7c3b9f5af0c20822d3a6a382eee
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/71818
Reviewed-by: Roger Chang <rogerycchang@google.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Adrià Armejach
2023-06-23 14:15:41 +02:00
committed by Adrià Armejach
parent 1aa8d6c004
commit fe7b18c2d7
3 changed files with 9 additions and 9 deletions
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1
src/arch/generic/isa.hh
View File

@@ -70,7 +70,6 @@ class BaseISA : public SimObject
public:
virtual PCStateBase *newPCState(Addr new_inst_addr=0) const = 0;
virtual void clear() {}
virtual void clearLoadReservation(ContextID cid) {}
virtual RegVal readMiscRegNoEffect(RegIndex idx) const = 0;
virtual RegVal readMiscReg(RegIndex idx) = 0;

3
src/arch/riscv/faults.cc
View File

@@ -154,7 +154,8 @@ RiscvFault::invoke(ThreadContext *tc, const StaticInstPtr &inst)
}
// Clear load reservation address
tc->getIsaPtr()->clearLoadReservation(tc->contextId());
auto isa = static_cast<RiscvISA::ISA*>(tc->getIsaPtr());
isa->clearLoadReservation(tc->contextId());
// Set PC to fault handler address
Addr addr = mbits(tc->readMiscReg(tvec), 63, 2);

14
src/arch/riscv/isa.hh
View File

@@ -92,13 +92,6 @@ class ISA : public BaseISA
return new PCState(new_inst_addr, rv_type);
}
void
clearLoadReservation(ContextID cid) override
{
Addr& load_reservation_addr = load_reservation_addrs[cid];
load_reservation_addr = INVALID_RESERVATION_ADDR;
}
public:
RegVal readMiscRegNoEffect(RegIndex idx) const override;
RegVal readMiscReg(RegIndex idx) override;
@@ -142,6 +135,13 @@ class ISA : public BaseISA
void resetThread() override;
RiscvType rvType() const { return rv_type; }
void
clearLoadReservation(ContextID cid)
{
Addr& load_reservation_addr = load_reservation_addrs[cid];
load_reservation_addr = INVALID_RESERVATION_ADDR;
}
};
} // namespace RiscvISA