From fe7b18c2d75276857edf24861a6d160796110bda Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Adri=C3=A0=20Armejach?= Date: Fri, 23 Jun 2023 14:15:41 +0200 Subject: [PATCH] arch-riscv: Make virtual method RISC-V private * Prior commit defined a shared virtual method that is only used in RISC-V. This patch makes the method only visible to the RISC-V ISA. Change-Id: Ie31e1e1e5933d7c3b9f5af0c20822d3a6a382eee Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/71818 Reviewed-by: Roger Chang Maintainer: Jason Lowe-Power Reviewed-by: Jason Lowe-Power Tested-by: kokoro --- src/arch/generic/isa.hh | 1 - src/arch/riscv/faults.cc | 3 ++- src/arch/riscv/isa.hh | 14 +++++++------- 3 files changed, 9 insertions(+), 9 deletions(-) diff --git a/src/arch/generic/isa.hh b/src/arch/generic/isa.hh index 58f66fc99b..e9e4d95d7b 100644 --- a/src/arch/generic/isa.hh +++ b/src/arch/generic/isa.hh @@ -70,7 +70,6 @@ class BaseISA : public SimObject public: virtual PCStateBase *newPCState(Addr new_inst_addr=0) const = 0; virtual void clear() {} - virtual void clearLoadReservation(ContextID cid) {} virtual RegVal readMiscRegNoEffect(RegIndex idx) const = 0; virtual RegVal readMiscReg(RegIndex idx) = 0; diff --git a/src/arch/riscv/faults.cc b/src/arch/riscv/faults.cc index 8fb8f81261..a929902e8b 100644 --- a/src/arch/riscv/faults.cc +++ b/src/arch/riscv/faults.cc @@ -154,7 +154,8 @@ RiscvFault::invoke(ThreadContext *tc, const StaticInstPtr &inst) } // Clear load reservation address - tc->getIsaPtr()->clearLoadReservation(tc->contextId()); + auto isa = static_cast(tc->getIsaPtr()); + isa->clearLoadReservation(tc->contextId()); // Set PC to fault handler address Addr addr = mbits(tc->readMiscReg(tvec), 63, 2); diff --git a/src/arch/riscv/isa.hh b/src/arch/riscv/isa.hh index 7ef5c526f5..31001c04b4 100644 --- a/src/arch/riscv/isa.hh +++ b/src/arch/riscv/isa.hh @@ -92,13 +92,6 @@ class ISA : public BaseISA return new PCState(new_inst_addr, rv_type); } - void - clearLoadReservation(ContextID cid) override - { - Addr& load_reservation_addr = load_reservation_addrs[cid]; - load_reservation_addr = INVALID_RESERVATION_ADDR; - } - public: RegVal readMiscRegNoEffect(RegIndex idx) const override; RegVal readMiscReg(RegIndex idx) override; @@ -142,6 +135,13 @@ class ISA : public BaseISA void resetThread() override; RiscvType rvType() const { return rv_type; } + + void + clearLoadReservation(ContextID cid) + { + Addr& load_reservation_addr = load_reservation_addrs[cid]; + load_reservation_addr = INVALID_RESERVATION_ADDR; + } }; } // namespace RiscvISA