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  • 8fe1228f3e scons, ext-testlib: rename NULL_All_Ruby to use all caps Erin Le 2024-10-31 14:45:01 -07:00
  • 3535fd0449 tests: additional trusted_stats files Erin Le 2024-10-31 14:17:23 -07:00
  • 6903420310 tests: Add more hierarchies to traffic gen tests Jason Lowe-Power 2022-04-27 16:48:29 -07:00
  • 97542c1a4c mem-ruby,scons: Add scons option for multiple protocols Jason Lowe-Power 2024-10-25 16:28:46 -07:00
  • 9a904478eb mem-ruby: Use runtime protocol instead of #defines Jason Lowe-Power 2024-10-24 13:54:25 -07:00
  • b7ce3040de mem-ruby: Add ProtocolInfo class Jason Lowe-Power 2024-10-24 13:38:19 -07:00
  • 4f53451073 mem-ruby,configs: Update AMD protos with new names Jason Lowe-Power 2024-10-23 17:16:32 -07:00
  • d1ed308af8 stdlib,mem-ruby: Use protocol-spec. names Jason Lowe-Power 2022-03-30 18:15:01 -07:00
  • 42fe5accea configs,mem-ruby: Procotol-spec. names in CHI Jason Lowe-Power 2022-03-30 17:13:24 -07:00
  • d56d561102 configs,mem-ruby: Protocol-spec. in learning gem5 Jason Lowe-Power 2022-03-30 17:11:20 -07:00
  • 3ba16adeff scons: Change scons for multiple protocols in SLICC Jason Lowe-Power 2024-10-23 15:57:56 -07:00
  • b925a6e57c mem-ruby: Update MachineType autogen file with all types Jason Lowe-Power 2024-10-23 15:56:20 -07:00
  • 18401758aa mem-ruby: Rename SLICC SimObjs with compatibility Jason Lowe-Power 2024-10-23 15:53:54 -07:00
  • 1a713e8c65 mem-ruby: Update HTML output to include protocol Jason Lowe-Power 2022-03-30 16:20:59 -07:00
  • feb45c9cb9 mem-ruby: Move protocol files to subdir Jason Lowe-Power 2022-03-23 17:46:06 -07:00
  • 3a4465d908 mem-ruby: Use namespaces for protocol types Jason Lowe-Power 2022-03-23 15:30:16 -07:00
  • 1b84fbbeae mem-ruby: Use shared and per-protocol SLICC files Jason Lowe-Power 2022-03-23 13:58:40 -07:00
  • c0f67f7388 python: Expand Enum param type to be more Enum-like Jason Lowe-Power 2022-04-26 15:03:59 -07:00
  • 0d16c92341 cpu: add comments and change input type to list studyztp 2024-10-31 13:15:48 -07:00
  • 627734e830 cpu: clear listeners list studyztp 2024-08-18 10:52:01 -07:00
  • 0b0a8431dc cpu: delete listener ptrs after removal studyztp 2024-08-18 10:46:05 -07:00
  • 9fede07f44 cpu: modified with review feedback studyztp 2024-08-18 09:50:50 -07:00
  • 6e39b737c8 cpu: add an example config script studyztp 2024-08-08 10:06:37 -07:00
  • ddb29819ee cpu: reorder functions, add more debug flags and comments studyztp 2024-08-07 22:13:55 -07:00
  • 66d3f7c038 cpu: add GlobalInstTracker and LocalInstTracker studyztp 2024-08-07 21:43:09 -07:00
  • b82ab5ac89 misc: Do not share the random number generator across components (#1534) aperais 2024-11-18 10:36:40 +01:00
  • 5ae26c0f09 stdlib: Add interface to set binary in fs mode (#1743) Jason Lowe-Power 2024-11-12 08:32:12 -06:00
  • c31bc284a8 mem-ruby,sim-se: Fix functional reads for MESI protocols Marleson Graf 2024-08-21 16:47:45 -03:00
  • 63d110fb7a mem-ruby,sim-se: Support Maybe_Stale in functional reads Marleson Graf 2024-08-21 15:39:01 -03:00
  • 78db0e26b2 misc: Merge branch v24.0 stable into v24.1 release staging Bobby R. Bruce 2024-11-11 13:51:39 -08:00
  • 665d32cba2 misc: Fix typo in README.md (#1763) Simon Lammer 2024-11-11 19:03:54 +01:00
  • 8b1075b792 arch, cpu: Add generic getValidAddr to correct exetrace symbol table (#1758) Yu-Cheng Chang 2024-11-08 21:33:53 +08:00
  • ad8bd6b5c7 arch-arm,util-m5: Change arm64's default m5 call type to addr (#1583) Noah Krim 2024-11-07 10:08:10 -08:00
  • ca07a06893 misc: bump mypy from 1.11.2 to 1.13.0 (#1748) dependabot[bot] 2024-11-06 10:41:03 -08:00
  • f2892fd5bc misc: update RELEASE-NOTES.md for simInsts and simOps (#1750) Erin (Jianghua) Le 2024-11-06 10:40:07 -08:00
  • ecde7d9fa9 misc: bump pre-commit from 3.8.0 to 4.0.1 (#1749) dependabot[bot] 2024-11-05 12:16:42 -08:00
  • 70c211236a arch-riscv: sign-extend the PC when enter/leave trap handler (#1756) Yu-Cheng Chang 2024-11-06 04:14:55 +08:00
  • 63ea52de56 arch-riscv: fix vrgather pin count (#1759) Saúl 2024-11-05 21:13:51 +01:00
  • 7f50372979 configs: Update legacy RISC-V FS Linux script (#1753) Tommaso Marinelli 2024-11-05 19:57:57 +01:00
  • 6881534bd2 misc: Add v24.1 release notes for RubySystem changes (#1735) Matthew Poremba 2024-11-05 10:47:37 -08:00
  • d463868f28 dev-amdgpu, gpu-compute, mem-ruby: Add support for writeback L2 in GPU (#1692) Vishnu Ramadas 2024-11-05 12:45:46 -06:00
  • 940f49b63b base: Make BaseGdbRegCache::data() non constant (#1734) ylldummy 2024-11-06 02:43:41 +08:00
  • 3e628dd1c0 arch-arm: Cache a pointer to previously matched TLB entry (#1752) Giacomo Travaglini 2024-11-05 08:49:17 +00:00
  • 2e998c9fc0 arch-riscv: Add support for Zicbop extension (#1710) Leon 2024-11-05 09:08:38 +08:00
  • dba9a9e564 misc: bump tqdm from 4.66.5 to 4.66.6 (#1747) dependabot[bot] 2024-11-04 11:11:40 -08:00
  • 4f74c3a949 arch-arm: Use the cached release object instead of HaveExt (#1751) Giacomo Travaglini 2024-11-03 11:18:10 +00:00
  • 2ed724b670 mem-ruby: Fix two NetDest locals using default constructor (#1746) Matthew Poremba 2024-11-02 08:37:04 -07:00
  • 956b164a43 Add Python interface to get port actual name (#1744) handsomeliu-google 2024-11-02 21:59:50 +08:00
  • d376360255 arch-arm: Rewrite the ArmTLB storage to use an AssociativeCache (#1661) Giacomo Travaglini 2024-11-02 10:18:44 +00:00
  • cc4f466e1e util: Bumps werkzeug in gem5-resources-manager (#1723) Ivana Mitrovic 2024-11-01 10:51:34 -07:00
  • a2476373c9 arch-arm: Do not compute purifyTaggedAddr in checkPermissions (#1739) Giacomo Travaglini 2024-11-01 16:18:57 +00:00
  • df6a318a86 arch-x86: Update MTRR defType register (#1732) Jason Lowe-Power 2024-11-01 08:59:33 -07:00
  • ad17fa040a base: Remove DPRINTF_UNCONDITIONAL (#1724) Daniel Carvalho 2024-10-31 15:40:38 -03:00
  • b5a73b59ef sim: Add include guards in simulate.hh (#1737) Bobby R. Bruce 2024-10-31 00:34:39 -07:00
  • 757b272a25 arch-riscv: Fix Zcmp implement typos (#1727) Yu-Cheng Chang 2024-10-31 00:47:30 +08:00
  • 24b672ab01 tests: update timout on pannotia fw gpu test (#1736) Bobby R. Bruce 2024-10-30 09:47:15 -07:00
  • 429580ee77 tests: update timout on pannotia fw gpu test Harshil Patel 2024-10-30 16:42:23 +00:00
  • 2c6de97ea1 Add SE mode to X86Board and RiscvBoard (#1702) Bobby R. Bruce 2024-10-29 20:17:47 -07:00
  • d5d7880840 util-docker: Add qemu-riscv-env Dockerfile (#1731) Bobby R. Bruce 2024-10-29 17:19:43 -07:00
  • d8e7c91127 mem-ruby: Remove unused variables/mark [maybe unused] (#1650) Bobby R. Bruce 2024-10-29 14:31:20 -07:00
  • 1442a4dccd mem-ruby: Re-enable assign with implicit_ctor structures (#1694) Matthew Poremba 2024-10-29 08:53:14 -07:00
  • 853f2ea012 configs,scons: Update scripts and build_opts to make GPU-FS simulations more configurable (#1693) Matt Sinclair 2024-10-28 17:19:18 -05:00
  • 11dd2c6c09 stdlib: address requested changes to X86, Riscv boards Erin Le 2024-10-28 15:00:19 -07:00
  • 7bddc764cc mem-ruby: Prevent LL/SC livelock in MESI protocols (#1384) (#1399) Marleson Graf 2024-10-28 13:57:10 -03:00
  • dde1c7d3a1 util-docker: Add RISCV to Ubuntu all-deps Docker platforms (#1716) Bobby R. Bruce 2024-10-26 21:17:40 -07:00
  • c9f94f4e06 arch-arm: Replace translateAtomic with translateFunctional in AT (#1713) Giacomo Travaglini 2024-10-25 17:15:52 +01:00
  • c91af552d4 tests: move weekly gpu tests to have separate jobs (#1698) Harshil Patel 2024-10-24 04:02:23 -07:00
  • 709f2c7695 mem-ruby,tests: Add CHI with ISA tests (#1651) Bobby R. Bruce 2024-10-23 15:12:37 -07:00
  • 35db93ada4 arch-riscv: Fix the bug of vsetivli frequently flushing the pipeline (#1526) Bobby R. Bruce 2024-10-23 08:32:56 -07:00
  • 089d780c76 arch-riscv: Fix the bug of vsetivli frequently flushing the pipeline Zhibo Hong 2024-10-23 17:24:43 +08:00
  • 7b7f5ef34a stdlib: add SE mode to RiscvBoard Erin Le 2024-10-22 16:31:01 -07:00
  • b9a19625ce stdlib: add SE mode to X86Board Erin Le 2024-10-22 14:49:21 -07:00
  • f01d68bf96 stdlib, configs: Add RiscvDemoBoard (#1490) Erin (Jianghua) Le 2024-10-22 10:13:22 -07:00
  • 3a14a73982 arch-arm: Add support of AArch32 VRINTN/X/A/Z/M/P instructions. (#1655) Giacomo Travaglini 2024-10-22 18:37:30 +02:00
  • faf764e668 arch-x86: break 32/64-bit LEA's input dependency on prior dest value (#1683) Nicholas Mosier 2024-10-22 09:34:30 -07:00
  • 0f75c39d30 arch-arm: Implement AT as standalone instructions (#1697) Giacomo Travaglini 2024-10-22 17:25:16 +02:00
  • fce42880b9 dev: move dprint of reg name before register read/write (#1684) Harry Chiang 2024-10-22 17:12:38 +08:00
  • 16217f843f mem-ruby: Fix issues in protocols due to multi-RubySystem (#1690) Matthew Poremba 2024-10-21 12:30:03 -07:00
  • 2c679bfa04 tests: Fix replacement_policies tests' refs (#1695) Bobby R. Bruce 2024-10-21 12:28:29 -07:00
  • abf939f880 arch-arm: Improve implementation of AT instructions Junshi Wang 2024-09-05 17:15:31 +08:00
  • 91c5218f91 arch-arm: Add WnR into the AnnotationIDs. Junshi Wang 2024-09-22 11:20:05 +08:00
  • b705629b83 learning-gem5: Add ruby_system param set to RubyPortProxy (#1686) Bobby R. Bruce 2024-10-20 13:04:47 -07:00
  • db47d20371 mem-ruby,misc: Remove redundant assignment (#1685) Bobby R. Bruce 2024-10-20 13:02:53 -07:00
  • d0a9945d47 scons: Changed bits per set for VEGA_X86 to 128 Nagendra-KJ 2024-07-23 11:29:50 -05:00
  • a443b5cbb8 configs: Added command line arguments to gpufs config scripts Nagendra-KJ 2024-07-23 11:27:47 -05:00
  • 644ad3cdb0 misc,tests: Fix incorrect date assignment in Actions Bobby R. Bruce 2024-10-18 14:59:16 -07:00
  • 3e83f3ce4f scons,misc: Portable debug flag generation (#1666) Mahesh Madhav 2024-10-18 14:39:09 -07:00
  • b836a3f239 tests: update input sizes for pannotia tests (#1631) Bobby R. Bruce 2024-10-18 13:42:30 -07:00
  • ddaf70b64f Merge branch 'develop' into update-pannotia-tests Bobby R. Bruce 2024-10-18 13:40:59 -07:00
  • 2e271459d0 mem-cache: Implementation of SMS prefetcher (#1454) Giacomo Travaglini 2024-10-18 19:15:57 +02:00
  • ae56a31b21 tests: Download only the resources used in ponnotia tests Harshil Patel 2024-10-18 17:12:43 +00:00
  • c974bca123 arch-arm: Implement the L2 TLB as a 5-way set associative Giacomo Travaglini 2024-07-15 23:57:35 +01:00
  • 7f826ffbaa arch-arm: Use the AssociativeCache in the ArmTLB Giacomo Travaglini 2024-07-15 13:05:32 +01:00
  • ab6354a9cc arch-arm: Rename TlbEntry::Lookup into TlbEntry::KeyType Giacomo Travaglini 2024-08-16 16:33:29 +01:00
  • c83321b843 arch-arm: Define a SetAssociative indexing policy for the TLB Giacomo Travaglini 2024-07-16 15:59:50 +01:00
  • 376530ef72 arch-arm: Add isValid method to the TlbEntry Giacomo Travaglini 2024-07-19 09:12:14 +01:00
  • 3f18cada53 arch-arm: Add insert method to the TlbEntry Giacomo Travaglini 2024-07-15 23:12:50 +01:00
  • c6cca14b74 arch-arm: Add invalidate method to the TlbEntry Giacomo Travaglini 2024-07-15 18:57:33 +01:00
  • ce8a98d657 arch-arm: Generate Lookup from TlbEntry Giacomo Travaglini 2024-07-15 23:02:27 +01:00
  • fda8eeace4 arch-arm: Keep track of observed page sizes in the TLB Giacomo Travaglini 2024-07-16 09:36:10 +01:00