arch-arm: Add WnR into the AnnotationIDs.

To force WnR to 1 when cache maintainance and address translation
instruction.

Change-Id: Id8608f655eacb5e3c2eba36da0a31e883c55a641

src/arch/arm/faults.cc

@@ -1430,6 +1430,9 @@ DataAbort::annotate(AnnotationIDs id, uint64_t val)
       case OFA:
         faultAddr  = val;
         break;
+      case WnR:
+        write = val;
+        break;
       // Just ignore unknown ID's
       default:
         break;

src/arch/arm/faults.hh

@@ -141,6 +141,8 @@ class ArmFault : public FaultBase
                // the abort is triggered by a CMO. The faulting address is
                // then the address specified in the register argument of the
                // instruction and not the cacheline address (See FAR doc)
+        WnR,  // Write or Read. it should be forced to 1 when
+              // Cache maintainance and address translation instruction.
 
         // AArch64 only
         SF,    // DataAbort: width of the accessed register is SixtyFour