diff --git a/src/arch/arm/faults.cc b/src/arch/arm/faults.cc
index b612516fcc..66c082a216 100644
--- a/src/arch/arm/faults.cc
+++ b/src/arch/arm/faults.cc
@@ -1430,6 +1430,9 @@ DataAbort::annotate(AnnotationIDs id, uint64_t val)
       case OFA:
         faultAddr  = val;
         break;
+      case WnR:
+        write = val;
+        break;
       // Just ignore unknown ID's
       default:
         break;
diff --git a/src/arch/arm/faults.hh b/src/arch/arm/faults.hh
index bcd067c284..025b670767 100644
--- a/src/arch/arm/faults.hh
+++ b/src/arch/arm/faults.hh
@@ -141,6 +141,8 @@ class ArmFault : public FaultBase
                // the abort is triggered by a CMO. The faulting address is
                // then the address specified in the register argument of the
                // instruction and not the cacheline address (See FAR doc)
+        WnR,  // Write or Read. it should be forced to 1 when
+              // Cache maintainance and address translation instruction.
 
         // AArch64 only
         SF,    // DataAbort: width of the accessed register is SixtyFour