ddab4d756a
Merge zizzer:/bk/newmem into zeep.pool:/z/saidi/work/m5.newmem
Ali Saidi
2007-01-22 16:17:11 -05:00
5c1d631f36
check if an executable is dynamic and die if it is Only implemented for ELf. Someone might want to implement it for ecoff and some point
Ali Saidi
2007-01-22 16:14:06 -05:00
e347b49a4e
use writeTagAccess() function to unify writing of Tag access registers Fix extracting of secondary context to shove into tag access register properly sign extend va from 59 bits to 63 (SPARC VA hole)
Ali Saidi
2007-01-22 16:11:49 -05:00
a7072c19db
make sure that page bits of VA on tlb insert are 0
Ali Saidi
2007-01-21 20:02:41 -05:00
3af3610c62
add dumb time of day device
Ali Saidi
2007-01-21 18:04:40 -05:00
d8eeb2e0ff
fix InterruptLevel code to return the correct level (the bit positition that is set in softint)
Ali Saidi
2007-01-20 23:12:32 -05:00
57d11578cf
atually set all 64 bits of the retun value to 0
Ali Saidi
2007-01-20 23:10:43 -05:00
95e4a51c6c
fix flushw implementation
Ali Saidi
2007-01-20 23:09:28 -05:00
ccd67ce44f
Rearange tlb code to remove some duplicate Sparc error register should return ull(0) since it's 64 bits Fix PS1 pointer creation to use the ps1 page size rather than ps0
Ali Saidi
2007-01-20 12:37:02 -05:00
6e0f1c6062
Spill and Fill handlers are actually n*4 + the start address
Ali Saidi
2007-01-20 12:34:00 -05:00
01c959aeaf
Merge zed.eecs.umich.edu:/.automount/zeep/z/saidi/work/m5.newmem into zed.eecs.umich.edu:/z/hsul/work/sparc/x86.m5
Lisa Hsu
2007-01-19 21:34:21 -05:00
f1aeaf7ceb
some hstick and hintp changes.
Lisa Hsu
2007-01-19 21:33:36 -05:00
ae0d8d1681
Allow ASI_LDTX_REAL
Ali Saidi
2007-01-17 18:36:12 -05:00
c8a2d602b1
do a linear search for matching tlb entries instead of using map because you could be mapping a larger page that intersects many fix for lookup table to keep it consistant with tlb on a replace of a specific entry
Ali Saidi
2007-01-17 17:59:22 -05:00
8173a05eaf
Implement reading writing of sync fault status register and address register
Ali Saidi
2007-01-17 13:09:26 -05:00
64528df38d
In the case that we generate a fault (e.g. a tlb miss) on a microcoded instruction set curMacroStaticInst to null This way we'll jump immediately to the handler
Ali Saidi
2007-01-16 19:12:33 -05:00
8d75e4ac3f
Don't add symbols for loaded files to symbol table since they are pretty much meaningless with all the copying that goes on
Ali Saidi
2007-01-16 19:09:27 -05:00
d6c92cdb3c
Fix legion lock code a bit so that if we jump out of a micro coded instruction (because of a fault on the first op) we don't lose sync with legion Only print TLB if there is a tlb difference
Ali Saidi
2007-01-16 19:08:21 -05:00
0584d5bd6c
In the case of ASI_P or ASI_LDTX_P set primary and skip the other checks
Ali Saidi
2007-01-16 19:06:33 -05:00
ecfd628ecd
Modify ISA and staticInst to support a IsFirstMicroOp flag Increment instruction count on first micro-op instead of last
Ali Saidi
2007-01-16 19:06:05 -05:00
5c9cbdbb45
Merge zed.eecs.umich.edu:/z/hsul/work/sparc/ali.m5 into zed.eecs.umich.edu:/z/hsul/work/sparc/m5
Lisa Hsu
2007-01-11 09:48:15 -05:00
42535f5f53
ua2005.cc: formatting/indentation for case statements
Lisa Hsu
2007-01-11 09:41:34 -05:00
9f75c1c58f
ua2005.cc: i SWEAR i committed this already, but apparently i didnt. ust start using HPSTATE::hpriv, etc. to access bitfields.
Lisa Hsu
2007-01-11 09:29:03 -05:00
d939060ec6
Add Trap Level Zero to interrupts, remove some unreachable code that I forgot to remove last time.
Lisa Hsu
2007-01-11 09:18:31 -05:00
9d04510869
bug fixes to get us to 145m instructions
Ali Saidi
2007-01-10 22:19:13 -05:00
28a83c6d1c
quiet/remove some warnings fix implementation of cwp manipulation implement PS0 and PS1 IMMU asis
Ali Saidi
2007-01-09 22:20:38 -05:00
7933aade85
add memory mapped disk device
Ali Saidi
2007-01-09 22:16:49 -05:00
0d7282d7ab
pagetable.hh: small fix so ALPHA_FS will build on macs interrupts.hh: small fix for alpha compile
Lisa Hsu
2007-01-08 20:50:45 -05:00
032ea9b2db
the way i understand it, interrupts in m5 is a little bloated. the usage of CPU->checkInterrupts bool is inconsistent, and i think should eventually be phased out. For now, I've just assumed that CPU->checkInterrupts() is the way to fast path a CPU if you have no interrupts by having a simple bitfield in each ISA to determine whether interrupts are pending. getInterrupts has been mostly filled in.
Lisa Hsu
2007-01-08 18:18:28 -05:00
b45219e7ae
some formatting changes, and update how I do bitfields for HPSTATE and PSTATE to avoid name confusion.
Lisa Hsu
2007-01-08 18:07:17 -05:00
a8b2d66661
change when legion-lock causes the simulation to die. It now happens after two consuctive differences since we compare stuff at slightly different times interrupts are seen the cycle before they happen in m5 so the pc gets changed early.
Ali Saidi
2007-01-08 17:11:10 -05:00
2f4239a685
fix softint and partially implement hstick interrupts need to figure out how to do the acutal interrupting still
Ali Saidi
2007-01-08 17:09:48 -05:00
4a8078192d
set the softint appropriately on an timer compare interrupt there is no interrupt_level_0 interrupt, so start the list at 0x40 so the adding is done correctly
Ali Saidi
2007-01-05 15:04:17 -05:00
b0f11f8f81
Merge zizzer:/bk/newmem into zeep.pool:/z/saidi/work/m5.newmem
Ali Saidi
2007-01-04 20:22:56 -05:00
b46aa88435
Fix stick compare to work correctly and set checkInterrupts to true at the appropriate time turn warnings into dprintfs
Ali Saidi
2007-01-04 20:22:45 -05:00
e6b4fed75d
set __name__ in the root m5 script to __m5_main__ so we can tell if the script is run from m5 as the m5 script
Nathan Binkert
2007-01-03 10:16:22 -08:00
fc45d42d01
Add 'Time' as a parameter type that can accept various formats for time (strings, datetime objects, etc.) Advance system time to 1/1/2009 Clean up time management code a little bit
Nathan Binkert
2007-01-03 10:12:55 -08:00
8840ebcb00
Merge zizzer:/bk/newmem into zower.eecs.umich.edu:/eecshome/m5/newmem
Gabe Black
2007-01-03 00:52:30 -05:00
7d7f3d0e99
Fix up previous commit to proper logic.
Kevin Lim
2006-12-30 13:21:25 -05:00
f6aa2ed47b
Merge zizzer.eecs.umich.edu:/bk/newmem into iceaxe.:/Volumes/work/m5/incoming
Nathan Binkert
2006-12-29 16:58:08 -08:00
a0e8aa6737
Fixes to get non-delay slot ISAs (Alpha) working again, and pulling some debug output out of ifdefs.
Gabe Black
2006-12-28 14:35:31 -05:00
3f2b25d997
Phased out DelaySlotInfo.
Gabe Black
2006-12-28 14:33:45 -05:00
d24f60788f
Some fixes for decode stage branches without delay slots. This will need some work to be compatible with delay slots too. Also changed some direct variable uses to use an accessor function.
Gabe Black
2006-12-28 14:32:41 -05:00
15df0a27bb
Make sure the value of PC is actually updated now that the instruction target isn't set explicitly.
Gabe Black
2006-12-28 14:29:17 -05:00
b642ad00eb
Implement a stub nnpc for alpha that is read only as npc+4.
Gabe Black
2006-12-28 14:27:45 -05:00
9ca6efdb60
Fixed NumMiscArchRegs. This is still a magic number, and it should be set automatically by the miscreg enum. I need to figure out how to do that without including the whole miscregfile.hh and making header spaghetti.
Gabe Black
2006-12-28 14:23:30 -05:00
b48a8fb347
Merge zizzer:/bk/newmem into zeep.pool:/z/saidi/work/m5.newmem
Ali Saidi
2006-12-27 14:38:22 -05:00
ba14d6d0e1
Bug fixes in the TLB Make our replacement algorithm same as legion (although not same as the spec) itb should be 64 entries not 48
Ali Saidi
2006-12-27 14:38:07 -05:00
ff88f3b13a
Compare legion and m5 tlbs for differences Only print faults instructions that aren't traps or faulting loads
Ali Saidi
2006-12-27 14:35:23 -05:00
b6dc902f6a
Change MemoryAccess dprintfs to print the data as well
Ali Saidi
2006-12-27 14:32:26 -05:00
9e90bfafb5
No need to use NULL, just use 0 The result of operator= cannot be an l-value
Nathan Binkert
2006-12-27 10:52:25 -08:00
0bd7518480
Remove some #if FULL_SYSTEMs so MP stuff works even in SE mode.
Kevin Lim
2006-12-26 01:43:18 -05:00
2d029fe584
Make sure that all of the bits in the result are set to some value.
Nathan Binkert
2006-12-24 15:15:12 -08:00
e68a87e7fa
remove some output formatting stuff that we don't use
Nathan Binkert
2006-12-24 14:06:56 -08:00
91ffe811a3
Add options for setting the kernel to run and the script to run
Nathan Binkert
2006-12-22 21:51:19 -08:00
ecd1420341
Expose the C++ event queue to python via the python function m5.internal.event.create(). It takes a python object and a Tick and calls process() when the Tick occurs.
Nathan Binkert
2006-12-21 22:38:50 -08:00
876c59fe8d
Stub for SE mode gdb support for MIPS.
Gabe Black
2006-12-21 20:42:40 -05:00
3f03e5f656
Create a wrapper function to more easily add swig stuff to the build
Nathan Binkert
2006-12-21 15:58:38 -08:00
2cb2b50802
move the swig initialization calls from src/sim/main.cc to src/python/swig/init.cc so that it's not as easy to forget about it when you add a new swig module.
Nathan Binkert
2006-12-21 15:49:16 -08:00
9aecfb3e3b
don't use (*activeThreads).begin(), use activeThreads->blah(). Also don't call (*activeThreads).end() over and over. Just call activeThreads->end() once and save the result. Make sure we always check that there are elements in the list before we grab the first one.
Nathan Binkert
2006-12-20 22:20:11 -08:00
4b3538b609
Merge zizzer.eecs.umich.edu:/bk/newmem into iceaxe.:/Volumes/work/m5/incoming
Nathan Binkert
2006-12-20 21:46:39 -08:00
6487d358a4
<scold> Make sure that variables are always initalized! </scold>
Nathan Binkert
2006-12-20 21:46:16 -08:00
68a0e6f2e9
Fixes to get MIPS_SE to compile.
Gabe Black
2006-12-20 22:14:40 -05:00
327f451eb7
Fixes to get ALPHA_FS and ALPHA_SE to compile again.
Gabe Black
2006-12-20 20:44:06 -05:00
f13155393d
Initial work to make remote gdb available in SE mode. This is completely untested.
Gabe Black
2006-12-20 18:39:40 -05:00
841d76d37b
Make sure the "stack_min" variable is page aligned.
Gabe Black
2006-12-20 15:44:37 -05:00
6bc1e78d07
Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/newmem into zizzer.eecs.umich.edu:/z/stever/bk/newmem-head
Steve Reinhardt
2006-12-19 02:11:48 -05:00
f27c686eb5
Merge zizzer:/bk/newmem into zeep.pool:/z/saidi/work/m5.newmem
Ali Saidi
2006-12-19 02:11:47 -05:00
5e9d8795f2
fix twinx loads a little bit bugfixes and demap implementation in tlb ignore some more differencs for one cycle
Ali Saidi
2006-12-19 02:11:33 -05:00
9d7db8bb2b
Streamline Cache/Tags interface: get rid of redundant functions, don't regenerate address from block in cache so that tags can turn around and use address to look up block again.
Steve Reinhardt
2006-12-18 23:07:52 -08:00
f655932700
No need to template prefetcher on cache TagStore type.
Steve Reinhardt
2006-12-18 21:53:06 -08:00
1428b0de7d
Get rid of generic CacheTags object (fold back into Cache).
Steve Reinhardt
2006-12-18 20:47:12 -08:00
5b41ab694c
Fix a place where the wrong width parameter was used, and set the nextNPC correctly on memory squashes.
Gabe Black
2006-12-18 18:20:13 -05:00
dfafe6741f
Make sure you only handle branch delay slots specially when there actually was a branch.
Gabe Black
2006-12-18 18:18:37 -05:00
af1e8d2d40
Fixing the extended twin format to go with the new isa parser interface.
Gabe Black
2006-12-18 18:17:30 -05:00
9b40a13728
cast chars to int when we want to print integers so we get a number instead of a character
Nathan Binkert
2006-12-18 14:07:52 -08:00
9e7dc34383
Merge zizzer.eecs.umich.edu:/.automount/zower/eecshome/m5/newmem into zizzer.eecs.umich.edu:/z/m5/Bitkeeper/sparco3
Gabe Black
2006-12-18 12:19:30 -05:00
6841f863c5
move the twinx loads to the correct opcode and add asis 0x24 and 0x27 Make the TLB ok to translate QUAD_LDD
Ali Saidi
2006-12-18 03:37:52 -05:00
d19d7aa8a5
Minor cleanup of new snippet/subst code.
Steve Reinhardt
2006-12-17 23:09:36 -08:00
968048f56a
Convert Alpha (and finish converting MIPS) to new InstObjParam interface.
Steve Reinhardt
2006-12-17 19:27:50 -08:00
2d09f30a6d
Utilities for doing a format check for some elements of proper m5 style and fixing whitespace. For whitespace, any tabs in leading whitespace on a line are converted to spaces, and any trailing whitespace is removed.
Nathan Binkert
2006-12-17 18:58:05 -08:00
c3ec52346b
Merge zizzer:/bk/newmem into zower.eecs.umich.edu:/eecshome/m5/newmem
Gabe Black
2006-12-17 11:55:24 -05:00
81996f855a
Compilation fixes.
Gabe Black
2006-12-17 11:16:04 -05:00
729dbb60e9
Added in the extended twin load format
Gabe Black
2006-12-17 11:15:37 -05:00
c299c2562b
Started removing "CodeBlock" objects from the mips isa description.
Gabe Black
2006-12-17 10:54:17 -05:00
220e99a29b
Compilation fix after messy merge.
Gabe Black
2006-12-17 10:53:10 -05:00
91b56d03fc
Merge zizzer:/bk/newmem into zower.eecs.umich.edu:/eecshome/m5/sparcfs
Gabe Black
2006-12-16 12:55:55 -05:00
c9f18981f9
Merge zizzer:/bk/sparcfs/ into zower.eecs.umich.edu:/eecshome/m5/sparcfs
Gabe Black
2006-12-16 12:55:15 -05:00
b9d069167c
Support for twin loads.
Gabe Black
2006-12-16 12:54:28 -05:00
fe73760388
Compiler error fix.
Gabe Black
2006-12-16 12:53:01 -05:00
9d0ca61b7e
Merge zizzer:/bk/newmem into zower.eecs.umich.edu:/eecshome/m5/newmem
Gabe Black
2006-12-16 11:35:40 -05:00
f4f00c5ae9
Switch the endianness of data that's forwarded. This is the same sort of problem that was happening when stores went all the way to memory and back.
Gabe Black
2006-12-16 09:35:09 -05:00
96e5086c81
Make fetch detect when a branch is happening, rather than trying to compute when.
Gabe Black
2006-12-16 09:34:20 -05:00
a6eb16adb4
Accidently "cleaned" away the NPC parameter to the constructor.
Gabe Black
2006-12-16 07:47:33 -05:00
Ali Saidi