derek/gem5
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

Commit Graph

  • f410d5f4e0 Don't have "predict" set the predicted target of the instruction. Do that explicitly when you use predict. Gabe Black 2006-12-16 07:39:44 -05:00
  • 569e0e883b Add in constants which let you explicitly check if endian conversion would do anything. This was needed for a case where a piece of data was within a larger data type. When the larger data type was swapped, the location of the smaller data type would move. Gabe Black 2006-12-16 07:37:33 -05:00
  • c6944e320c Add in capability to return to unblocking after a squash. This is needed because if you don't squash -all- the instructions, you need to keep clearing out whatever is left in the skid buffer. Gabe Black 2006-12-16 07:35:56 -05:00
  • 244506ae12 Make sure endian conversion is done on the memory data when it's just set to an existing buffer. Gabe Black 2006-12-16 07:34:34 -05:00
  • 6413b74e4f Make the decoder use the new setup in the dyninsts for branch prediction. Gabe Black 2006-12-16 07:33:08 -05:00
  • 37b9966eb4 Made branch delay slots get squashed, and passed back an NPC and NNPC to start fetching from. Gabe Black 2006-12-16 07:32:06 -05:00
  • 4d66ddbe35 Added a predicted NPC field, explicitly stored whether the instruction was predicted taken or not. Gabe Black 2006-12-16 07:22:19 -05:00
  • 181f4f32f6 Made changes to CWP be non speculative. Gabe Black 2006-12-16 07:10:58 -05:00
  • 6aa06a26b7 Changes to the isa_parser and affected files to fix an indexing problem with split execute instructions and miscregs aliasing with integer registers. Gabe Black 2006-12-16 07:10:04 -05:00
  • 4da37bcd1b Merge zizzer:/bk/newmem into zed.eecs.umich.edu:/z/hsul/work/m5/newmem Lisa Hsu 2006-12-15 18:07:39 -05:00
  • 956e673c55 Merge zizzer:/bk/sparcfs into zed.eecs.umich.edu:/z/hsul/work/m5/newmem Lisa Hsu 2006-12-15 18:02:23 -05:00
  • 385a3ff054 small change to eliminate address range overlap. Lisa Hsu 2006-12-15 17:58:20 -05:00
  • 551ba56ae2 little fixes i noticed while searching for reason for address range issues (but these weren't the cause of the problem). Lisa Hsu 2006-12-15 17:55:47 -05:00
  • 991146218d Merge zizzer:/bk/sparcfs into zed.eecs.umich.edu:/z/hsul/work/sparc/m5 Lisa Hsu 2006-12-15 13:27:53 -05:00
  • b93b32ec33 Merge zizzer:/bk/sparcfs into zed.eecs.umich.edu:/z/hsul/work/m5/newmem Lisa Hsu 2006-12-15 13:06:37 -05:00
  • 573d59441e some small general fixes to make everythign work nicely with other ISAs, now we can merge back with newmem. exetrace.cc: wrap this variable between FULL_SYSTEM #ifs mmaped_ipr.hh: fix for build miscregfile.cc: fixes for HPSTATE access during SE mode Lisa Hsu 2006-12-15 13:05:46 -05:00
  • fbc796b347 loadstore.isa: this privilegedString is never used Lisa Hsu 2006-12-15 13:01:06 -05:00
  • 9a4370ec3b tlb.cc: fix namespace indentations Lisa Hsu 2006-12-15 12:58:02 -05:00
  • 4943d58272 Use my range_map to speed up findPort() in the bus. The snoop code could still use some work. Ali Saidi 2006-12-15 01:49:41 -05:00
  • 5e70511bff Optimized the TLB translations with some caching Ali Saidi 2006-12-15 01:48:09 -05:00
  • fa4293af33 flesh out twinx asis fix TICK register reads reduce the number of readmiscreg accesses, implement tsb pointer stuff Ali Saidi 2006-12-14 19:01:21 -05:00
  • d172e1576a Split CachePort class into CpuSidePort and MemSidePort and push those into derived Cache template class to eliminate a few layers of virtual functions and conditionals ("if (isCpuSide) { ... }" etc.). Steve Reinhardt 2006-12-13 22:04:36 -08:00
  • a10eff03a5 Merge zizzer:/bk/newmem into zed.eecs.umich.edu:/z/hsul/work/sparc/m5 Lisa Hsu 2006-12-13 17:52:24 -05:00
  • 98bb1c62b3 fix MiscRegFile::readRegWithEffect, which neglected the MISCREGS. Lisa Hsu 2006-12-13 17:51:28 -05:00
  • 0fa30e579e Merge zizzer:/bk/newmem into zed.eecs.umich.edu:/z/hsul/work/sparc/m5 Lisa Hsu 2006-12-13 14:33:59 -05:00
  • a983c4968c Merge zizzer:/bk/sparcfs into zed.eecs.umich.edu:/z/hsul/work/sparc/m5 Lisa Hsu 2006-12-13 14:33:32 -05:00
  • 5d42fd836b Merge zizzer:/bk/newmem into zed.eecs.umich.edu:/z/hsul/work/sparc/m5 Lisa Hsu 2006-12-12 21:19:51 -05:00
  • 90907f6b3c Merge zizzer:/bk/newmem/ into zower.eecs.umich.edu:/eecshome/m5/newmem Gabe Black 2006-12-12 18:10:00 -05:00
  • bc05f5982e Merge ktlim@zizzer:/bk/newmem into zamp.eecs.umich.edu:/z/ktlim2/clean/tmp/test-regress Kevin Lim 2006-12-12 17:55:50 -05:00
  • 139519ef87 Fix bugs in tlbmap (and thus rangemap since the code is nearly identical) Deal with block initializing stores (by doing nothing, at some point we might want to do the write hint 64 like thing) Fix tcc instruction igoner in legion-lock stuff to be correct in all cases Have console interrupts warn rather than panicing until we figure out what to do with interrupts Ali Saidi 2006-12-12 17:55:27 -05:00
  • c7ad7b44eb Allow for multiple redirects to happen on a single cycle (only the one for the oldest instruction is passed on to commit). Kevin Lim 2006-12-12 17:35:46 -05:00
  • 6c8c86f2f9 Rename the StaticInst-based (read|set)(Int|Float)Reg methods to (read|set)(Int|Float)RegOperand to distinguish from non-StaticInst version. Steve Reinhardt 2006-12-12 09:58:40 -08:00
  • a7ea4885ce If no tests are specified for regression, just build the binaries (instead of complaining and exiting). Steve Reinhardt 2006-12-12 09:54:59 -08:00
  • cdc3e5bc22 Get rid of unused lock code. Steve Reinhardt 2006-12-12 02:21:03 -05:00
  • 34924ce3b8 Fix up in case a req hasn't yet been generated for this instruction (if there was a fault prior to translation). Kevin Lim 2006-12-11 23:51:21 -05:00
  • 1868c9fd7f Fix for fetch to use the icache's block size to generate proper access size. Kevin Lim 2006-12-11 23:47:30 -05:00
  • f5a4b454c3 Merge zizzer.eecs.umich.edu:/z/stever/bk/newmem-head into zizzer.eecs.umich.edu:/z/stever/bk/newmem-cache3 Steve Reinhardt 2006-12-10 02:05:33 -05:00
  • fecc0dbc57 Reorder CacheTags members for better cache performance. Steve Reinhardt 2006-12-10 02:04:53 -05:00
  • 90c9ad042e Get rid of dummy 'hello world' outputs. Steve Reinhardt 2006-12-10 01:52:18 -05:00
  • fcb9a304b5 Delete parser reference outputs so that test will no longer be run. Runtimes are way too long with current inputs. Steve Reinhardt 2006-12-10 01:50:12 -05:00
  • 7b25e4091c Merge zizzer.eecs.umich.edu:/z/stever/bk/newmem-cache2 into zizzer.eecs.umich.edu:/z/stever/bk/newmem-cache3 Steve Reinhardt 2006-12-10 01:42:31 -05:00
  • 96d1efe0a9 Add '-j' option directly to regress script (passed to scons). Steve Reinhardt 2006-12-10 01:42:16 -05:00
  • cfc6710f63 Merge vm1.(none):/home/stever/bk/newmem-head into vm1.(none):/home/stever/bk/newmem-cache2 Steve Reinhardt 2006-12-09 22:05:30 -08:00
  • 4947bf276e fix lisa's hand merge Ali Saidi 2006-12-09 18:27:54 -05:00
  • 2eef266c45 Merge zizzer:/bk/sparcfs into zeep.pool:/z/saidi/work/m5.newmem Ali Saidi 2006-12-09 18:00:49 -05:00
  • 81a00fdcfe Allocate the correct number of global registers Fix fault formating and code for traps fix a couple of bugs in the decoder Cleanup/fix page table entry code Implement more mmaped iprs, fix numbered tlb insertion code, add function to dump tlb contents Don't panic if we differ from legion on a tcc instruction because of where legion prints its data and where we print our data Ali Saidi 2006-12-09 18:00:40 -05:00
  • 369e10d95a Merge zizzer:/bk/sparcfs into zed.eecs.umich.edu:/z/hsul/work/sparc/m5 Lisa Hsu 2006-12-08 15:07:26 -05:00
  • da6c1f5b09 mostly implemented SOFTINT relevant interrupt stuff. Lisa Hsu 2006-12-08 14:37:31 -05:00
  • 498e235ae0 Fixed to take into account the misc regs that became int regs. Gabe Black 2006-12-07 19:00:46 -05:00
  • ed22eb781d get legion/m5 to first tlb miss fault Ali Saidi 2006-12-07 18:50:33 -05:00
  • 97cdd5198b Compilation fixes Gabe Black 2006-12-07 18:49:10 -05:00
  • 0f8fd5fd68 Fix for squashing during a serializing instruction. Gabe Black 2006-12-07 18:47:33 -05:00
  • 41051f35ac Make branches handle the lack of a symbol table or the lack of a symbol gracefully. Gabe Black 2006-12-07 18:45:30 -05:00
  • 015873fa86 Change how Page Faults work in SPARC. It now prints the faulting address, and panics instead of fatals. This isn't technically what it should do, but it makes gdb stop at the panic rather than letting m5 exit. Gabe Black 2006-12-07 18:43:55 -05:00
  • ac32645c27 Change detault regression build from opt to fast. Steve Reinhardt 2006-12-07 14:41:56 -05:00
  • 03be92f23b Handle access to ASI_QUEUE Add function for interrupt ASIs add all the new MISCREGs to the copyMiscRegs() file Ali Saidi 2006-12-06 19:25:53 -05:00
  • ecbb8debf6 Many more fixes for SPARC_FS. Gets us to the point where SOFTINT starts getting touched. Ali Saidi 2006-12-06 14:29:10 -05:00
  • b618e733bd Fix for MIPS_SE/m5.fast compile. Kevin Lim 2006-12-06 14:23:31 -05:00
  • 50b8cce355 Use the renamed register index, rather than the flattened one. Gabe Black 2006-12-06 11:40:41 -05:00
  • f04fcf58f1 Got rid of some typedefs and moved the tlbs into the base o3 cpu. Gabe Black 2006-12-06 11:39:49 -05:00
  • 07a4e2cd36 Use the setSyscallReturn defined in arch rather than duplicating it here. Gabe Black 2006-12-06 11:38:39 -05:00
  • ef942ceecb Moved the RegIdx arrays to the base dyninst. Gabe Black 2006-12-06 11:37:39 -05:00
  • 6826ee53db Got rid of some typedefs, moved the tlbs to the base o3 cpu, and called the architecture defined setSyscallReturn function instead of a duplicate copy. Gabe Black 2006-12-06 11:36:40 -05:00
  • 0ed6c52c1e Made the alpha setSyscallReturn take a ThreadContext pointer instead of a RegFile *. Gabe Black 2006-12-06 11:33:37 -05:00
  • b3cfa6ec42 Added a flattenIntIndex function for Alpha. Gabe Black 2006-12-06 11:30:41 -05:00
  • 2dcf00bc8b Merge zizzer:/bk/newmem into zower.eecs.umich.edu:/eecshome/m5/newmem Gabe Black 2006-12-06 06:05:28 -05:00
  • be29adf51c Added a DPRINTF to print out the actual value pulled from memory. Gabe Black 2006-12-06 06:02:13 -05:00
  • 75b93179ab Flattening and syscallReturn fixes Gabe Black 2006-12-06 06:00:04 -05:00
  • 1886795368 Don't panic, but this needs to be fixed. Gabe Black 2006-12-06 05:58:07 -05:00
  • 1d7d7df315 Make syscalls flatten their register indices, and also call into the ISA's setSyscallReturn function rather than having a duplicated one. Gabe Black 2006-12-06 05:56:34 -05:00
  • 156cf0db51 Change rename to rename the flattened register index instead of the architectural one. Gabe Black 2006-12-06 05:55:23 -05:00
  • 6456cb535c Added in endianness conversion on memory accesses as the data goes out. This will break the checker! Gabe Black 2006-12-06 05:54:16 -05:00
  • 20340b5e26 Change how optional delay slot instructions are detected and squashed. Gabe Black 2006-12-06 05:51:18 -05:00
  • 8a21635eff Get rid of some typedefs which were hardly used, and move some stuff back here that shouldn't be in the architecture specific DynInst classes. Gabe Black 2006-12-06 05:48:59 -05:00
  • dc105934f3 Change to use -return_value.value like other implementations. Gabe Black 2006-12-06 05:47:19 -05:00
  • bf5f6c6430 Some changes for misc regs which were changed into unofficial integer registers, and moved the flattenIndex function into the register file. Gabe Black 2006-12-06 05:46:44 -05:00
  • 5ad1731a12 Reorganize the includes and add an include for misc.hh. Gabe Black 2006-12-06 05:45:18 -05:00
  • 643cb6dd81 Added some debug output, and made sure not to accidentally ask for the result of a store conditional. Gabe Black 2006-12-06 05:44:31 -05:00
  • a36a59e8d7 Some basic fix ups, and CWP is no longer set explicitly. Gabe Black 2006-12-06 05:43:25 -05:00
  • c541be3a48 Changed the integer register file to work with flattened indices. Gabe Black 2006-12-06 05:42:09 -05:00
  • 4d8a0541dd Change MIPS's setSyscallReturn to use a thread context. Gabe Black 2006-12-06 05:41:08 -05:00
  • a3f351ab59 Added basic flatten function for mips. Gabe Black 2006-12-06 05:40:11 -05:00
  • 54a946604b Override default SConscript options and only build the SimpleCPUs. Kevin Lim 2006-12-05 11:12:18 -05:00
  • 2e1200e57f Merge zizzer.eecs.umich.edu:bk/newmem-cache2 into vm1.(none):/home/stever/bk/newmem-cache2 Steve Reinhardt 2006-12-05 07:24:13 -08:00
  • c50965042f Merge zizzer.eecs.umich.edu:/z/stever/bk/newmem-head into zizzer.eecs.umich.edu:/z/stever/bk/newmem-cache2 Steve Reinhardt 2006-12-05 10:23:20 -05:00
  • 51b3d7f4de Merge zizzer.eecs.umich.edu:/z/stever/bk/newmem-head into zizzer.eecs.umich.edu:/z/stever/bk/newmem-cache2 Steve Reinhardt 2006-12-05 10:18:35 -05:00
  • 1c28682cea Don't compress data on writebacks unless it's actually necessary. Steve Reinhardt 2006-12-05 07:16:36 -08:00
  • 12c5bd2305 Move the SyscallReturn class into sim/syscallreturn.hh. Also move some miscregs into the integer register file so they get renamed. Gabe Black 2006-12-05 01:55:02 -05:00
  • a2c315b85f Merge vm1.(none):/home/stever/bk/newmem-head into vm1.(none):/home/stever/bk/newmem-cache2 Steve Reinhardt 2006-12-04 21:35:48 -08:00
  • 4d57cab49a forgot to commit miscreg file Ali Saidi 2006-12-04 20:29:55 -05:00
  • 8b1bcc3f52 Merge zizzer:/bk/sparcfs into zower.eecs.umich.edu:/eecshome/m5/newmemmid Gabe Black 2006-12-04 19:56:04 -05:00
  • 251f4e1134 Add in code to pass the ASI to translation. Gabe Black 2006-12-04 19:55:52 -05:00
  • 2de685cc21 Merge zizzer:/bk/sparcfs into zed.eecs.umich.edu:/z/hsul/work/sparc/m5 Lisa Hsu 2006-12-04 19:39:58 -05:00
  • 8e75b6e2a5 reogranize code to split off FS only misc regs with effect into their own file (reducing the number of if FULL_SYSTEM defines and includes) Protect other pieces of code so that sparc compiles SE again Ali Saidi 2006-12-04 19:39:57 -05:00
  • e86832bed8 automatically build sparc system or alpha system. Lisa Hsu 2006-12-04 19:37:50 -05:00
  • 6c1b311faf Merge zizzer.eecs.umich.edu:/bk/newmem into vm1.(none):/home/stever/bk/newmem-head Steve Reinhardt 2006-12-04 16:10:50 -08:00
  • 9d39407500 Update SPEC CPU2000 tests with actual benchmark output. Steve Reinhardt 2006-12-04 19:07:00 -05:00
  • 34a1f9e14e Only update stderr, stdout, m5stats.txt, and config.* on update_ref, since we don't know which of the other files are outputs and which are inputs. Steve Reinhardt 2006-12-04 19:05:09 -05:00
  • 66a9697c49 Clean up SPEC CPU2000 reference files. Get rid of reference files for o3-atomic (non-existent configuration) and mcf (doesn't seem to be working). Left in empty refs for parser/simple-timing... this appears to be dying because it's running out of memory, so maybe it will be OK once we get the memory leak fixed. Steve Reinhardt 2006-12-04 18:57:17 -05:00
  • db427bb3a9 delete m5stats which shouldn't have been commited Ali Saidi 2006-12-04 18:25:21 -05:00