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some hstick and hintp changes.

Browse Source 
src/arch/sparc/interrupts.hh:
    condition hstick matches on HINTP
src/arch/sparc/miscregfile.cc:
    implement HINTP
src/arch/sparc/ua2005.cc:
    don't post interrupt unless it is enabled.

--HG--
extra : convert_revision : f71d1c1d9fd1a898ddafd5a885c3a8d5c75e8ff0
This commit is contained in:
Lisa Hsu
2007-01-19 21:33:36 -05:00
parent 5c9cbdbb45
commit f1aeaf7ceb
3 changed files with 33 additions and 18 deletions
Download Patch File Download Diff File Expand all files Collapse all files

22
src/arch/sparc/interrupts.hh
View File

@@ -108,9 +108,11 @@ enum interrupts_t {
if (hpstate & HPSTATE::hpriv) {
if (ie) {
if (interrupts[hstick_match]) {
interrupts[hstick_match] = false;
--numPosted;
return new HstickMatch;
if (tc->readMiscReg(MISCREG_HINTP) & 1) {
interrupts[hstick_match] = false;
--numPosted;
return new HstickMatch;
}
}
if (interrupts[interrupt_vector]) {
interrupts[interrupt_vector] = false;
@@ -118,9 +120,13 @@ enum interrupts_t {
//HAVEN'T IMPLed THIS YET
return NoFault;
}
} else {
if (interrupts[hstick_match]) {
return NoFault;
}
}
} else {
if (interrupts[trap_level_zero]) {
if ((pstate & HPSTATE::tlz) && (tc->readMiscReg(MISCREG_TL) == 0)) {
interrupts[trap_level_zero] = false;
@@ -129,9 +135,11 @@ enum interrupts_t {
}
}
if (interrupts[hstick_match]) {
interrupts[hstick_match] = false;
--numPosted;
return new HstickMatch;
if (tc->readMiscReg(MISCREG_HINTP) & 1) {
interrupts[hstick_match] = false;
--numPosted;
return new HstickMatch;
}
}
if (ie) {
if (interrupts[cpu_mondo]) {

4
src/arch/sparc/miscregfile.cc
View File

@@ -214,7 +214,7 @@ MiscReg MiscRegFile::readReg(int miscReg)
case MISCREG_HTSTATE:
return htstate[tl-1];
case MISCREG_HINTP:
panic("HINTP not implemented\n");
return hintp;
case MISCREG_HTBA:
return htba;
case MISCREG_HVER:
@@ -468,7 +468,7 @@ void MiscRegFile::setReg(int miscReg, const MiscReg &val)
htstate[tl-1] = val;
break;
case MISCREG_HINTP:
panic("HINTP not implemented\n");
hintp = val;
case MISCREG_HTBA:
htba = val;
break;

25
src/arch/sparc/ua2005.cc
View File

@@ -42,10 +42,7 @@ MiscRegFile::setFSRegWithEffect(int miscReg, const MiscReg &val,
switch (miscReg) {
/* Full system only ASRs */
case MISCREG_SOFTINT:
// Check if we are going to interrupt because of something
setReg(miscReg, val);
tc->getCpuPtr()->checkInterrupts = true;
tc->getCpuPtr()->post_interrupt(hstick_match);
setReg(miscReg, val);;
if (val != 0x10000 && val != 0)
warn("Writing to softint not really supported, writing: %#x\n", val);
break;
@@ -53,6 +50,8 @@ MiscRegFile::setFSRegWithEffect(int miscReg, const MiscReg &val,
case MISCREG_SOFTINT_CLR:
return setRegWithEffect(MISCREG_SOFTINT, ~val & softint, tc);
case MISCREG_SOFTINT_SET:
tc->getCpuPtr()->checkInterrupts = true;
tc->getCpuPtr()->post_interrupt(soft_interrupt);
return setRegWithEffect(MISCREG_SOFTINT, val | softint, tc);
case MISCREG_TICK_CMPR:
@@ -96,6 +95,9 @@ MiscRegFile::setFSRegWithEffect(int miscReg, const MiscReg &val,
case MISCREG_HVER:
panic("Shouldn't be writing HVER\n");
case MISCREG_HINTP:
setReg(miscReg, val);
case MISCREG_HTBA:
// clear lower 7 bits on writes.
setReg(miscReg, val & ULL(~0x7FFF));
@@ -204,9 +206,11 @@ MiscRegFile::processSTickCompare(ThreadContext *tc)
if (ticks == 0) {
DPRINTF(Timer, "STick compare cycle reached at %#x\n",
(stick_cmpr & mask(63)));
tc->getCpuPtr()->post_interrupt(soft_interrupt);
tc->getCpuPtr()->checkInterrupts = true;
softint |= ULL(1) << 16;
if (!(tc->readMiscReg(MISCREG_STICK_CMPR) & (ULL(1) << 63))) {
tc->getCpuPtr()->post_interrupt(soft_interrupt);
tc->getCpuPtr()->checkInterrupts = true;
setRegWithEffect(MISCREG_SOFTINT, softint | (ULL(1) << 16), tc);
}
} else
sTickCompare->schedule(ticks * tc->getCpuPtr()->cycles(1) + curTick);
}
@@ -225,8 +229,11 @@ MiscRegFile::processHSTickCompare(ThreadContext *tc)
if (ticks == 0) {
DPRINTF(Timer, "HSTick compare cycle reached at %#x\n",
(stick_cmpr & mask(63)));
tc->getCpuPtr()->post_interrupt(hstick_match);
tc->getCpuPtr()->checkInterrupts = true;
if (!(tc->readMiscReg(MISCREG_HSTICK_CMPR) & (ULL(1) << 63))) {
setRegWithEffect(MISCREG_HINTP, 1, tc);
tc->getCpuPtr()->post_interrupt(hstick_match);
tc->getCpuPtr()->checkInterrupts = true;
}
// Need to do something to cause interrupt to happen here !!! @todo
} else
sTickCompare->schedule(ticks * tc->getCpuPtr()->cycles(1) + curTick);