Modify ISA and staticInst to support a IsFirstMicroOp flag

Increment instruction count on first micro-op instead of last

src/arch/sparc/isa/decoder.isa:
    Implement a twin load for ASI_LDTX_P(0xe2)
src/arch/sparc/isa/formats/mem/blockmem.isa:
    set the new flag IsFirstMicroOp when needed
src/cpu/simple/atomic.cc:
    Increment instruction count on first micro-op instead of last (because if we take a fault on a micro coded instruction it should be counted twice acording to legion)
src/cpu/static_inst.hh:
    Add IsFirstMicroop flag to static insts

--HG--
extra : convert_revision : 02bea93d38c03bbafe4570665eb4c01c11caa2fc

src/arch/sparc/isa/decoder.isa

@@ -1079,6 +1079,9 @@ decode OP default Unknown::unknown()
                 //ASI_LDTX_N_L
                 0x2F: TwinLoad::ldtx_n_l(
                     {{RdTwin.udw = Mem.udw}}, {{EXT_ASI}});
+                //ASI_LDTX_P
+                0xE2: TwinLoad::ldtx_p(
+                    {{RdTwin.udw = Mem.udw}}, {{EXT_ASI}});
                 default: ldtwa({{
                         uint64_t val = Mem.udw;
                         RdLow = val<31:0>;

src/arch/sparc/isa/formats/mem/blockmem.isa

@@ -1,4 +1,4 @@
-// Copyright (c) 2006 The Regents of The University of Michigan
+// Copyright (c) 2006-2007 The Regents of The University of Michigan
 // All rights reserved.
 //
 // Redistribution and use in source and binary forms, with or without
@@ -451,6 +451,8 @@ let {{
             flag_code = ''
             if (microPc == 7):
                 flag_code = "flags[IsLastMicroOp] = true;"
+            elif (microPc == 0):
+                flag_code = "flags[IsDelayedCommit] = true; flags[IsFirstMicroOp] = true;"
             else:
                 flag_code = "flags[IsDelayedCommit] = true;"
             pcedCode = matcher.sub("Frd_%d" % microPc, code)
@@ -492,7 +494,7 @@ let {{
                 flag_code = "flags[IsLastMicroOp] = true;"
                 pcedCode = matcher.sub("RdHigh", code)
             else:
-                flag_code = "flags[IsDelayedCommit] = true;"
+                flag_code = "flags[IsDelayedCommit] = true; flags[IsFirstMicroOp] = true;"
                 pcedCode = matcher.sub("RdLow", code)
             iop = InstObjParams(name, Name, 'TwinMem', pcedCode,
                     opt_flags, {"ea_code": addrCalcReg,

src/cpu/simple/atomic.cc

@@ -497,7 +497,7 @@ AtomicSimpleCPU::tick()
 
             // @todo remove me after debugging with legion done
             if (curStaticInst && (!curStaticInst->isMicroOp() ||
-                        curStaticInst->isLastMicroOp()))
+                        curStaticInst->isFirstMicroOp()))
                 instCnt++;
 
             if (simulate_stalls) {

src/cpu/static_inst.hh

@@ -146,6 +146,7 @@ class StaticInstBase : public RefCounted
         IsMicroOp,	///< Is a microop
         IsDelayedCommit,	///< This microop doesn't commit right away
         IsLastMicroOp,	///< This microop ends a microop sequence
+        IsFirstMicroOp,	///< This microop begins a microop sequence
         //This flag doesn't do anything yet
         IsMicroBranch,	///< This microop branches within the microcode for a macroop
 
@@ -244,6 +245,7 @@ class StaticInstBase : public RefCounted
     bool isMicroOp() const { return flags[IsMicroOp]; }
     bool isDelayedCommit() const { return flags[IsDelayedCommit]; }
     bool isLastMicroOp() const { return flags[IsLastMicroOp]; }
+    bool isFirstMicroOp() const { return flags[IsFirstMicroOp]; }
     //This flag doesn't do anything yet
     bool isMicroBranch() const { return flags[IsMicroBranch]; }
     //@}