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  • 7a4d75bae3 CPU: Refactor read/write in the simple timing CPU. Gabe Black 2008-11-13 23:30:37 -08:00
  • bcfd284d24 X86: Update the mcf stats. I must have missed updating these for the change to send both parts of a split packet at the same time. Gabe Black 2008-11-13 23:30:15 -08:00
  • 4d64d7664c SCons: Allow top level directory of EXTRAS able to contain SConscripts. The current EXTRAS will fail if the top level directory pointed to by EXTRAS has a SConscript file in it. We allow this by including the directory name of the EXTRA in the build directory which prevents a clash between src/SConscript and extra/SConscript. Maintain compatibility with older uses of EXTRAS by adding a -I for each top level extra directory. Nathan Binkert 2008-11-10 11:51:18 -08:00
  • eb5d9ba72b pseudo inst: Add rpns (read processor nanoseconds) instruction. This instruction basically returns the number of nanoseconds that the CPU has been running. Nathan Binkert 2008-11-10 11:51:18 -08:00
  • c25d966b06 Clean up the SimpleTimingPort class a little bit. Move the constructor into the .cc file and get rid of the typedef for SendEvent. Nathan Binkert 2008-11-10 11:51:18 -08:00
  • ea70a44c9f clean: Move some stuff from the hh file to the cc file. Nathan Binkert 2008-11-10 11:51:18 -08:00
  • 4e02e7c217 python: Fix the reference counting for python events placed on the eventq. We need to add a reference when an object is put on the C++ queue, and remove a reference when the object is removed from the queue. This was not happening before and caused a memory problem. Nathan Binkert 2008-11-10 11:51:18 -08:00
  • 1adfe5c7f3 O3CPU: Make the instcount debugging stuff per-cpu. This is to prevent the assertion from firing if you have a large multicore. Also make sure that it's not compiled in when NDEBUG is defined Clint Smullen 2008-11-10 11:51:18 -08:00
  • 9c49bc7b00 mem: update stuff for changes to Packet and Request Nathan Binkert 2008-11-10 11:51:17 -08:00
  • 3535d746ab style: clean up the Packet stuff Nathan Binkert 2008-11-10 11:51:17 -08:00
  • 2dd699ed3d flags: Provide an object for managing boolean flags for an object. In many cases it might be preferable to use bitset, but this object allows the user more easily manipulate groups of flags because the underlying type (e.g. uint64_t) is exposed. Nathan Binkert 2008-11-10 11:51:17 -08:00
  • 194f0310d3 safe_cast: add a new cast function for casts that should always succeed. In DEBUG mode, this does a dynamic_cast and asserts that the result is non null. Otherwise, it just does a static_cast. Again, this is only intended for cases where the cast should always succeed and what's desired is a debugging check to make sure. Nathan Binkert 2008-11-10 11:51:17 -08:00
  • 27e8f3c98a DmaDevice: fix minor type in error message. Steve Reinhardt 2008-11-10 14:45:31 -08:00
  • 63127cbf37 mem: Assert that requests have non-negative size. Would have saved me much debugging time if these had been in there previously. Steve Reinhardt 2008-11-10 14:11:07 -08:00
  • 42bd460d7f Cache: Refactor packet forwarding a bit. Makes adding write-through operations easier. Steve Reinhardt 2008-11-10 14:10:28 -08:00
  • c981b7ed50 X86: Add x86 reference output for the timing CPU. Gabe Black 2008-11-09 21:57:15 -08:00
  • 846cb450f9 CPU: Make unaligned accesses work in the timing simple CPU. Gabe Black 2008-11-09 21:56:28 -08:00
  • 8c15518f30 X86: Fix completeAcc get call. Gabe Black 2008-11-09 21:55:43 -08:00
  • 909380f3ee X86: Make the timing simple CPU handle variable length instructions. Gabe Black 2008-11-09 21:55:01 -08:00
  • 72743e5020 tracediff: add '#' support for sub-arg alternatives, '-n' param Steve Reinhardt 2008-11-06 20:23:05 -08:00
  • 92714e529f Automated merge with ssh://daystrom.m5sim.org//repo/m5 Lisa Hsu 2008-11-06 11:11:50 -05:00
  • ddd179a418 Reference updates. Since split cache is gone, a lot of config.ini changes, and minor changes to stats that are likely due to the decoupling of insertions/evictions in the cache. Lisa Hsu 2008-11-06 11:11:42 -05:00
  • be679b8e5e Automated merge with ssh://m5sim.org//repo/m5 Lisa Hsu 2008-11-05 18:12:21 -05:00
  • 2435918ac2 new mp eio test Lisa Hsu 2008-11-05 18:10:30 -05:00
  • 44839d6b71 Fix a few more places where the context stuff wasn't changed Nathan Binkert 2008-11-05 07:20:03 -08:00
  • 46b56bb7b6 Fix SPARC_FS compile Lisa Hsu 2008-11-05 16:19:17 -05:00
  • 07969dbbf1 Right now a single thread cpu 1 could get assigned context Id != 1, depending on the order in which it's registered with the system. To make them match, here is a little change. Lisa Hsu 2008-11-05 15:30:49 -05:00
  • c68032ddcb decouple eviction from insertion in the cache. Lisa Hsu 2008-11-04 11:35:58 -05:00
  • 4ab52cb986 Change the findBlock(addr, lat) to accessBlock, which I think has better connotations for what is really happening and how it should be used. Lisa Hsu 2008-11-04 11:35:57 -05:00
  • dd99ff23c6 get rid of all instances of readTid() and getThreadNum(). Unify and eliminate redundancies with threadId() as their replacement. Lisa Hsu 2008-11-04 11:35:42 -05:00
  • d857faf073 Add in Context IDs to the simulator. From now on, cpuId is almost never used, the primary identifier for a hardware context should be contextId(). The concept of threads within a CPU remains, in the form of threadId() because sometimes you need to know which context within a cpu to manipulate. Lisa Hsu 2008-11-02 21:57:07 -05:00
  • 67fda02dda Make it so that all thread contexts are registered with the System, even in SE. Process still keeps track of the tc's it owns, but registration occurs with the System, this eases the way for system-wide context Ids based on registration. Lisa Hsu 2008-11-02 21:57:06 -05:00
  • c55a467a06 make BaseCPU the provider of _cpuId, and cpuId() instead of being scattered across the subclasses. generally make it so that member data is _cpuId and accessor functions are cpuId(). The ID val comes from the python (default -1 if none provided), and if it is -1, the index of cpuList will be given. this has passed util/regress quick and se.py -n4 and fs.py -n4 as well as standard switch. Lisa Hsu 2008-11-02 21:56:57 -05:00
  • f4bceb9760 Libelf: Append options to CCFLAGS for warning free libelf compile instead of deleting CCFLAGS. Should fix 64bit OS X compile problem. Ali Saidi 2008-10-28 21:13:21 -04:00
  • 95af120e60 CPU: The API change to EventWrapper did not get propagated to the entirety of TimingSimpleCPU. The constructor no-longer schedules an event at construction and the implict conversion between int and bool was allowing the old code to compile without warning. Clint Smullen 2008-10-27 18:18:04 -04:00
  • cfa32d8de7 Checkpointing: createCountedDrain function, it was only returning an Event, which does not expose a setCount method to Python. Clint Smullen 2008-10-27 19:46:01 -04:00
  • aadae0b06e BATCH: Run as, ar, and ranlib with BATCH_CMD so that they execute on the batch hosts, not local host. Ali Saidi 2008-10-26 14:45:47 -04:00
  • 8788d703f8 s/cpu_id/cpuId in o3 (to be consistent and match style), also fix some typos in comments. Lisa Hsu 2008-10-23 16:49:17 -04:00
  • 546a6c0c1b probe function no longer used anywhere. Lisa Hsu 2008-10-23 16:49:13 -04:00
  • 7a28ab2d18 remove the totally obsolete split cache Lisa Hsu 2008-10-23 16:11:28 -04:00
  • 9836d81c2b style: Use the correct m5 style for things relating to interrupts. Nathan Binkert 2008-10-21 07:12:53 -07:00
  • aac93b7d0c Regression: Add single and dual boot O3 regressions. They both take about 8 minutes to complete. Ali Saidi 2008-10-20 19:00:07 -04:00
  • b760b99f4d O3CPU: Undo Gabe's changes to remove hwrei and simpalcheck from O3 CPU. Removing hwrei causes the instruction after the hwrei to be fetched before the ITB/DTB_CM register is updated in a call pal call sys and thus the translation fails because the user is attempting to access a super page address. Ali Saidi 2008-10-20 16:22:59 -04:00
  • 4fac54f227 Automated merge with ssh://daystrom.m5sim.org//z/repo/m5 Lisa Hsu 2008-10-19 22:50:53 -04:00
  • 9b8011e255 need to add packet_access.hh in order to get tempalte definition Nathan Binkert 2008-10-16 22:22:47 -07:00
  • 81f5da1e89 get rid of local variable that's only used in an assert so fast compiles Nathan Binkert 2008-10-16 22:22:17 -07:00
  • 101c2d9174 Automated merge with ssh://daystrom.m5sim.org//z/repo/m5 Lisa Hsu 2008-10-16 14:16:26 -04:00
  • 90e40ca982 This function declaration isn't used anywhere. HG: user: Lisa Hsu <hsul@eecs.umich.edu> HG: branch default HG: changed src/mem/cache/cache.hh Lisa Hsu 2008-10-14 17:22:03 -04:00
  • 5b07448cf1 eventq: make python events actually work Nathan Binkert 2008-10-14 09:34:11 -07:00
  • ff2eea1ba3 eventq: revert code for unserializing events. Since I never implemented a proper solution, put it back to something that at least works for now. Once I add more event queues, I'll have to really fix this though Nathan Binkert 2008-10-14 09:33:52 -07:00
  • 809f6cb6d1 CPU: Explain why some code is commented out. Gabe Black 2008-10-12 23:52:02 -07:00
  • 34ca72d16d Get rid of some commented out code. Gabe Black 2008-10-12 23:50:22 -07:00
  • 3c4567f2a6 X86: Set the delayed commit flag in x86 microops appropriately. Gabe Black 2008-10-12 23:29:10 -07:00
  • 33ebd04474 X86: Make the local APIC timer event generate an interrupt. Gabe Black 2008-10-12 23:28:49 -07:00
  • bdc28d793d X86: Implement the EOI register in the local APIC. Gabe Black 2008-10-12 23:28:11 -07:00
  • fd37688294 X86: Add some DPRINTFs to the local APIC. Gabe Black 2008-10-12 23:27:45 -07:00
  • be6055e0f2 X86: Make auto eoi mode work in the I8259 PIC. Gabe Black 2008-10-12 23:27:08 -07:00
  • fb5bb434a9 X86: Make non-specific EOI commands work. Gabe Black 2008-10-12 23:25:48 -07:00
  • 8e664f3959 X86: Make the I8259 PIC accept a specific EOI command. Gabe Black 2008-10-12 23:22:58 -07:00
  • e3004c579f X86: Fix the segment setting code in IRET, and make it restore the flags. Gabe Black 2008-10-12 23:05:22 -07:00
  • 349a155b6e X86: Panic when an unimplemented fault is invoked, rather than spinning forever Gabe Black 2008-10-12 23:00:28 -07:00
  • 564eda827b X86: Implement the swapgs instruction. Gabe Black 2008-10-12 23:00:07 -07:00
  • a2e0d539d8 X86: Add wrval/rdval microops for reading significant miscregs. Gabe Black 2008-10-12 22:55:55 -07:00
  • 9e8e2f9ec6 X86: Make the x86 interrupt fault kick off the interrupt microcode. Gabe Black 2008-10-12 22:42:10 -07:00
  • 4c19c56a77 X86: Implement entering an interrupt in microcode. Gabe Black 2008-10-12 22:42:03 -07:00
  • f813a4be49 X86: Make sure register microops set fault rather than returning one. Gabe Black 2008-10-12 22:24:06 -07:00
  • 961b40cdb5 X86: Implement an wrdh microop which loads bases/offsets from 16 byte descriptors. Gabe Black 2008-10-12 22:16:53 -07:00
  • 989fa4fc0f X86: Make the MicroPC type 16 bit. Gabe Black 2008-10-12 20:48:24 -07:00
  • 6074b1abf2 X86: Implement local labels for the ROM that actually refer into the ROM. Gabe Black 2008-10-12 20:44:11 -07:00
  • 6b46e5204d X86: Implement the chks check of interrupt gate target code segments. Gabe Black 2008-10-12 20:38:22 -07:00
  • 30feb90c1c X86: Add a check type for interrupt gates. Gabe Black 2008-10-12 20:33:37 -07:00
  • 15f5bb3055 X86: Fix chks checking the submode for stack segments. Gabe Black 2008-10-12 20:29:52 -07:00
  • 9e1fe2050a X86: Let segment manipulation microops be conditional. Gabe Black 2008-10-12 20:25:06 -07:00
  • e9158d763a X86: Let the microassembler know about the microcode only H segment. Gabe Black 2008-10-12 20:17:38 -07:00
  • 223fc41c07 X86: Fix the rdbase microop Gabe Black 2008-10-12 20:07:46 -07:00
  • 0756dbb37a X86: Don't fetch in the simple CPU if you're in the ROM. Gabe Black 2008-10-12 19:32:06 -07:00
  • f245358343 Get rid of old RegContext code. Gabe Black 2008-10-12 17:57:46 -07:00
  • cefb768131 X86: Create a handy way to access labels from the ROM in microcode. Gabe Black 2008-10-12 17:52:51 -07:00
  • e5f8092467 X86: Make X86's microcode ROM actually do something. Gabe Black 2008-10-12 17:48:44 -07:00
  • c9ea0b7349 CPU: Make the highest order bit in the micro pc determine if it's combinational or from the ROM. Gabe Black 2008-10-12 16:59:55 -07:00
  • 2736086d7c CPU: Create a microcode ROM object in the CPU which is defined by the ISA. Gabe Black 2008-10-12 15:59:21 -07:00
  • 6fd4eff68f X86: Create an eret microop which returns from ROM to combinational decoding. Gabe Black 2008-10-12 15:53:04 -07:00
  • 4aa18aa800 X86: Make Br never report itself as the last microop. Gabe Black 2008-10-12 15:43:35 -07:00
  • 77c0e1d110 X86: Create a SeqOp class of microops and make Br one of them. Gabe Black 2008-10-12 15:33:17 -07:00
  • 8384ff7d6c X86: Update the stats for cpuid's new implementation Gabe Black 2008-10-12 15:31:37 -07:00
  • a76c4b8ca1 X86: Implement CPUID with a magical function instead of microcode. Gabe Black 2008-10-12 15:31:28 -07:00
  • d0a43ce2b2 X86: Fix the ordering of special physical address ranges. Gabe Black 2008-10-12 14:01:06 -07:00
  • 3a1905157e X86: Create a mechanism for the IO APIC to access I8259 vectors. Gabe Black 2008-10-12 13:54:57 -07:00
  • c35da8e495 X86: Actually use the extra vector bits we get from ICW2. Gabe Black 2008-10-12 13:51:48 -07:00
  • ec9d3aad71 X86: Make the local APIC process interrupts and send them to the CPU. Gabe Black 2008-10-12 13:45:21 -07:00
  • 876f4845f2 X86: Make the local APIC handle interrupt messages from the IO APIC. Gabe Black 2008-10-12 13:44:24 -07:00
  • 4d5c7f7038 X86: Change the default value for the IO APIC redirection table. Gabe Black 2008-10-12 13:35:26 -07:00
  • 3420ad7644 X86: Make the bases for x86 fault class public. Gabe Black 2008-10-12 13:29:26 -07:00
  • 557bde43c3 X86: Make APICs communicate through the memory system. Gabe Black 2008-10-12 13:28:54 -07:00
  • e459013182 Create a message port for sending messages as apposed to reading/writing a memory range. Gabe Black 2008-10-12 12:08:51 -07:00
  • e0f137a87c X86: Add a LocalApic trace flag. Gabe Black 2008-10-12 12:07:25 -07:00
  • 42ebebf99a X86: Make the local APIC accessible through the memory system directly, and make the timer work. Gabe Black 2008-10-12 11:08:00 -07:00
  • d9f9c967fb Turn Interrupts objects into SimObjects. Also, move local APIC state into x86's Interrupts object. Gabe Black 2008-10-12 09:09:56 -07:00
  • c4f1cc3b48 CPU: Eliminate the get_vec function. Gabe Black 2008-10-12 08:24:09 -07:00
  • 0c3848732e CPU: Add a getInterruptController function Gabe Black 2008-10-11 16:13:58 -07:00