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X86: Add wrval/rdval microops for reading significant miscregs.

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Gabe Black
2008-10-12 22:55:55 -07:00
parent 9e8e2f9ec6
commit a2e0d539d8
3 changed files with 25 additions and 2 deletions
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5
src/arch/x86/isa/microasm.isa
View File

@@ -159,6 +159,11 @@ let {{
assembler.symbols["CTrue"] = "ConditionTests::True"
assembler.symbols["CFalse"] = "ConditionTests::False"
for reg in ('sysenter_cs', 'sysenter_esp', 'sysenter_eip',
'star', 'lstar', 'cstar', 'sf_mask',
'kernel_gs_base'):
assembler.symbols[reg] = "MISCREG_%s" % reg.upper()
# Code literal which forces a default 64 bit operand size in 64 bit mode.
assembler.symbols["oszIn64Override"] = '''
if (machInst.mode.submode == SixtyFourBitMode &&

16
src/arch/x86/isa/microops/regop.isa
View File

@@ -1028,6 +1028,22 @@ let {{
DestReg = SegSelSrc1;
'''
class Rdval(RegOp):
def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"):
super(Rdval, self).__init__(dest, \
src1, "NUM_INTREGS", flags, dataSize)
code = '''
DestReg = MiscRegSrc1;
'''
class Wrval(RegOp):
def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"):
super(Wrval, self).__init__(dest, \
src1, "NUM_INTREGS", flags, dataSize)
code = '''
MiscRegDest = SrcReg1;
'''
class Chks(RegOp):
def __init__(self, dest, src1, src2=0,
flags=None, dataSize="env.dataSize"):

6
src/arch/x86/isa/operands.isa
View File

@@ -153,7 +153,9 @@ def operands {{
'GDTRLimit': ('ControlReg', 'uqw', 'MISCREG_TSG_LIMIT', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 206),
'CSBase': ('ControlReg', 'udw', 'MISCREG_CS_EFF_BASE', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 207),
'CSAttr': ('ControlReg', 'udw', 'MISCREG_CS_ATTR', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 208),
'TscOp': ('ControlReg', 'udw', 'MISCREG_TSC', (None, None, ['IsSerializeAfter', 'IsSerializing', 'IsNonSpeculative']), 209),
'M5Reg': ('ControlReg', 'udw', 'MISCREG_M5_REG', (None, None, None), 210),
'MiscRegDest': ('ControlReg', 'uqw', 'dest', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 209),
'MiscRegSrc1': ('ControlReg', 'uqw', 'src1', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 210),
'TscOp': ('ControlReg', 'udw', 'MISCREG_TSC', (None, None, ['IsSerializeAfter', 'IsSerializing', 'IsNonSpeculative']), 211),
'M5Reg': ('ControlReg', 'udw', 'MISCREG_M5_REG', (None, None, None), 212),
'Mem': ('Mem', 'uqw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 300)
}};