Adds a new config script to configure the MI_example protocol. This script
closely follows the script used for MSI, but instead supports the
MI_example protocol. This script works with the simple_ruby runscript and
can be included instead of msi_caches.
Change-Id: I8be0be67bf51369763ba103a5f101cfc01ad8859
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/8945
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Adds the required configuration files to run the MSI protocol. These
config files are much simpler than the current Ruby examples and follow
the pattern in the other Learning gem5 run scripts.
By default, this script runs with two CPUs and runs the recently added
thread test binary.
Currently, only SE mode is supported.
This code follows Learning gem5 Part 3.
http://learning.gem5.org/book/part3/index.html
Change-Id: I813a3153d49e47198444c38a6af30269bd1310cd
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/8943
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Replacement policies (LRU, Random) are currently considered as array
indexing methods, but have completely different functionalities:
- Array indexers determine the possible locations for block allocation.
This information is used to generate replacement candidates when
conflicts happen.
- Replacement policies determine which of the replacement candidates
should be evicted to make room for new allocations.
For this reason, they were split into different classes. Advantages:
- Easier and more straightforward to implement other replacement
policies (RRIP, LFU, ARC, ...)
- Allow easier future implementation of cache organization schemes
As now we can't assure the use of sets, the previous way to create a
true LRU is not viable. Now a timestamp_bits parameter controls how
many bits are dedicated for the timestamp, and a true LRU can be
achieved through an infinite number of bits (although a few bits suffice
in practice).
Change-Id: I23750db121f1474d17831137e6ff618beb2b3eda
Reviewed-on: https://gem5-review.googlesource.com/8501
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Prior to this changeset the bootloader rom (instantiated as a
SimpleMemory) in ruby Arm systems was treated as an IO device and it
was fronted by a DMA controller. This changeset moves the bootloader
rom and adds it to the system as another memory with a dedicated
directory controller.
Change-Id: I094fed031cdef7f77a939d94f948d967b349b7e0
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/8741
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
This changeset updates the lat_mem_rd.py to configure the L3Cache
using the split tag_latency, data_latency parameters.
Change-Id: I8bc41d5f7664111bdda0972356d1a17762aa77e5
Reviewed-on: https://gem5-review.googlesource.com/8288
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
We have not added the --generate-dtb option for non-ARM systems and
hence this case becomes dead code. It also leads to error on non-ARM
systems as is tries to access a non existent field.
Change-Id: Ia926bd0c61efa275bc5e3864b8a9c3ffb7aa3cb5
Signed-off-by: Nayan Deshmukh <nayan26deshmukh@gmail.com>
Reviewed-on: https://gem5-review.googlesource.com/7801
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Equips the fs.py config routine with an extra commandline option
--generate-dtb that will generate a dtb file automatically before
running the simulation. Only works with ARM systems and gives a warning
if the simulated system is not of --machine-type VExpress_GEM5_V1.
Change-Id: I7766e5459fd9bec2245de83cef103091ebaf7229
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/5968
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
commit 8ad26e2688
cpu: Don't override ISA if provided by user
removed the default ISA from the BaseCPU, and instead relies on
createThreads() to initiate a default ISA if none is specified. the apu_se.py
script, however does not call creatThreads() leading to a fatal when
constructing CPU objects. this patch adds the appropriate calls to
createThreads() inside apu_se.py.
Change-Id: I16a5929454c59d68a3f1b7b3858c48a70cb76412
Reviewed-on: https://gem5-review.googlesource.com/7101
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Michael LeBeane <Michael.Lebeane@amd.com>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
The format of AddrRange parameters was changed, but
config/example/read_config.py wasn't updated for the new format.
Change-Id: Ie0da7aaa47c827bacc2b4f7f44929efd868b8794
Reviewed-on: https://gem5-review.googlesource.com/6942
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Ruby has no support for atomic_noncaching accesses, which prevents using
it with kvm-cpu. This patch fixes this by directly forwarding atomic
requests from the ruby port/sequencer to the corresponding directory
based on the destination address of the packet.
Change-Id: I0b4928bfda44fd9e5e48583c51d1ea422800da2d
Reviewed-on: https://gem5-review.googlesource.com/5601
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Bradford Beckmann <brad.beckmann@amd.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Bradford Beckmann <brad.beckmann@amd.com>
Since BaseCPU.createThreads() no longer overrides the BaseCPU.isa
parameter, switch_cpus should have the ISA copied. This fixes a
fatal error in BaseCPU when restoring from a checkpoint.
Change-Id: I4fdcacb76da46bdbe1ce37dcf05c5a6a8a9e5237
Signed-off-by: Austin Harris <austinharris@utexas.edu>
Reviewed-on: https://gem5-review.googlesource.com/6241
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
This patch adds two regression tests that execute the script in the
configs dir for triggering low power mode transitions. A separate
test is required for each page policy because for close-adaptive
page policy the DRAM goes into the Precharge Power-down mode while
for open-adaptive page policy it goes into the Activate Power-down
mode.
Change-Id: Iad61af23f132db046f2857cc3ef64b2bf42cf5e4
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/5726
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
This change adds a Python script to sweep a few parameters with a
goal to trigger transitions to the low power states of the DRAM
controller.
This script is largely based on the sweep.py but is helpful to study
the impact of inter-transaction delay on the behaviour of the DRAM
in addition to typical sweep params like stride size, bank
utilization and read percent. An idle period is added as the last
traffic generator state to target hitting self-refresh.
Change-Id: I34380afffbf2de9f4e997dfe9fff5e615e077524
Reviewed-by: Wendy Elsasser <wendy.elsasser@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/5725
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
These functions were already being treated as psuedo objects and had
properties assigned to them setting what their paths were. That's a bit
unusual and made it less obvious what the code was doing, but also
forced the "system" function to know what all the possible path
searching functions were so that they'd have their "path" property
initialized properly in a central location.
This change introduces a PathSearcFunc class which encapsulates the
mechanisms of the old code and makes it implicitly extensible so that
other path searching functions which might look in other directories
can be added in other places.
Change-Id: I7be28e51481a06ec83997677af99927709b18003
Reviewed-on: https://gem5-review.googlesource.com/5341
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
The change "config: Change mem_range attribute naming in ARM
SimpleSystem" modified the SimpleSystem class to be compatible with
the MemConfig utility script. While doing so, the way we report the
memory ranges supported by the system changed, which broke the bL
example configration. This changeset introduces the necessary changes
to make the script work again.
Change-Id: I789987950ff04b6c5ae1c8b807355bcba34f6b3c
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/4380
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
The ARM example configs used to rely on CPU aliases for the
AtomicSimpleCPU and KVM when configuring clusters. This broken when
support for CPU aliases was removed ('config: Remove support for CPU
aliases.'). This change updates the config scripts to use the full
class names instead.
Change-Id: If36c46207f39ca1897ecf77d9588f1c059819e63
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/4360
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Old ARM systems used to pass the machine type in the ATAGS list passed
to the kernel. This has been largely deprecated by the introduction of
device trees. Switch to the DTOnly machine type by default in gem5
since all new platforms and kernel will require this behavior.
Change-Id: Icfd085e4862863b4ef495566bfddbd11591866c3
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/4260
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
The CpuConfig helper currently assumes that all timing models live in
the cores.arm package. This ignores the potential mismatch between the
target ISA and the ISA assumptions made by the timing models.
Instead of unconditionally listing all CPU models in cores.arm, list
timing models from cores.generic and cores.${TARGET_ISA}. This ensures
that the listed timing models support the ISA that gem5 is targeting.
Change-Id: If6235af2118889638f56ac4151003f38edfe9485
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/3947
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
The High-Performance In-order (HPI) CPU timing model is tuned to be
representative of a modern in-order ARMv8-A implementation. The HPI
core and its supporting simulation scripts, namely starter_se.py and
starter_fs.py (under /configs/example/arm/) are part of the ARM
Research Starter Kit on System Modeling. More information can be found
at: http://www.arm.com/ResearchEnablement/SystemModeling
Change-Id: I124bd06ba42d20abff09d447542b031d17eabe22
Signed-off-by: Ashkan Tousi <ashkan.tousimojarad@arm.com>
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/4201
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
MemConfig.config() expects memory ranges to be defined in a particular
way. This patch changes the naming of the mem_range attribute in
SympleSystem to enable use of MemConfig for configuring the memory.
Change-Id: I4964c136e53a99c69ff5e086cacb929aa435168d
Signed-off-by: Gabor Dozsa <gabor.dozsa@arm.com>
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/4200
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Assign different pids to the different commands specified with the "--cmd"
flag to configs/example/se.py
Without this change, the following command line triggers
a "fatal: _pid 100 is already used" error:
command=$PWD/tests/test-progs/hello/bin/arm/linux/hello
./build/ARM/gem5.opt configs/example/se.py -n 2 -c "$command;$command"
Change-Id: If6f726481eb196d4f42680b6aa46364fce4190ed
Signed-off-by: Pau Cabre <pau.cabre@metempsy.com>
Reviewed-on: https://gem5-review.googlesource.com/4160
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
Maintainer: Brandon Potter <Brandon.Potter@amd.com>
This patch adds some more functionality to the cpu model and the arch to
interface with the vector register file.
This change consists mainly of augmenting ThreadContexts and ExecContexts
with calls to get/set full vectors, underlying microarchitectural elements
or lanes. Those are meant to interface with the vector register file. All
classes that implement this interface also get an appropriate implementation.
This requires implementing the vector register file for the different
models using the VecRegContainer class.
This change set also updates the Result abstraction to contemplate the
possibility of having a vector as result.
The changes also affect how the remote_gdb connection works.
There are some (nasty) side effects, such as the need to define dummy
numPhysVecRegs parameter values for architectures that do not implement
vector extensions.
Nathanael Premillieu's work with an increasing number of fixes and
improvements of mine.
Change-Id: Iee65f4e8b03abfe1e94e6940a51b68d0977fd5bb
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
[ Fix RISCV build issues and CC reg free list initialisation ]
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/2705
When importing the cores.arm package, we currently throw an exception
if a timing model can't be imported due to a missing dependency (e.g.,
the required CPU model wasn't included in the build). This is
undesirable since it prevents other, working, timing models from being
added to the package. Wrap the import_module call in a try-except
block and skip timing models that have missing dependencies.
Change-Id: I92bab62c989f433a8a4a7bf59207d9d81b3d19e1
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/3946
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
The ex5_LITTLE and ex5_big configs currently depend on Caches.py and
O3_ARM_v7a.py. These aren't actual dependencies since all of the
params from the caches and the old O3 model are overridden. This
changeset updates the ex5 models to derive from the base SimObjects
instead.
Change-Id: I999e73bb9cc21ad96865c1bc0dd5973faa48ab61
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Gabor Dozsa <gabor.dozsa@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/3942
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
MemConfig currently assumes that all callers include the its full set
of options in the command line parser. This is unnecessary and
sometimes confusing. Make most of the options optional to avoid having
to add all of them to example scripts.
Change-Id: I2d73be2454427b00db16716edcfd96a47133c888
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Gabor Dozsa <gabor.dozsa@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/3940
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Ruby for ARM systems is not fully supported but certain configurations
are expected to work. This change removes the more general fail
statement and warns or fails depending on the particular
configuration.
Change-Id: Ic24799aff966ba15858b93482e0f24a8672d9483
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/2905
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
ARM systems require local exclusive monitors for the implementation of
synchronization primitives between processors. A ruby memory system
needs to forward invalidations to the local exclusive monitors to
to correctly determine their state.
Change-Id: I7bc4d0f2a5be0f4e36a25c87aa4a81a3f086fb3c
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/2904
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Previously the directory covered a flat address range that always
started from address 0. This change adds a vector of address ranges
with interleaving and hashing that each directory keeps track of and
the necessary flexibility to support systems with non continuous
memory ranges.
Change-Id: I6ea1c629bdf4c5137b7d9c89dbaf6c826adfd977
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/2903
Reviewed-by: Bradford Beckmann <brad.beckmann@amd.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
