Moving the address translation logic outside of the ISA::setMiscReg will
allow it to return and potentially invoke a fault
upon execution of the AT instruction. This change affects AArch64 mode
only
Originally, the debug print for read/write to specific register name
will happen after reg.read() and reg.write(). However, there might be
other debug print or warning inside reg.read(), reg.write() which would
be confusing if this debug log happen after all other debug print inside
reg.read(), reg.write().
Creating this commit to change the order.
Starting with https://github.com/gem5/gem5/pull/1453 , some Ruby
structures require a block size be set
and other require a pointer to the Ruby system. This fixes some cases
which were not covered by the per-checkin tests but seen in daily+
tests. In particular:
- WriteMasks and PerfectCacheMemory must explicitly set a block size.
- NetDest and RubyProxyPort require RubySystem pointer.
- Classes inheriting Message now have a setRubySystem collecting all
objects that need a RubySystem pointer and this should be called in
the constructor of the Message.
This commit makes sure all of these happen. This should fix daily
arm_boot_tests and daily learning_gem5 tests.
At some point 'system' -> 'board' in the stdlib code the replacement
policy tests used. Due to this the output is slightly different meaning
the refs need updated.
This was causing the Daily Tests to fail.
Move AT instructions out of setMiscReg.
Modification includes:
- Add template for AT instructions in misc64.isa.
- Add decoder and execution of AT instruction in aarch64.isa and
data64.isa.
- Add AtOp64 and AtOp64Hub to perform the behavior of AT instructions.
Change-Id: I7e8b802421f7335203edb9f8d748ad8669954b8c
This missing parameter causing the Learning gem5 tests to fail.
**Note:** We need to update the website's learning gem5 examples to
reflect this change.
Modifies union construction in the debug directory so output is more
amenable to alternative compilers. Verified that this change produces
code that builds with clang, gcc, msvc, nvhpc, aocc, icc, openxl, and
cray hpc.
These were the kinds of errors seen in MSVC, which this patch fixes.
```
debug/Decoder.hh(24): error C2461: 'gem5::debug::unions::Decoder': constructor syntax missing formal parameters
debug/Decoder.hh(31): error C7624: Type name 'gem5::debug::unions::Decoder' cannot appear on the right side of a class member access expression
```
This PR addresses comments from #1584
- removed tests using the same binary multiple times. Each binary is
tested once with one graph
- Updated the input sizes as per the comments in the above mentioned PR
This PR adds the SMS prefetcher described in [this
](https://web.eecs.umich.edu/~twenisch/papers/isca06.pdf) paper.
This work was done in collaboration with @Setu-Gupta, and @xmlizhao
On branch sms
Changes to be committed:
modified: src/mem/cache/prefetch/Prefetcher.py
modified: src/mem/cache/prefetch/SConscript
new file: src/mem/cache/prefetch/sms.cc
new file: src/mem/cache/prefetch/sms.hh
Change-Id: I68d3bb6cf07385177d0f776fb958f652cfc41489
With this commit we replace the TlbEntry storage within the TLB from an
array of entries with a custom hardcoded FA indexing policy and LRU
replacement, into the flexible SetAssociative cache.
Change-Id: Ia74ff6962ac8195802b51dcc0caa516965f0ce37
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
KeyType definition is required if we want to store the TlbEntry
within an AssociativeCache. We could add an alias and keep the
Lookup name but this will just create extra confusion
Change-Id: Ib0b7c9529498f0f6f15ddd0e7cf3cec52966e8df
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
This is needed for compliance with the AssociativeCache
container. It will call the invalidate method when
invalidating the TLB entry
Change-Id: Idb1bc40b5aea8c475146700c81ab79d9980f745d
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
With this commit we record the page sizes of all valid
TLB entries in a TLB.
We update the set conservatively, therefore allowing
false positives but not false negatives.
This information will be used when doing a page size based
lookup. At the moment we don't strictly need it as we
iterate over all TLB entries (the TLB implements a fully
associative cache) and if we find multiple matches, it means
we have stored some partial translations.
The existing logic is prioritizing complete translations
over partial translations and among the latter, late stage
translations over early stage (with the idea to minimize
the number of walks).
The "iterate once over the entire TLB and record all matches"
won't work well when we shift from a fully associative
TLB into a set associative. With the introduction of the
aforementioned set, we can do page size based lookups,
so we can explicitly lookup the TLB for a specific page size
therefore looking into the appropriate set for a match
Change-Id: If77853373792d6a5ec84cf1909ee5eb567f3d0e4
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Some ISAs (like Arm) have moved most of the translation logic into
the MMU and use the TLB simply as translation storage. It makes
sense to use the MMU debug flag for that logic and reduce the
scope of the TLB flag to TLB insertion/hits/misses
Change-Id: I2a164545c711d83d3e87075b0cb5c279eed274c9
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
This commit is moving some MMU methods definition in the
source file from the header to avoid including tlb.hh
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Change-Id: I8fb1aeccd9c38c48b09583b4dc5d152acd09c3e6
It is a simple enum to distinguish between short and big
descriptors. By moving it away from the ArmFault we can
avoid including fault.hh from mmu.hh
Change-Id: Ib556b577c62f5ea3e4c8c9e0d4560a3e99c96778
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
We are implementing derived classes of SignalSinkPort that does some
additional logic after it's triggered (set() invoked by SignalSourcePort
peer), and before executing the callback that a device provides (in
onChange_). The logic is like additional logging, or providing debugging
features. However, set() itself directly calls the onChange_ callback.
Making the set() virtual could provide the flexibility to achieve this
feature.
This demo board is a preset arm board, that can be used to run example
gem5 simulations. This board doesnt simulate any known hardware.
The board will be used to run benchmarks such as gapbs and npb to
collect stats. The plan is to show these stats on the gem5 resources
website to provide more details about the resources.
1. Implement Zcmp(cm.push, cm.pop, cm.popret, cm.popretz, cm.mva01s,
cm.mvsa01) instructions
2. The Zcd instructions overlap the Zcmp and Zcmt instruction. This
option is used to enable/disable Zcd extension, implies enable Zcmp/Zcmt
extension. If Zcd is enable, the Zcmp and Zcmt is disabled. Otherwise,
Zcmp and Zcmt is enabled.
Spec: https://github.com/riscv/riscv-isa-manual/blob/main/src/zc.adoc
- This change updates syntax of constructors of Template Classes from
`class<T>()` to `class()`
- Initializes coherence to 0 in `src/mem/cache_blk.hh`
The above changes are made to solve the errors when compiling gem5 in
gcc 14
This commit modifies X86DemoBoard so it has numbers more similar to that
of RiscvDemoBoard and ArmDemoBoard. It also adds SE mode to
X86DemoBoard. Note that the changes here depend on the changes in PR
1579.
**Note**: This PR was created so @BobbyRBruce could add his commits to
#1600
---------
Co-authored-by: Erin Le <ejle@ucdavis.edu>
There were a number of variables in the arm and x86 decoders that are
static (e.g., the decode cache). It's a bit interesting that this
doesn't cause problems with multiple cores since each core has its own
decoder.
However, this causes segfaults if you run different cores on different
*host* threads. We are experimenting with running gem5 with multiple
host thread (i.e., in parallel), and removing these static variables
resolves the segfault.
This change also adds const to any other static variables to ensure that
they cannot be modified.
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
The Zcd instructions overlap the Zcmp and Zcmt instruction
This option is used to enable/disable Zcd extension, implies enable
Zcmp/Zcmt extension. If Zcd is enable, the Zcmp and Zcmt is disabled.
Otherwise, Zcmp and Zcmt is enabled.
Spec: https://github.com/riscv/riscv-isa-manual/blob/main/src/zc.adoc#zc-overview
Change-Id: I3788eb6539e13a210c9946efc43ca1fef4639560
There are two issues related to setting an element in PackedReg where
the element spans multiple dwords. First, the mask value is wrong and is
clobbering both dwords. Second, a portion of the value is shifted out of
the narrower input type.
Fix this by using the correct mask to clear the bits where the value
will be placed and use a larger data type to shift the value into place.
* Deprecates the setting of FS/SE mode via the `Simulator` module.
* Moved the creation of the `Root` object from the `Simulator` to the
board.
* Moved the setting of `sim_quantum` from the `Simulator` to the
processor.
* Allows for easier development of boards which support both SE and FS
mode simulation by moving board setup function calls to occur after the
set_workload function is call which sets a boards stats `is_fs` status.
This pops up in kernel 6.8.0. The device it is trying to write is
currently unknown but does not cause problems ignoring the device,
therefore change the panic to a warning and responding to the request
with the default PCI latency.
Change-Id: I4c1229753a75a94a255d8cfd411ac7311283366b
