derek/gem5
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

arch-riscv: Add enable_Zcd options to RiscvISA

Browse Source 
The Zcd instructions overlap the Zcmp and Zcmt instruction

This option is used to enable/disable Zcd extension, implies enable
Zcmp/Zcmt extension. If Zcd is enable, the Zcmp and Zcmt is disabled.
Otherwise, Zcmp and Zcmt is enabled.

Spec: https://github.com/riscv/riscv-isa-manual/blob/main/src/zc.adoc#zc-overview

Change-Id: I3788eb6539e13a210c9946efc43ca1fef4639560
This commit is contained in:
Roger Chang
2024-07-04 16:02:49 +08:00
parent deb8f983a1
commit aa782cffee
8 changed files with 84 additions and 54 deletions
Download Patch File Download Diff File Expand all files Collapse all files

7
src/arch/riscv/RiscvISA.py
View File

@@ -114,6 +114,13 @@ class RiscvISA(BaseISA):
enable_Zicbom_fs = Param.Bool(True, "Enable Zicbom extension in FS mode")
enable_Zicboz_fs = Param.Bool(True, "Enable Zicboz extension in FS mode")
enable_Zcd = Param.Bool(
True,
"Enable Zcd extensions. "
"Set the option to false implies the Zcmp and Zcmt is enable as "
"c.fsdsp is overlap with them."
"Refs: https://github.com/riscv/riscv-isa-manual/blob/main/src/zc.adoc",
)
wfi_resume_on_pending = Param.Bool(
False,

2
src/arch/riscv/decoder.cc
View File

@@ -44,6 +44,7 @@ Decoder::Decoder(const RiscvDecoderParams &p) : InstDecoder(p, &machInst)
ISA *isa = dynamic_cast<ISA*>(p.isa);
vlen = isa->getVecLenInBits();
elen = isa->getVecElemLenInBits();
_enableZcd = isa->enableZcd();
reset();
}
@@ -127,6 +128,7 @@ Decoder::decode(PCStateBase &_next_pc)
emi.vtype8 = next_pc.vtype() & 0xff;
emi.vill = next_pc.vtype().vill;
emi.rv_type = static_cast<int>(next_pc.rvType());
emi.enable_zcd = _enableZcd;
return decode(emi, next_pc.instAddr());
}

1
src/arch/riscv/decoder.hh
View File

@@ -62,6 +62,7 @@ class Decoder : public InstDecoder
uint32_t vlen;
uint32_t elen;
bool _enableZcd;
virtual StaticInstPtr decodeInst(ExtMachInst mach_inst);

2
src/arch/riscv/isa.cc
View File

@@ -260,7 +260,7 @@ RegClass ccRegClass(CCRegClass, CCRegClassName, 0, debug::IntRegs);
ISA::ISA(const Params &p) : BaseISA(p, "riscv"),
_rvType(p.riscv_type), enableRvv(p.enable_rvv), vlen(p.vlen), elen(p.elen),
_privilegeModeSet(p.privilege_mode_set),
_wfiResumeOnPending(p.wfi_resume_on_pending)
_wfiResumeOnPending(p.wfi_resume_on_pending), _enableZcd(p.enable_Zcd)
{
_regClasses.push_back(&intRegClass);
_regClasses.push_back(&floatRegClass);

10
src/arch/riscv/isa.hh
View File

@@ -108,6 +108,14 @@ class ISA : public BaseISA
*/
const bool _wfiResumeOnPending;
/**
* Enable Zcd extensions.
* Set the option to false implies the Zcmp and Zcmt is enable as c.fsdsp
* is overlap with them.
* Refs: https://github.com/riscv/riscv-isa-manual/blob/main/src/zc.adoc
*/
bool _enableZcd;
public:
using Params = RiscvISAParams;
@@ -184,6 +192,8 @@ class ISA : public BaseISA
bool resumeOnPending() { return _wfiResumeOnPending; }
bool enableZcd() { return _enableZcd; }
virtual Addr getFaultHandlerAddr(
RegIndex idx, uint64_t cause, bool intr) const;
};

1
src/arch/riscv/isa/bitfields.isa
View File

@@ -34,6 +34,7 @@
// Bitfield definitions.
//
def bitfield RVTYPE rv_type;
def bitfield ENABLE_ZCD enable_zcd;
def bitfield QUADRANT <1:0>;
def bitfield OPCODE5 <6:2>;

114
src/arch/riscv/isa/decoder.isa
View File

@@ -54,23 +54,25 @@ decode QUADRANT default Unknown::unknown() {
Rp2 = rvSext(sp + imm);
}}, uint64_t);
format CompressedLoad {
0x1: c_fld({{
offset = CIMM3 << 3 | CIMM2 << 6;
}}, {{
STATUS status = xc->readMiscReg(MISCREG_STATUS);
if (status.fs == FPUStatus::OFF)
return std::make_shared<IllegalInstFault>("FPU is off",
machInst);
0x1: decode ENABLE_ZCD {
0x1: c_fld({{
offset = CIMM3 << 3 | CIMM2 << 6;
}}, {{
STATUS status = xc->readMiscReg(MISCREG_STATUS);
if (status.fs == FPUStatus::OFF)
return std::make_shared<IllegalInstFault>("FPU is off",
machInst);
// Mutating any floating point register changes the FS bit
// of the STATUS CSR.
status.fs = FPUStatus::DIRTY;
xc->setMiscReg(MISCREG_STATUS, status);
// Mutating any floating point register changes the FS bit
// of the STATUS CSR.
status.fs = FPUStatus::DIRTY;
xc->setMiscReg(MISCREG_STATUS, status);
Fp2_bits = Mem;
}}, {{
EA = rvSext(Rp1 + offset);
}});
Fp2_bits = Mem;
}}, {{
EA = rvSext(Rp1 + offset);
}});
}
0x2: c_lw({{
offset = CIMM2<1:1> << 2 |
CIMM3 << 3 |
@@ -152,18 +154,20 @@ decode QUADRANT default Unknown::unknown() {
}
}
format CompressedStore {
0x5: c_fsd({{
offset = CIMM3 << 3 | CIMM2 << 6;
}}, {{
STATUS status = xc->readMiscReg(MISCREG_STATUS);
if (status.fs == FPUStatus::OFF)
return std::make_shared<IllegalInstFault>("FPU is off",
machInst);
0x5: decode ENABLE_ZCD {
0x1: c_fsd({{
offset = CIMM3 << 3 | CIMM2 << 6;
}}, {{
STATUS status = xc->readMiscReg(MISCREG_STATUS);
if (status.fs == FPUStatus::OFF)
return std::make_shared<IllegalInstFault>("FPU is off",
machInst);
Mem = Fp2_bits;
}}, {{
EA = rvSext(Rp1 + offset);
}});
Mem = Fp2_bits;
}}, {{
EA = rvSext(Rp1 + offset);
}});
}
0x6: c_sw({{
offset = CIMM2<1:1> << 2 |
CIMM3 << 3 |
@@ -381,23 +385,25 @@ decode QUADRANT default Unknown::unknown() {
Rc1 = rvSext(Rc1 << imm);
}}, uint64_t);
format CompressedLoad {
0x1: c_fldsp({{
offset = CIMM5<4:3> << 3 |
CIMM1 << 5 |
CIMM5<2:0> << 6;
}}, {{
STATUS status = xc->readMiscReg(MISCREG_STATUS);
if (status.fs == FPUStatus::OFF)
return std::make_shared<IllegalInstFault>("FPU is off",
machInst);
0x1: decode ENABLE_ZCD {
0x1: c_fldsp({{
offset = CIMM5<4:3> << 3 |
CIMM1 << 5 |
CIMM5<2:0> << 6;
}}, {{
STATUS status = xc->readMiscReg(MISCREG_STATUS);
if (status.fs == FPUStatus::OFF)
return std::make_shared<IllegalInstFault>("FPU is off",
machInst);
status.fs = FPUStatus::DIRTY;
xc->setMiscReg(MISCREG_STATUS, status);
status.fs = FPUStatus::DIRTY;
xc->setMiscReg(MISCREG_STATUS, status);
Fc1_bits = Mem;
}}, {{
EA = rvSext(sp + offset);
}});
Fc1_bits = Mem;
}}, {{
EA = rvSext(sp + offset);
}});
}
0x2: c_lwsp({{
offset = CIMM5<4:2> << 2 |
CIMM1 << 5 |
@@ -480,19 +486,21 @@ decode QUADRANT default Unknown::unknown() {
}
}
format CompressedStore {
0x5: c_fsdsp({{
offset = CIMM6<5:3> << 3 |
CIMM6<2:0> << 6;
}}, {{
STATUS status = xc->readMiscReg(MISCREG_STATUS);
if (status.fs == FPUStatus::OFF)
return std::make_shared<IllegalInstFault>("FPU is off",
machInst);
0x5: decode ENABLE_ZCD {
0x1: c_fsdsp({{
offset = CIMM6<5:3> << 3 |
CIMM6<2:0> << 6;
}}, {{
STATUS status = xc->readMiscReg(MISCREG_STATUS);
if (status.fs == FPUStatus::OFF)
return std::make_shared<IllegalInstFault>("FPU is off",
machInst);
Mem_ud = Fc2_bits;
}}, {{
EA = rvSext(sp + offset);
}});
Mem_ud = Fc2_bits;
}}, {{
EA = rvSext(sp + offset);
}});
}
0x6: c_swsp({{
offset = CIMM6<5:2> << 2 |
CIMM6<1:0> << 6;

1
src/arch/riscv/types.hh
View File

@@ -58,6 +58,7 @@ BitUnion64(ExtMachInst)
// Decoder state
Bitfield<63, 62> rv_type;
Bitfield<61> compressed;
Bitfield<60> enable_zcd;
// More bits for vector extension
Bitfield<57, 41> vl; // [0, 2**16]
Bitfield<40> vill;