Commit Graph

21002 Commits

Author SHA1 Message Date
Bobby R. Bruce
bfd25f5352 util-docker: Enforce cmake version >=3.24 for DRAMSys (#627)
DRAMSys requires cmake 3.24 or greater. By default neither Ubuntu 22.04
or 20.04 delevery this by APT.

In both cases wget is required. In 20.04 OpenSSL is required.

Then ext/dramsys README file has been updated to state this requirement.
2023-11-30 21:23:53 -08:00
Jason Lowe-Power
62a2b6eed2 ext: Update readme for DRAMSys
Specify the cmake version

Change-Id: I8bbdb128667df37724c38caef5572d8fb1641ef5
2023-11-30 15:09:28 -08:00
Jason Lowe-Power
b3e7af9d79 Support for classic prefetchers in Ruby (#502)
This patch adds supports for using the "classic" prefetchers with ruby
cache controllers.

This pull request includes a few commits making the changes in this
order:
- Refactor decouples the classic cache and prefetchers interfaces
- Extras probes for later integration with ruby
- General ruby-side support
- Adds support for the CHI protocol

Commit [mem-ruby: support prefetcher in CHI
protocol](2bdb65653b)
may be used as example on how to add support for other protocols.

JIRA issues that may be related to this pull request:
    https://gem5.atlassian.net/browse/GEM5-457
    https://gem5.atlassian.net/browse/GEM5-1112
2023-11-30 10:24:29 -08:00
Yu-Cheng Chang
a16fd8a592 scons: Limit adding fastmodel files and libpath (#629)
The change will only add include and library path if the fastmodel is
required to build. The change will benefit for most of gem5 build.

Change-Id: I98c20bd1470b7227940036199e02bc001e307eac
2023-11-30 07:36:26 -08:00
Jason Lowe-Power
9afe9932bc sim,python: Restore sigint handler in python (#531)
Currently, if you try to use ctrl-c while python code is running nothing
happens. This is not ideal. This change enables users to use ctrl-c
while python is running (e.g., when a large disk image is downloading).
To do this, we moved the `initSignals` function in gem5 from `main` to
the simulate loop. Thus, every time the simulate loop starts (i.e., is
called from python) gem5 will install its signal handlers. Also, when
the control is returned to python, we put python's default SIGINT
handler back.

Change-Id: I14490e48d931eb316e8c641217bf8d8ddaa340ed
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
2023-11-30 07:27:52 -08:00
Andreas Sandberg
dcdebec0f6 misc,python: Add isort hook to pre-commit (#431) 2023-11-30 09:54:12 +00:00
Bobby R. Bruce
d11c40dcac misc: Run pre-commit run --all-files
This ensures `isort` is applied to all files in the repo.

Change-Id: Ib7ced1c924ef1639542bf0d1a01c5737f6ba43e9
2023-11-29 22:06:41 -08:00
Bobby R. Bruce
7d67109ca2 python,misc: Add isort to pre-commit
Change-Id: I391a8948f0817bd5c6a9fe8a4c3e4fed07a98c49
2023-11-29 22:06:05 -08:00
Bobby R. Bruce
f256064b4a util-docker: Enforce cmake version >=3.24 for DRAMSys
DRAMSys requires cmake 3.24 or greater. By default neither Ubuntu 22.04
or 20.04 delevery this by APT.

In both cases wget is required. In 20.04 OpenSSL is required.

Change-Id: I51a7f8a8a46e8cf1908a120adb9289aa3907ccda
2023-11-29 21:49:11 -08:00
Bobby R. Bruce
403bf38a0e tests: switch lulesh/hacc to use vega_x86 (#620) 2023-11-29 18:55:53 -08:00
Harshil Patel
b59a398312 tests: change HACC tests to VEGA_X86
Change-Id: I846229db1ab1480d79471c717b714698c3132df9
2023-11-29 16:02:30 -08:00
Harshil Patel
392086b43d stdlib, resources: removed deprecated if statement in obtain_resource for workload resources (#611)
- The resources field in workload now changed to a dict of id and
version from a string with just the id.
There was an if statement added to support both versions in develop.
Removing the if statement so that 23.1 supports the new changes only.

Change-Id: Id8dc3f932f53a156e4fb609a215db7d85bd81a44
2023-11-29 14:27:23 -08:00
Bobby R. Bruce
fcbcd1ce72 arch-x86: Fixes page fault for CLFLUSH on write-protected pages (#592)
Converts CLFLUSHOPT/WB/FLUSH operations from Write to Read operations
during address translation so that they don't trigger a page fault when
done on write-protected pages.

Solves #226
2023-11-29 14:25:21 -08:00
Hoa Nguyen
1d1cba297b scons: Add an option to reduce memory usage of ld (#601)
Linking the gem5 binary consists of linking numerous object files. By
default, ld optimizes for speed over for memory consumption [1]. This
leads to the huge memory consumption of gem5 at the linking stage.

This patch adds an option to add the `--no-keep-memory` flag to ld.
According to the documentation [1], this flag optimizes the memory usage
of ld.

[1]
https://ftp.gnu.org/old-gnu/Manuals/ld-2.9.1/html_chapter/ld_2.html#IDX133

Signed-off-by: Hoa Nguyen <hn@hnpl.org>
2023-11-29 14:24:48 -08:00
Yu-Cheng Chang
57ba3fccb7 scons: Move CPPPATH systemc_home to "src/systemc" folder (#617)
Files under src/systemc require the include path of systemc_home

Change-Id: Ibcbac2762259a0b997ac444b2c63a218c27af9ee
2023-11-29 13:56:23 -08:00
Bobby R. Bruce
a2e7bd4698 arch-riscv: Support combination of privilege modes configuration (#522)
The user can select privilege modes witch is included in the system, not
always enable the user and supervisor privilege modes.
2023-11-29 10:12:57 -08:00
Adrià Armejach
b0cefac9b2 arch-riscv: Fix narrow datatypes in RVV isa files (#606)
Some variables hava narrow datatypes that overflow on large VLEN values.
For example, the maximum number of microops for LMUL=8 SEW=8 and
VLEN=64K is 2^16.

Change-Id: I5cce759f040884e09ce83bee7e54a62c4b42c5aa

Co-authored-by: Adrià Armejach <adria.armejach@bsc.es>
2023-11-29 10:11:06 -08:00
Adrià Armejach
eb13b32314 cpu-o3: Fix discarded requests str-ld forwarding (#614)
With the use of large RVV vectors (i.e., 8K or 16K bits) and a limited
number of cacheLoadPorts, some loads take multiple cycles to execute.
This triggered certain conditions when store-to-load forwarding happens
in the middle of the execution of a load that already has outstanding
packets.

First, after store-to-load forwarding the request is marked as discarded
and the load is immediately writtenback, which triggers a writebackDone
that tries to delete the request, triggering an assert as it still has
outstanding packets. This patch avoid deleting the request leaving it
self owned, it will be deleted when the last packet arrives in
packetReplied.

Second, this patch avoid checking snoops on discarded requests by
checking if the request exists.

Change-Id: Icea0add0327929d3a6af7e6dd0af9945cb0d0970

Co-authored-by: Adrià Armejach <adria.armejach@bsc.es>
2023-11-29 08:45:03 -08:00
Harshil Patel
089b82b2e9 arch-riscv: fix tlb bug (#610)
- one tlb miss was getting counted twice by the lookup function.

Change-Id: I5fee08bd6e936896704e7dbbd242720b8d23b547
2023-11-29 08:39:02 -08:00
Harshil Patel
23cadf0886 tests: switch lulesh to use vega_x86
Change-Id: Ifbf0fdfd7d8c2bbaad0b6094090acecd1cb8055c
2023-11-29 07:41:51 -08:00
Tiago Mück
0f8c60bce5 mem-ruby: add missing state for CHI Prefetch event
RUSC state is missing for the Prefetch event.

Change-Id: If440ac0052100dba295708471a75a24cd234c011
Signed-off-by: Tiago Mück <tiago.muck@arm.com>
2023-11-28 18:30:50 -06:00
Tiago Mück
91cf58871e mem-ruby: support prefetcher in CHI protocol
Use RubyPrefetcherProxy to support prefetchers in the
CHI cache controller

L1I/L1D/L2 prefechers can now be added by specifying a non-null
prefetcher type when configuring a CHI_RNF.

Related JIRA:
https://gem5.atlassian.net/browse/GEM5-457
https://gem5.atlassian.net/browse/GEM5-1112

Additional authors:
    Tuan Ta <tuan.ta2@arm.com>

Change-Id: I41dc637969acaab058b22a8c9c3931fa137eeace
Signed-off-by: Tiago Mück <tiago.muck@arm.com>
2023-11-28 18:30:50 -06:00
Tiago Mück
94d5cc17a2 mem-ruby,mem-cache: ruby supports classic pfs
This patch adds RubyPrefetcherProxy, which provides means to inject
requests generated by the "classic" prefetchers into a SLICC prefetch
queue. It defines defines notifyPf* functions to be used by protocols
to notify a prefetcher. It also includes the probes required to
interface with the classic implementation.
AbstractController defines the accessor needed to snoop the caches.

A followup patch will add support for RubyPrefetcherProxy in the
CHI protocol.

Related JIRA:
https://gem5.atlassian.net/browse/GEM5-457
https://gem5.atlassian.net/browse/GEM5-1112

Additional authors:
    Tuan Ta <tuan.ta2@arm.com>

Change-Id: Ie908150b510f951cdd6fd0fd9c95d9760ff70fb0
Signed-off-by: Tiago Mück <tiago.muck@arm.com>
2023-11-28 18:30:50 -06:00
Tiago Mück
3a7192d682 mem-cache: change hasBeenPrefetched
hasBeenPrefetched can now take a requestor id and returns true only if
the block was prefetched by a prefetcher with the same id. This may be
necessary to properly train multiple prefetchers attached to the same
cache. If returns true if the block was prefetched by any prefetcher
when the id is not provided.

Related JIRA:
https://gem5.atlassian.net/browse/GEM5-457
https://gem5.atlassian.net/browse/GEM5-1112

Change-Id: I205e000fd5ff100e5a5d24d88bca7c6a46689ab2
Signed-off-by: Tiago Mück <tiago.muck@arm.com>
2023-11-28 18:30:49 -06:00
Tiago Mück
a63ff3c442 mem-cache: add prefetcher listener for evictions
Listener to data update probe notifies prefetcher of evictions.
Prefetchers need to implement notifyEvict to make use of this
information.

Related JIRA:
https://gem5.atlassian.net/browse/GEM5-457
https://gem5.atlassian.net/browse/GEM5-1112

Change-Id: I052cfdeba1e40ede077554ada104522f6a0cb2c7
Signed-off-by: Tiago Mück <tiago.muck@arm.com>
2023-11-28 18:30:49 -06:00
Tiago Mück
d8a04f902e mem-cache: add prefetch info to update probe
CacheDataUpdateProbeArg has additional info to tell listeners if the
block was prefetched and evicted without being used, as well as which
object prefetched the block.

Related JIRA:
https://gem5.atlassian.net/browse/GEM5-457
https://gem5.atlassian.net/browse/GEM5-1112

Change-Id: Id8ac9099ddbce6e94ee775655da23de5df25cf0f
Signed-off-by: Tiago Mück <tiago.muck@arm.com>
2023-11-28 18:30:49 -06:00
Tiago Mück
becba00d95 mem-cache,configs: remove extra prefetch_* params
Remove the prefetch_on_access and prefetch_on_pf_hit from BaseCache.
BasePrefetch no longer expects this params to exist in the parent.

Configurations that set these parameter using the cache object were
fixed.

Change-Id: I9ab6a545eaf930ee41ebda74e2b6b8bad0ca35a7
Signed-off-by: Tiago Mück <tiago.muck@arm.com>
2023-11-28 18:30:49 -06:00
Tiago Mück
af2ee0db30 mem-cache: decoupled prefetchers from cache
This patches decouples the prefetchers from the cache implementation
as the first step to allow using the classic prefetchers with ruby
caches. The prefetchers that need do cache lookups can do so using
the accessor object provided when the probes are notified. This may
also facilitate connecting the same prefetcher to multiple caches.

Related JIRA:
https://gem5.atlassian.net/browse/GEM5-457
https://gem5.atlassian.net/browse/GEM5-1112

Change-Id: I4fee1a3613ae009fabf45d7b747e4582cad315ef
Signed-off-by: Tiago Mück <tiago.muck@arm.com>
2023-11-28 18:30:49 -06:00
Jason Lowe-Power
3fe5e58f28 arch-x86: Fix misc registers in mov instructions (#593)
MOV instructions 8C and 8E can be prefixed with a REX prefix to extend
the source/destination register.
However, the R bit in REX will be applied to the segment register.  
The decoder file checks for valid segment registers, checking the
MODRM_REG only, however, later this will be extended with the REX_R when
adding the register to the sources/destinations of the instruction.
This will trigger an assert.

Additionally, MOV instructions of various miscelaneous registers are
also not check for being valid when taking into account the REX_R bit.

This patch checks that the REX_R is not set, otherwise, UD2 will be
generated.
2023-11-28 11:14:53 -08:00
Andreas Sandberg
0c30353c59 cpu: Require BTB hit to detect branches. (#493)
In a high performance CPU there is no other way than a BTB hit
to know about a branch instruction and its type. For low-end CPU's
pre-decoding might sit in from of the BPU to provide this information.
Currently, the BPU models only low-end behavior and updates the
RAS and the indirect branch prediction even without a BTB hit.
This patch adds three things to model the correct behavior for high-end
CPUs.
1. A check before the RAS and indirect predictor wheather there was
a BTB hit or not. Only for BTB hits the BPU will consolidate RAS, and
indirect predictor.
2. Since, this check requires a BTB hit for indirect branches they must
also be installed into the BTB. For returns this was already done.
3. Finally, the BTB update previously happened at squash (decode
or commit). Since this can be out-of-order that means branches from
the false path can get installed without ever been retired.
2023-11-28 09:39:14 +00:00
Roger Chang
9a0c671cce arch-riscv: Handle the exception following the privilege mode set
Change-Id: I4867941ec286fe485e01db848b8c7357488f6cf4
2023-11-28 09:26:27 +08:00
Roger Chang
d56801c240 arch-riscv: Add misa rvs check for memory translation
The memory translation require supervisor mode implement. If the
supervisor mode is not implemented, the satp CSR is not exists and
should not do address translation

Change-Id: Ie6c8a1a130d0aab0647b35e0f731f6b930834176
2023-11-28 09:26:27 +08:00
Roger Chang
6fd4feb797 arch-riscv: fatal_if the process run without SU modes
Change-Id: Ifce7eec6cea10881964c29d206a92f3d10271de6
2023-11-28 09:26:27 +08:00
Roger Chang
9e738a65ea arch-riscv: Add isaExts field for CSR registers
Change-Id: Idd94af57f3a721d455ea7fb9d335fab7b16a0f7e
2023-11-28 09:26:27 +08:00
Roger Chang
0e4f82a119 arch-riscv: define the CSR masks for each privilege modes
Change-Id: I9936d9bc816921a827b94550847d4898b3aa3292
2023-11-28 09:26:27 +08:00
Roger Chang
f745e8cf89 arch-riscv: Initial the privilege modes configuration
1. Declare the new enum type PrivilegeModes
2. Disallow setting the MISA register RVU and RVS.

Change-Id: I932d714bc70c9720a706353c557a5be76c950f81
2023-11-28 09:26:27 +08:00
aditya
c00209a0c0 Merge branch 'x86-clflush-fault-fix' of github.com:AKKamath/gem5 into x86-clflush-fault-fix
Change-Id: Ia9a694b0f7ef99331430cdb796c252ce8bb51f3b
2023-11-28 00:42:27 +00:00
Aditya K Kamath
9a0566e295 arch-x86: Fixes page fault for CLFLUSH on write-protected pages
Converts CLFLUSHOPT/WB/FLUSH operations from Write to Read operations
during address translation so that they don't trigger a page fault
when done on write-protected pages.

Change-Id: I20e89cc0cb2b288b36ba1f0ba39a2e1bf0f728af
2023-11-28 00:42:17 +00:00
Bobby R. Bruce
d94d6017b0 scons: Change to Kconfig build system (#69)
The PR contains the following changes:
- Move all of the config options(`env["CONF"]`) from SConsopt to Kconfig
files
- Update `build_opts` files to Kconfig option formats
- The Ruby Protocol files are only built if `RUBY=y`
- Remove the default-default build target
- Kconfig commands are included in the PR:
    - defconfig
    - setconfig
    - meunconfig
    - guiconfig
    - listnewconfig
    - savedefconfig
    - oldconfig
    - olddefconfig
- Add the `python3-tk` package dependencies
 
Jira issue: https://gem5.atlassian.net/browse/GEM5-1211
2023-11-27 13:59:18 -08:00
Matthew Poremba
9e6a87e67a dev-amdgpu: Writeback PM4 queue rptr when empty (#597)
The GPU device keeps a local copy of each ring buffers read pointer
(rptr) to avoid constant DMAs to/from host memory. This means it needs
to be periodically updated on the host side as the driver uses this to
determine how much space is left in the queue and may hang if it believe
the queue is full. For user-mode queues, this already happens when
queues are unmapped. For kernel mode queues (e.g., HIQ, KIQ) the rptr is
never updated leading to a hang.

In this patch the rptr for *all* queues is reported back to the kernel
whenever the queue reaches an empty state (rptr == wptr). Additionally
to handle PM4 queue wrap-around, the queue processing function checks if
the queue is not empty instead of rptr < wptr. This is state because the
driver fills PM4 queues with NOP packets on initialization and when wrap
around occurs.

Change-Id: Ie13a4354f82999208a75bb1eaec70513039ff30f
2023-11-27 11:02:11 -08:00
Bobby R. Bruce
d4b7c8a26d Merge branch 'develop' into develop-kconfig 2023-11-27 09:39:08 -08:00
Bobby R. Bruce
0f6eabe8c9 ext,github,tests: Update DRAMSys tests to v5.0 and handle new dependencies (#577)
#525 Updated DRAMSys to v5.0. This PR further improves v5.0
inforporation into gem5 by better managing its new dependencies and
updating the DRAMSys tests to use v5.0.

This PR:

1. Adds a check which throws warning if DRAMSys cannot be build due to a
missing `cmake` instead of failing with a build error. `cmake` is not a
hard gem5 requirement. It is only required to build DRAMSys in the cases
it is required. It is therefore prudent to not fail a build in cases
`cmake` is not present on the host system.
2. Updates the "all-dependency" Docker images to include the optional
dependencies `git-lfs` (needed to clone the DRAMSys repo when running
the command outlined in ext/dramsys/README -- introduced in #525) and
`cmake` (needed to build DRAMSys).
3. Updates the Weekly workflow's `dramsys-tests`' `Checkout DRAMSys` job
to clone DRAMSys in the same manner as outlined in ext/dramsys/README.
This ensures the `dram-systests` test the instructions we give users.
4. `.gitignore` is added to ext/dramsys to ignore the
ext/dramsys/DRAMSys directory when cloned for building and integration
into gem5.

(2.) Should fix our failing weekly tests:
https://github.com/gem5/gem5/actions/runs/6912511984/job/18808339821 and
(3.) will ensure the changes introduced in #525 are tested.
2023-11-27 09:37:11 -08:00
Harshil Patel
1de992bc75 tests: fix lulesh (#600)
- fixed the broken command that was causing lulesh to fail the run
Change-Id: I4e8a310f153d86deb8829f41b5ddd0c317df23cb
2023-11-27 07:42:59 -08:00
Matthew Poremba
cc9f81b08a arch-vega,arch-gcn3: Bugfix V_PERM_B32 and V_OR3_B32 (#599)
The V_PERM_B32 instruction is selecting the correct byte, but is
shifting into place moving by bits instead of bytes. The V_OR3_B32
instruction is calling the wrong instruction implementation in the
decoder.

This patch fixes both issues plus a bonus fix for GCN3's V_PERM_B32.
(GCN3 does not have V_OR3_B32).

Change-Id: Ied66c43981bc4236f680db42a9868f760becc284
2023-11-26 23:22:01 -08:00
Bobby R. Bruce
0b2c56ef66 mem-cache: Revert "Prefetchers Improvements" (#581)
Reverts gem5/gem5#564 to fix #580.

Discussion in #581 showed there may be a fix to this but reverting for now until 
a better solution is found.
2023-11-26 18:43:21 -08:00
Bobby R. Bruce
ab1d5dc3a0 arch-arm: Fix Virtual Interrupt logic in secure mode (#584)
This PR is fixing remaining issues in the ArmISA::Interrupt class; more
specifically it is enabling
virtual interrupts in secure mode (when FEAT_SEL2 is present). Previous
version was assuming no
virtual interrupt was possible in secure mode. We fix this assumption by
replacing the security check
with the EL2Enabled helper which closely matches the Arm pseudocode
2023-11-26 18:11:08 -08:00
Bobby R. Bruce
36e83943b5 tests,misc: Update DRAMSys test clone command
This clone is updated to reflect the new advice given in
ext/dramasys/README that was introduced in PR
https://github.com/gem5/gem5/pull/525 to upgrade DRAMSysm to v5.0.

Change-Id: I868619ecc1a44298dd3885e5719979bdaa24e9c2
2023-11-26 17:10:40 -08:00
Bobby R. Bruce
8f9a328652 util-docker: Add 'cmake' to all-deps
'cmake' is required to build DRAMSysm.

This is an optional dependency for compiling DRAMSys. It is therefore
not required. It is included in the "all-dependencies" Docker images
as they may be needed if DRAMSys is desired.

Change-Id: I1a3e1a6fa2da4d0116d423e9267d4d3095000d4e
2023-11-26 17:10:40 -08:00
Bobby R. Bruce
575114b63b ext: Add .gitignore to ext/dramsys
Change-Id: Ifc1a3c77b56cbe5777d041a88b2c0d5cb77eaf89
2023-11-26 17:10:40 -08:00
Bobby R. Bruce
cb61d01ede ext: Add 'cmake' dep check to DRAMSys install
CMake is not required to build gem5. It is only required to build
and link the optional DRAMSysm library. Therefore, if the DRAMSys repo
has been cloned but CMake is not present this patch ensures no attempt
at building or linking DRAMSysm is made. A warning is thrown
inform the user of the missing CMake.

Change-Id: I4d22e3a16655fd90f6b109b4e75859628f7d532d
2023-11-26 17:10:40 -08:00