Commit Graph

19930 Commits

Author SHA1 Message Date
bc6133e6a1 mem: Add DRAMSys wrapper as a memory object
Add a DRAMSys wrapper to the gem5 memory source that
instantiates the DRAMSys simulator.
Another DRAMSys SimObject implements the AbstractMemory
interface and exposes the tlm target socket.

Change-Id: I8a95e729905e0924453043e5e7744df7a7ce4548
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/62912
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
Reviewed-by: Bobby Bruce <bbruce@ucdavis.edu>
2023-03-29 08:19:08 +00:00
ddcf452b1b ext: Add DRAMSys integration instructions
Add instructions to add the DRAMSys memory simulator
to gem5 in the ext/ directory.
The provided SConscript file compiles DRAMSys.

Change-Id: If5c723db61a3151c9155190f968c66927d7bfaa3
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/62911
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby Bruce <bbruce@ucdavis.edu>
2023-03-29 08:19:08 +00:00
Gabe Black
d03bc9d33c base,cpu,dev: Add a level of indirection for ListenSockets.
This makes room for there to be different implementations for different
types of sockets.

Change-Id: I8c959e2c3400caec8242e693e11330e072bc2c5f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/69162
Reviewed-by: Yu-hsin Wang <yuhsingw@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
2023-03-29 07:27:43 +00:00
Gabe Black
7c614d225b base: Make ListenSocket::listen(int port) protected.
Stop making the old API available.

Change-Id: I70752d081cb572a8ae5bf396d2ea43ecc7be1e9c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/69161
Maintainer: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Yu-hsin Wang <yuhsingw@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2023-03-29 03:05:06 +00:00
Gabe Black
67fb75d659 base,cpu,dev,sim: Pull common logic into ListenSocket::listen().
Create a version of listen() which handles common logic internally,
including scanning for an available port number, and notifying what
port was chosen.

The port is managed internal to ListenSocket, so that the logic
interacting with it doesn't need to manually manage a port number, and
hence a port number does not need to exist for non AF_INET sockets.

Change-Id: Ie371eccc4d0da5e7b90714508e4cb72fb0091875
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/69160
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Yu-hsin Wang <yuhsingw@google.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
2023-03-29 03:05:06 +00:00
Xuan Hu
461520d0ab ext: Update softfloat to 3d full version
* Add all softfloat source files without any change.
* Remove useless file softfloat.mk.in, since gem5 use Scons.
* Add `use_fast_int64` in SConscript to distinguish src of two strategies for data
  larger than 64 bits.
  * The SoftFloat library uses two strategies to handle data larger than 64bit. One is
    spliting data into `fast_int64`, and the other is using pointer. Two strategies
    are distinguished by macro `SOFTFLOAT_FAST_INT64`. But not all "*.c" files are
    guarded by this macro, which leads to including useless files in compiling progress
    and compiling error. `use_fast_int64` used in SConscript can exclude unnecessary
    files.

Change-Id: I7cec10412c00a35c247299cd92d83cdee9066410
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/66552
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
2023-03-28 10:47:18 +00:00
Bobby R. Bruce
c68fac2cfc tests: Add "run threads" optional parameter to weekly.sh
Adds a third argument to the weekly.sh script, allowing for a different
number of "run threads" (maximum number of tests that can be run at
once) and "compile threads" (threads to allocate to the running of
gem5). This is useful for cases where a high number of compilation
threads is wanted (e.g., 50 or so), but that number of tests running at
once is undesirable.

Change-Id: Ifd67c5826c6f3602db1546a8a48e615cb03ba820
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/69241
Reviewed-by: Bobby Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
2023-03-28 06:46:44 +00:00
Bobby R. Bruce
c8abd97584 tests: Disable the looppoint checkpoint tests
The Looppoint checkpoint  feature is still under-development.
These tests are stalling indefinitely and causing the Weekly tests to
timeout. They are therefore disabled until looppoint functionality is
complete and this bug is resolved.

Change-Id: I2c16abdaec639120c0ba349d90f5cc2fe747f8e6
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/69240
Reviewed-by: Bobby Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
2023-03-28 06:46:44 +00:00
Bobby R. Bruce
4ce826b244 tests: Check if ARM/gem5.opt not built in test_hdf5.py
This test was failing to load as ARM/gem5.opt is not built when this
test is pased during the Weekly tests. This bug is highlighed here:
https://gem5.atlassian.net/browse/GEM5-1073.

Comments have been added explaining this issue and the test not fails
more quitely. It, however, is not run.

Change-Id: I1f26f541a15438f6124a7541c01d44f70647762a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/69239
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
2023-03-28 06:46:44 +00:00
Bobby R. Bruce
3f59eed523 tests: Fix the Weekly arm-boot-tests
These tests were broken due to an incorrect 'valid_isas' flag. This
patch fixes this error.

Change-Id: I941deb209151dd94ca64f2741229398f13153c50
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/69238
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
2023-03-28 06:46:44 +00:00
Bobby R. Bruce
68fed7b5e1 tests: Fix Replacement Policy Tests
The script run by 'test_replacement_policies.py' was named
'run_replacement_policy_test.py'. This caused the TestLib framework to
fail as any file with the string "test" in it was attempted to parse as
a test. As this is a gem5 Python config file, this caused a failure.

To fix this the file was renamed 'run_replacement_policy.py'.

Change-Id: I6f0a09e4f5056a9c94e258c9aea26bf277206733
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/69237
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
2023-03-28 06:46:44 +00:00
Bobby R. Bruce
8dfaec0e10 util-docker: Update systemc docker image to use 22.04
Updates the Dockerfile, and therefore the Docker image, to use Ubuntu
22.04 instead of Ubuntu 20.04.

Change-Id: I0969205159d47ece9b0b6c0452ce0f3420f32e4c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/69317
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby Bruce <bbruce@ucdavis.edu>
2023-03-28 01:21:52 +00:00
Ayaz Akram
024a907cbb stdlib: Small fix in mesi three level component
This change ensures that if cache_line_size is not
an integer type, we don't incorrectly raise the
exception of cache size not equal to 2^bits.

Change-Id: I5a06cdac820283feb54f23d805fd87490fae1c3b
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/69297
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
2023-03-27 20:45:00 +00:00
Matt Sinclair
2112eea414 tests: add GPU Ruby Random tester with WB L2 caches
The current GPU Ruby Random tester tests only test for WT L2 caches,
meaning that some transitions (specific to WB caches) are never
tested.  To help ensure better coverage, this commit adds a separate
test that tests WB GPU L2 caches to the per-checkin and nightly
regressions.

Change-Id: I539ece3b825b9a38630027d947dc11ebef588752
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/69258
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
Reviewed-by: Bobby Bruce <bbruce@ucdavis.edu>
2023-03-24 06:21:31 +00:00
Gabe Black
db1a5a367d base,cpu,dev: Simplify ListenSocket::listen().
Remove the "reuse" parameter which default to true and was always
also explicitly set to true. Tidy up the code itself slightly, mostly
by using "panic_if" to remove some nesting.

Change-Id: Ie23971aabf2fe4252d27f1887468360722a72379
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/69159
Maintainer: Gabe Black <gabeblack@google.com>
Reviewed-by: Yu-hsin Wang <yuhsingw@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2023-03-22 09:19:44 +00:00
Yu-hsin Wang
daaccaa9ae fastmodel: skip vector registers update in remote gdb
iris::ThreadContext doesn't implement the write interface for vector
registers. Skip that part in fastmodel remote_gdb to make updating
common registers work at least.

Change-Id: Ifa071f5dff4bdeee7361ae824b4b76e0b2805460
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/69177
Maintainer: Gabe Black <gabeblack@google.com>
Reviewed-by: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2023-03-22 08:33:30 +00:00
Gabe Black
2e1d24d048 base,dev: Simplify the ListenSocket::accept method.
Remove the nodelay option which is always set to the same thing, and
simplify the logic of the method itself.

Change-Id: I78cd91f99cbaec9abddedbc7dcddc563daedb81f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/69158
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Reviewed-by: Yu-hsin Wang <yuhsingw@google.com>
2023-03-22 08:27:23 +00:00
Alvaro Moreno
79cfef2650 stdlib: Define env variables in SE workload
Implements a parameter in SE binary workload class
to define env variables inside each process.

Change-Id: I943a560043eff423989297cb2afa386a90df6791
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/68937
Reviewed-by: Bobby Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
2023-03-22 07:31:27 +00:00
Matt Sinclair
a030ff2745 mem-ruby: fix atomic deadlock with WB GPU L2 caches
By default the GPU VIPER coherence protocol uses a WT L2 cache.
However it has support for using WB caches (although this is not
tested currently).  When using a WB L2 cache for the GPU, this
results in deadlocks with atomics.

Specifically, when an atomic reaches the L2 and the line is
currently in M or W, the line must be written back before the atomic
can be performed.  However, the current support has two issues:

a) it never performs the atomic operation -- while VIPER current
assumes all atomics are system scope atomics and thus cannot be
performed at the L2 and this transition requires the dirty line be
written back before performing the atomic, the transition never
performs the atomic nor does the response path handle it.
b) putting the atomic action right after the write back is not
safe because we need to ensure the requests are ordered when they
reach memory -- thus we have to wait until the write back is
acknowledged before it's safe to send/perform the atomic.

To fix this, this change modifies the transition in question to
put the atomic on the stalled requests buffer, which the WBAck will
check when it returns to the L2 (and thus perform the atomic, which
will result in the atomic being sent on to the directory).

This fix has been tested and verified with both the per-checkin and
nightly GPU Ruby Random tester tests (with a WB L2 cache).

Change-Id: I9a43fd985dc71297521f4b05c47288d92c314ac7
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/68978
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
Reviewed-by: Matthew Poremba <matthew.poremba@amd.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2023-03-22 04:00:38 +00:00
Matt Sinclair
92d920f994 mem-ruby: fix load deadlock with WB GPU L2 caches
By default the GPU VIPER coherence protocol uses a WT L2 cache.
However it has support for using WB caches (although this is not
tested currently).  When using a WB L2 cache for the GPU, this
results in deadlocks with loads.

Specifically, when a load reaches the L2 and the line is currently
in the W state, that line must be written back before the load can
be performed.  However, the current transition for this in the L2
did not attempt to retry the load when the WB completes, resulting
in a deadlock.  This deadlock can be replicated by running the GPU
Ruby random tester as is with a WB L2 cache instead of a WT L2
cache.

To fix this, this change modifies the transition in question to
put the load on the stalled requests buffer, which the WBAck will
check when it returns to the L2 (and thus perform the load).

This fix has been tested and verified with both the per-checkin and
nightly GPU Ruby Random tester tests (with a WB L2 cache).

Change-Id: Ieec4f61a3070cf9976b8c3ef0cdbd0cc5a1443c6
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/68977
Reviewed-by: Matthew Poremba <matthew.poremba@amd.com>
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
2023-03-22 04:00:38 +00:00
Gabe Black
fb4eb86711 base: Flip the default for ListenSocket::accept(bool nodelay).
This option was almost always overridden from false to true anyway,
except in one place (in the ethertap device) which was likely just by
accident.

This will give external users a chance to remove the option without
changing behavior, so that the option can be removed entirely in a
later change.

Change-Id: I77add40b8131b91997b2aecbfff6c7de0ee9ead9
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/69157
Reviewed-by: Yu-hsin Wang <yuhsingw@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
2023-03-22 03:20:43 +00:00
Roger Chang
2c488e07df arch-riscv: Add pmp index checking
Check the index is within the bounds of PMP table before updating the
address and config

Change-Id: Ie938b3c2a61eca9527192c0452d1db9522f07af9
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/69117
Reviewed-by: Bobby Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Ayaz Akram <yazakram@ucdavis.edu>
Reviewed-by: Yu-hsin Wang <yuhsingw@google.com>
2023-03-22 01:31:17 +00:00
Giacomo Travaglini
069688df35 misc: Update the .git-blame-ignore-revs to ignore flynt commit
This [1] is just a cosmetic change which shouldn't affect functionalities.
We might want to ignore it when running git blame

[1]: https://gem5-review.googlesource.com/c/public/gem5/+/68957

Change-Id: I96e3308beb0bc6ad9638df137341bf611d4db5b1
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/69037
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
2023-03-21 06:54:40 +00:00
Giacomo Travaglini
7b39a7f14e misc: Rename DEBUG macro into GEM5_DEBUG
The DEBUG macro is not part of any compiler standards (differently from
NDEBUG, which elides assertions).

It is only meant to differentiate gem5.debug from .fast and .opt builds.
gem5 developers have used it to insert helper code that is supposed to
aid the debugging process in case anything goes wrong.

This generic name is likely to clash with other libraries linked with
gem5.  This is the case of DRAMSim as an example.

Rather than using undef tricks, we just inject a GEM5_DEBUG macro
for gem5.debug builds.

Change-Id: Ie913ca30da615bd0075277a260bbdbc397b7ec87
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/69079
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
2023-03-21 06:53:55 +00:00
Giacomo Travaglini
e4a9864458 sim: Remove unused SimObject::debugObjectBreak
The static method is only present in gem5.debug builds and
it doesn't seem to do anything else than setting up a boolean
flag. I was not able to understand from git history which
was the purpose of it but I am confident it's not currently
used.

It was maybe meant to work with the --debug-break option, which
sends a SIGRAP to the current PID in order to halt a GDB
session at a specific time. Maybe the idea was to halt only
when executing a SimObject method?

Change-Id: Ic21e8f55b5e35480c2bc617c24e1352c37516e8f
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/69078
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
2023-03-21 06:53:55 +00:00
Giacomo Travaglini
2bbd2b9596 base: Remove unnecessary DEBUG guard
There is no performance improvement on guarding a cprint
before a panic. We should just print as many info as possible
anytime we encounter a failure

Change-Id: I3ee9fb2c3b8a8f23bdf6173bb2a010020f2b2572
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/69077
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Tested-by: kokoro <noreply+kokoro@google.com>
2023-03-21 06:53:55 +00:00
Yu-hsin Wang
f6ee1f2724 fastmodel: delay the breakpoint event handle to simulation stop
The fastmodel simulation would be paused when it hits a breakpoint.
However, the order of stop event happens after the breakpoint event. If
we handle the breakpoint logic in the breakpoint event, it may cause
somehow status unsynchronized. To make the behavior stable, we delay the
breakpoint handle until the simulation stop event called.

Change-Id: I0083561f561af71370ccaa066220b72ed7831b78
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/68697
Reviewed-by: Earl Ou <shunhsingou@google.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2023-03-20 02:45:20 +00:00
Giacomo Travaglini
e73655d038 misc: Use python f-strings for string formatting
This patch has been generated by applying flynt to the
gem5 repo (ext has been excluded)

JIRA: https://gem5.atlassian.net/browse/GEM5-831

Change-Id: I0935db6223d5426b99515959bde78e374cbadb04
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/68957
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby Bruce <bbruce@ucdavis.edu>
2023-03-16 09:05:29 +00:00
Bobby R. Bruce
07fca546e6 ext: Update Pybind to Version 2.10.3
Updating Pybind11 is necessary for gem5 to compile correctly with
Python 3.11. As of March 9th 2023, 2.10.3 is the latest version of
Pybind11.

Change-Id: I32c68c507770040d3fac2de442d88a8f46b48896
Issue-on: https://gem5.atlassian.net/browse/GEM5-1295
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/68818
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
2023-03-15 21:03:41 +00:00
Bobby R. Bruce
b305019ac4 python: Replace 'getargspec' with 'signature' in SimObject.py
In Python 3.11 'inspect.getargspec' has been removed. It has been
marked for deprecation since 3.5. The SimObject.py class has therefore
been rewritten to use 'inspect.signature' instead.

Change-Id: I9efd831e05e0b1619f366ffe722abb0a072fd519
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/68817
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2023-03-15 21:03:41 +00:00
Roger Chang
fa0795ff5b arch-riscv: Add new misa bit union
The new misa bit union type can help get and set misa CSR more
clearily

Change-Id: Id48b140968a0e8021b09782815aa612b409ac75b
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/68917
Reviewed-by: Bobby Bruce <bbruce@ucdavis.edu>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
2023-03-15 01:18:09 +00:00
Razeza
a589d7b569 arch-x86: Add instructions from SSE4.1 set.
The following instructions were implemented: PHMINPOSUW, ROUNDSS, ROUNDSD, EXTRACTPS, INSERTPS, PMULLD, PMULDQ,
PCMPGTQ, PMINUW, PMINUD, PMINSB, MINSD, PMAXUW, PMAXUD, PMAXSB, PMAXSD, PEXTRB, PEXTRW for memory, PEXTRD, PEXTRQ,
PINSRB, PINSRD, PINSRQ, PACKUSDW, PBLENDW, BLENDPS, BLENDPD, BLENDVPD, BLENDVPS, PBLENDVB, PMOVSXDQ, PMOVSXWQ,
PMOVSXWD, PMOVSXBQ, PMOVSXBD, PMOVSXBW, PMOVZXDQ, PMOVZXWQ, PMOVZXWD, PMOVZXWD, PMOVZXBQ, PMOVZXBD, PMOVZXBW.

Also fix bug in PACKUSWB_XMM_M, it was marked as sign operation, though it is unsigned.

Jira Issue: https://gem5.atlassian.net/browse/GEM5-1308

Change-Id: I1a8d26c0426690841dcc80a6fa5dcffb8cbc5d9a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/67737
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
Reviewed-by: Bobby Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
2023-03-13 10:24:16 +00:00
Gabriel Busnot
99852d5687 sim: Deprecate pointer version of MemberEventWrapper constructor
It makes no sense to initialize such event with nullptr. Favor the
reference version for safer behavior.

Change-Id: I695f41362a56aca98ceb52d49cf84be43f1465a2
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/67656
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Daniel Carvalho <odanrc@yahoo.com.br>
2023-03-13 06:47:09 +00:00
Gabriel Busnot
ba19f967d7 sim: Use ref constructor of MemberEventWrapper everywhere
Change-Id: I77989aa7318142634c771c558293138e7b1e8e51
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/67657
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
2023-03-13 06:47:09 +00:00
Gabriel Busnot
7813e294ff sim: Deprecate EventWrapper in favour of MemberEventWrapper
Change-Id: I87363fb36cd998e7f0afeb25381e5b230a15b493
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/67654
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Tested-by: kokoro <noreply+kokoro@google.com>
2023-03-13 06:47:09 +00:00
Gabriel Busnot
1bb8cd3d44 sim: Switch from EventWrapper to MemberEventWrapper before deprec
Change-Id: I25c81787d522a0dd063112b6727669da46e0f0e7
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/67655
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
2023-03-13 06:47:09 +00:00
Gabriel Busnot
4ec432caa4 sim: Define a new MemberEventWrapper event class
This new event class simplifies the use of EventWrapper and aims at
superseeding it. EventWrapper has been redefined in terms of
MemberEventWrapper.

MemberEventWrapper makes use of the new type traits to simplify
template parameterization and encourage its use over SimpleEvent that
often wraps a lambda that merely calls a member function.

Change-Id: Ie59e4c51705b9c2b2faa27097678d7d85f5b99c6
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/67653
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
2023-03-13 06:47:09 +00:00
Gabriel Busnot
9fe9b2853c base: Create a gem5 type_traits.hh header
That header currently contains type traits that derive the class, the
return type and the arguments of a member function from a pointer to
that member function.

Change-Id: I41dd41056f507016219d6111d25c8cb4c2ad3439
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/67652
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Daniel Carvalho <odanrc@yahoo.com.br>
Tested-by: kokoro <noreply+kokoro@google.com>
2023-03-13 06:47:09 +00:00
Hoa Nguyen
3fe129e8ea stdlib: use atomic_noncaching when using AtomicSimpleCPU with Ruby
mem_mode is supposed to be atomic_noncaching when running
AtomicSimpleCPU with Ruby cache.

Change-Id: Icb419f9370038f5c1f80dd879b187338279a5b93
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/68877
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2023-03-12 02:44:40 +00:00
Hoa Nguyen
6841e1aa5a stdlib: Fix bug in MESI_Three_Level_Cache initialization
Change-Id: I2d06c842955aa1868053a0d852fc523392480154
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/68857
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
2023-03-12 02:44:40 +00:00
Alex Richardson
79d407280c arch-riscv: Fix invalid std::map access
The CSRData map uses a RISC-V CSR number as the key rather than one of
the MISCREG_* enumerators. Use MiscRegNames[] instead to stringify the
argument for the debug message.

Change-Id: I2533bc29d148d3b34c01022eeaeedf64c39a99b9
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/68759
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2023-03-09 09:38:32 +00:00
Alex Richardson
54e06f88c2 tests: Fix import path in simple_binary_run.py
We should be using gem5.components instead of python.gem5.components.
In https://gem5-review.git.corp.google.com/c/public/gem5/+/68518 I was
seeing the RISC-V tests fail with
`ModuleNotFoundError: No module named 'python.gem5.components.processors.base_cpu_core'`.

This fixes the issue for me with the RISC-V tests. I also searched for
other similar imports and I've removed a similar (unused) one in
x86_boot_exit_run.py.

Change-Id: I61a0c4c27724854956f778f14e1fcfafea927ffd
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/68757
Reviewed-by: Bobby Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
2023-03-09 09:36:23 +00:00
paikunal
cdab011373 configs: Adds an example script for POWER Hello
Used the "power-hello" resource to make an
stdlib example script for that resource

Change-Id: Ia8a051330e263617aa0e2ef08321d01cfa1093c4
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/68737
Reviewed-by: Boris Shingarov <shingarov@labware.com>
Maintainer: Boris Shingarov <shingarov@labware.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2023-03-08 03:43:44 +00:00
Nicolas Boichat
4c8ad56072 fastmodel: Check early for license server issue
We have a setup that requires manual startup of an ssh proxy to
access license server, and without that, gem5 takes about a minute
until the license checkout times out (until then, it's unclear
why nothing is happening).

We asked ARM for a way to decrease timeouts, but that doesn't
seem to be easy to do.

Change-Id: I37b84fd52cb7fb221a9e48dcb52a33a11f4d1580
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/68177
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2023-03-07 23:21:15 +00:00
Bobby R. Bruce
85342dbb0e cpu: Revert CPU stats changes
This reverts this relationchain:
https://gem5-review.googlesource.com/c/public/gem5/+/67396/6

This was pre-maturely submitted before all testing and checking was
done. To be safe this has been reverted. When all testing and checks are
completed, this revert will be undone.

Change-Id: I2a88cadfee03c1fc81932e6548938db108786dd2
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/68717
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
Reviewed-by: Bobby Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
2023-03-07 21:42:54 +00:00
Alex Richardson
18ba4e1278 tests: Fix GCC -W(maybe-)uninitialized warnings
These all look like valid (but harmless) diagnostics to me and are
all simple to fix. Most of them can be fixed by using ASSERT_* variants
of the GTest checkers to ensure that the remainder of the function is
not executed and the uninitialized result isn't touched.

Change-Id: Ib5fe2ac2ec539c880d670ebc3321ce98940c7e38
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/68517
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
Reviewed-by: Bobby Bruce <bbruce@ucdavis.edu>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
2023-03-07 09:23:25 +00:00
Matt Sinclair
b440355cbc tests: cleanup m5out directly in weekly
The weekly test script was implicitly assuming that no m5out
directory existed in the folder where the script was run.
However, if a prior test ran and failed, it would not clean up
its m5out directory, causing the weekly tests to fail.

This commit resolves this by removing the m5out directory before
trying to run any tests in the weekly script.  Moreover, we also
update the weekly script to explicitly remove this m5out directory
at the end of the script.

Change-Id: If10c59034528e171cc2c5dacb928b3a81d6b8c50
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/67198
Reviewed-by: Bobby Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
2023-03-07 05:03:41 +00:00
Roger Chang
8a9a629bdb arch-riscv: Support PMP lock feature
The lock feature will let M mode do memory permission check before
R/W/X data. If the lock bit of pmpicfg set, then the pmpicfg and
pmpaddri will ignore the update value later until CPU reset, and
pmpaddri-1 will ignore if the TOR A field is set.

The following is add in CL:
1. Add condition to run PMP check when any lock bit of pmp tables
   is set
2. Add PMP_LOCK bit check when try to update pmpaddr and pmpcfg
3. If there is no PMP entry matches and priviledge mode is M,
   no fault generated
4. If the address matches PMP entry, return no fault if priviledge
mode is M and lock bit is not set

For more details about PMP, please see RISC-V Spec Volumn II,
Priviledge Archtecture, Ver 1.12, Section 3.7 Physical Memory
Protection

Change-Id: I3e7c5824d6c05f2ea928ee9ec7714f7271e4c58c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/68057
Reviewed-by: Ayaz Akram <yazakram@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Yu-hsin Wang <yuhsingw@google.com>
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
2023-03-07 03:10:45 +00:00
Melissa Jost
457d70df62 cpu-kvm: Implement IPC and CPI base stats for KVM CPU
Replaced committedInsts stats of KVM CPU with commitStats.numInsts
of BaseCPU. This results in IPC and CPI printing in stats.txt for
KVM simulations.

Change-Id: I02395630fc50a69adebf11f4ed39d9cefb852e1f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/67396
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2023-03-07 00:17:25 +00:00
Melissa Jost
0974fe6f24 cpu-o3: Move O3 IEW stats to BaseCPU::ExecuteCPUStats
Moved numInsts, numBranches, numNop, numRefs, numLoadInsts, numRate to
Base. Merged numRefs into numMemRefs of ExecuteCPUStats. Renamed
numRate to instRate. Updated formatting in ExecuteCPUStats group.

Change-Id: I1fd3a989d917eb2ffaa865b067b80e266d6f55bc
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/67395
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
2023-03-07 00:17:25 +00:00