Commit Graph

19860 Commits

Author SHA1 Message Date
Bobby R. Bruce
b4b024808e stdlib: Fix checkpoint setting through set_workload func
Due to a typo ('checkpoint_dir' instead of 'checkpoint'), setting
checkpoints via the set_workload functions was not working. This patch
fixes this error.

Change-Id: I5720406f2a01f166666e80079c1f84651f750fe2
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/68277
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
Reviewed-by: Bobby Bruce <bbruce@ucdavis.edu>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2023-02-23 12:07:30 +00:00
Bobby R. Bruce
55348d062c configs,stdlib: Update simpoint-se-restore checkpoint
This patch fixes the checkpoint resource for the simpoints-se-restore.py
script.

Change-Id: I29698844023c54fdc645c99da4a19c77bae58729
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/68338
Reviewed-by: Bobby Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
2023-02-23 12:07:30 +00:00
Bobby R. Bruce
ce516397da configs stdlib: Update checkpoint resource for riscv-hello
This change updates the riscv-hello-restore-checkpoint.py script's
checkpoint for one compatible with v23

Change-Id: Idee262491db45049d9afe69190bc8890d75c8cdf
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/68337
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
Reviewed-by: Bobby Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
2023-02-23 12:07:30 +00:00
Bobby R. Bruce
5d0dd10cfa stdlib: Add LooppointJsonResource resource
This resource wraps the LooppointJsonLoader class for use with gem5
resources.

Change-Id: Ic00d689c289330bab8564abc4c68a9047d5096e0
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/67858
Reviewed-by: Bobby Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
2023-02-23 12:07:30 +00:00
Bobby R. Bruce
4ad1150372 stdlib: Add the LooppointCsvResource resource
This resource wraps the LooppointCsvLoader class so it may be obtained
as a specialized resource via gem5 resources.

Relevant tests and config scripts have been updated.

Change-Id: Ib8e5ff5500fb1560951c9c0110e3c3aec8ca3c42
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/67857
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
Reviewed-by: Bobby Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
2023-02-23 12:07:30 +00:00
Bobby R. Bruce
29b19530ce tests: Incorporate Looppoint example scripts into TestLib
Change-Id: I97d89d3cc80ce8d8991ca8d3cb4aab8019324d76
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/67758
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby Bruce <bbruce@ucdavis.edu>
2023-02-23 12:07:30 +00:00
Bobby R. Bruce
52194c87b0 tests: Add pyunit tests for Looppoint
Change-Id: Ie275e50bbcf5fb3d38ee98d7ada27c3afe4ec1b0
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/67757
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
Reviewed-by: Bobby Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
2023-02-23 12:07:30 +00:00
Bobby R. Bruce
aae3430281 stdlib: Refactor Looppoint
This change refactors the Looppoint files. While functionally
equivalent, this classes have been moved and altered to be easier to
handle going forward. The following changes have been made:

- New classes have been added to represent the data structure of the
  Looppoint JSON. This simplifies the parsing of JSON files and makes it
  handle Looppoint data structures. Ultimately this is hidden from the
  user via the new 'gem5.resources.Looppoint' class which will be the
  front-facing class for Looppoint interactions.
- The `LooppointCheckpoint` class has been replaced with
  `LooppointCsvLoader`. This new class takes in a CSV pintpoints file
  to load necessary looppoint data.
- The `LoopPointRestore` class has been replaced by
  `LooppointJsonLoader`.
- All Looppoint classes have been moved to `gem5.resources`. This will
  make it easier when we add Looppoints as specific gem5 resources.

Change-Id: I11dd1fe8f76658db220320584270d57cb37a3c62
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/67611
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
2023-02-23 12:07:30 +00:00
Bobby R. Bruce
f59d860e51 stdlib: Add looppoint example scripts
Change-Id: If9827af9ba7958af492a6c09cf83e4f6dac9a2eb
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/67493
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
Reviewed-by: Bobby Bruce <bbruce@ucdavis.edu>
2023-02-23 12:07:30 +00:00
Bobby R. Bruce
82aec1c19b stdlib: Update LoopPointRestore to take singular region_id
This change has been introduced as we only restore to one checkpoint at
a time. The change updates LoopPointRestore to take a sigular region_id
and use it to generate the LoopPpoint from the LoopPoint JSON file.

Change-Id: I0e88d5ba03b164bdd5da098397f44e16af591134
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/67492
Reviewed-by: Bobby Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
2023-02-23 12:07:30 +00:00
Bobby R. Bruce
de5044cfe0 stdlib: Change the default Looppoint JSON output to m5out
Change-Id: I6ac9aa55dfd4a0250c487ae743a1f4ea0b1bc154
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/67491
Reviewed-by: Bobby Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
2023-02-23 12:07:30 +00:00
Zhantong Qiu
afbca3b6e7 stdlib: Added LoopPoint checkpoint specific generator
Added looppoint_save_checkpoint_generator to take checkpoints for
LoopPoint methodology.
Users can decide to update the relative counts storing in the LoopPoint
module and exit when all the target PC-count pairs are encountered or
not.

Change-Id: Id1cf1516f4fa838e20a67530e94b361e42ca09f3
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/67197
Reviewed-by: Bobby Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
2023-02-22 19:30:09 +00:00
Zhantong Qiu
82c587bd88 stdlib: Allow se_binary_workload to setup LoopPoints
Added a set_se_looppoint_workload function to take in information for
workload and a stdlib LoopPoint object that stores all the information
the workload needed to run the LoopPoint sampling method.
Added a get_looppoint function to return the stdlib LoopPoint object.

Change-Id: I7afc5c4c743256f7df97345f331b6f72b7a5fd07
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/67196
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
Reviewed-by: Bobby Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
2023-02-22 19:30:09 +00:00
Zhantong Qiu
41816bf030 stdlib: Added stdlib LoopPoint classes
LoopPoint is a multithreaded workload sampling method that targets
PCs and PC execution counts.
The main idea for LoopPoint is to base the beginning and end of the
simjulation sample on the number of times a particular loop (PC) has
been executed globally across all threads in a region that partitioned
with a set length of instruction counts. This in some senses
generalizes SimPoint which use the instruction count of a single
thread.
The link to the paper: https://ieeexplore.ieee.org/document/9773236

The LoopPointCheckpoint is designed to take in LoopPoint data file
and generate the information needed to take checkpoints for LoopPoint
regions(warmup regions+simulation region)
The LoopPointRestore is designed to take in the LoopPOint data file
and generate information needed to to restore a checkpoint taken by
the LoopPOintCheckpoint.
The LoopPoint is the parent class for LoopPointCheckpoint and
LoopPointRestore.

Change-Id: I595b0ff9d350c7c496639748a9c63ecc61fbaec9
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/67195
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
2023-02-22 19:30:09 +00:00
Zhantong Qiu
0d129a6bf2 sim: Added PcCountTracker and PcCountTrackerManager
PcCountTracker is a probelistener that connects to one core and listens
for a list of Program Counter addresses(PCs). It notifys the
PcCountTrackerManager every time it encounters a Program Counter
address in the list.
PcCountTrackerManager is a SimObject that is responsible for keeping
track of a list of PC-count pairs and the number of time a particular
PC has been executed globally.

This patch adds a way to track the number of times a set of specific
PCs have been executed.

Change-Id: I8f47bfa7e29aa2bb6ab817417266033439b85d51
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/67194
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
Reviewed-by: Bobby Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
2023-02-22 19:30:09 +00:00
Zhantong Qiu
717d3b239c base,python: Added PcCountPair type and parameter
This commit introduces a PcCountPair type that stores a Program Counter
address and an integer of counts for the Program Counter address.
The PcCountPair can be used in the same way and hashable in both C++
and Python.

Change-Id: I66d93e2c6a1d286cb9dd795ba97f8d887f67d503
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/67193
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
2023-02-22 19:30:09 +00:00
Bobby R. Bruce
e1601954f0 stdlib: Implement Simpoint Resources
This patches does the following:
- Adds 'SimpointResource' which encapsulates Simpoint data and
  functionality. It replaces the old 'gem5.util.simpoint.SimPoint'
  class. Simpoints can be loaded from gem5-resources using the
  `obtain_resource` function.
- Adds 'SimpointDirectoryResource'. This inherits form
  'SimpointResource'. While 'SimpointResource' takes raw Simpoint data
  via parameters, 'SimpointDirectoryResource' assumes the data exists
  in files, in a directory.
- Updates the
  "configs/example/gem5_library/checkpoints/simpoints-se-checkpoint.py"
  and
  "configs/example/gem5_library/checkpoints/simpoints-se-restory.py"
  example files to utilize this new Simpoint resource classes.

**Note**: While the old "SimPoint" class
("src/python/gem5/util/simpoint.py") is marked as deprecated, it may be
difficult to utilize given updates to the APIs in the gem5 stdlib Cores
and Simulator modules.

Change-Id: I9bed5c643ffc735838c9f22a58c53547941010e7
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/67339
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
2023-02-22 19:30:09 +00:00
Bobby R. Bruce
cc838d72a6 stdlib: Update resources to have downloads optional
With this patch, when a resource entry does not specify a "url" field,
there is no file downloaded. This is necessary infrastructure for
gem5-resources which do not have specific files/directories to be
downloaded but exist solely in the resources.json file.

Change-Id: I0d92e830bfcef750119078b8c226b0659ba7f6cb
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/67338
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
2023-02-22 19:30:09 +00:00
Bobby R. Bruce
a9b69ee055 stdlib: Add null/None versioning in resources.json
This patch allows for the "version" field in the resources.json file to
be `null` (translated to `None` in the Python JSON package) or not
declared. In this case the resources.json file will be used regardless
as to what version the gem5 binary is set. This is useful for testing
purposes.

Tests have been updated to utilize this where possible.

Change-Id: I9d8ae18cb3e61d58bc822bad30853fa3442cb33f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/67337
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
2023-02-22 19:30:09 +00:00
Bobby R. Bruce
4ee724e054 stdlib: Specialize the gem5-resources
This commit specializes the Resource class into specific sub-types.

The `Resource`, `CustomResource` and `CustomDiskImageResource` classes
have been deprecated in favor of the `AbstractResource` subclasses.
Custom Resources can be created via the resource specialization
constructor. Resources can be obtained via the gem5-resource
infrastructure with the `obtain_resource` function.

Fully implemented:

- DiskImageResource
- BinaryResource
- KernelResource
- BootloaderResource
- FileResource
- DirectoryResource

Partially implemented:

- SimpointResource
- CheckpointResource

While the schema of the resource.json file has changed, efforts have
been made to ensure backwards compatibility is maintained during this
transition.

Tests are included in this commit to verify this feature works as
expected.

**Note:** The Simpoint tests are disabled in this commit, to be
reenabled when Simpoint resource specialization is fully incorporated
here:
https://gem5-review.googlesource.com/c/public/gem5/+/67339

Change-Id: I77277ecaffc7abc86db08526aacc0b606ef04fe8
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/67175
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
2023-02-22 19:30:09 +00:00
Bobby R. Bruce
3892ee029a configs: Deprecate fs.py and se.py scripts
Ideally, 'configs/common' should also be deprecated, but some tests still
depend on this directory.

Change-Id: I7c0cbf1f854e1dec9308b6802d6fb70c9af97fc0
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/68157
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
2023-02-22 11:26:49 +00:00
Ivan Turasov
c995d96956 arch-arm: Add missing <array> header in regs/misc.hh
Adding the header avoids "error: implicit instantiation of undefined template 'std::array..."
error that halted the build process on macOS.

Relevant discussion on Slack with Gabriel Bunsot

Change-Id: I935d7045f4b2c01ecef7c663de7c1e9408eead57
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/68217
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
2023-02-21 18:36:13 +00:00
Yan Lee
4dfc312d6d base: extensible: add example codes of extension
Change-Id: Iaab1f2998a3f621b86d63bed7274373ba433d71c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/68017
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2023-02-21 06:03:05 +00:00
Yan Lee
4c9253761f mem: add extension mechanism into Request
Change-Id: Ie144e0cf243bab6d9ddbea79caf559c7e774a787
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/67958
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Yu-hsin Wang <yuhsingw@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
2023-02-21 06:02:54 +00:00
Yan Lee
c913c098a6 mem: add extension mechanism into Packet
Change-Id: Ieda941f73078d98ad7896a376d95dd1573c938e6
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/67957
Reviewed-by: Yu-hsin Wang <yuhsingw@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2023-02-21 06:02:44 +00:00
Nikos Nikoleris
df0bed6858 python: Ensure that m5.internal.params is available
Add an import to m5.internal.params which became necessary after:

95f9017c2e configs,python: Clean some cruft out of m5.objects.

This import is necessary but also causes problems when scons calls
build_tools/sim_object_param_struct_hh.py to generate
params/SimObject.hh. m5.internal.params itself imports _m5 and _m5 is
unavalailable resulting in an ImportError. This is bening and we can
safely ignore it.

Change-Id: I3809e81284e730fb9c9e0e7e91bd61b801d73f90
Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/67797
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
2023-02-20 13:40:40 +00:00
Yan Lee
109c327209 base: add extensible type
Extensible is for carrying additional user-defined
information. Each type of the extension will have a unique
extension ID and there is a linked list of extension in every
Extensible object. There will be most one extension with the same type in
the linked list. With the shared_ptr, the extension will be
deleted automatically. That is, the caller should allocate
the extension and add into the packet.

Change-Id: I54729536a305c91c751d5fb059bd2f9a3db05523
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/62892
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
2023-02-17 03:51:19 +00:00
Matthew Poremba
f028bd55e0 arch-vega: Update API for some flat atomics
Some recently submitted atomic instructions were using two older APIs.
Update these to use the newer APIs to support all apertures and avoid
compilation issue.

Change-Id: Ibd6bc00177d33236946f54ef8e5c7544af322852
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/67977
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
2023-02-16 03:28:25 +00:00
Roger Chang
3b4f241fb5 arch-riscv: Fix incorrect trap value of instruction fault
As we add rv_type bit in machInst at 62, It will get the machine
code with rv_type specification if we just return machInst. We
only need return machine code for handling instruction fault.

Change-Id: I9dd7a25047d4a13df5b47dc9e422345ba44b7b09
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/67677
Reviewed-by: Yu-hsin Wang <yuhsingw@google.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2023-02-16 00:59:49 +00:00
Roger Chang
4b1c245420 arch-riscv: Fix the behavior of write to status CSR
According to RISC V spec Volumn I, Section 11.1, the CSR will be
written only if RS1 != 0 or imm != 0. However, after the change
of CL(https://gem5-review.googlesource.com/c/public/gem5/+/67717),
it will cause IllegalInstFault to write status CSR if we don't
change the data.

Example of Instruction Fault for mstatus

```
addi a5, zero, 8
csrc mstatus, a5
```

It will cause instruction fault if mstatus value is 0 due to
"newdata_all == olddata_all". We can just simply check if
the data value is changed out of mask.

Change-Id: Iab4ce7ac646a9105dc04e69c24d084572e28ebab
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/67897
Reviewed-by: Yu-hsin Wang <yuhsingw@google.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2023-02-15 06:36:39 +00:00
hungweihsu
e10be09dcf dev: add method to set initial register value out of constructor.
The initial value of register is set in constructor but there is no
standard way to assign the initial value and default value at the same
time out of that. So we decided to add an extra method to set the
initialValue to current register value. The usecase would be:

reg.get().field1 = val1;
reg.get().field2 = val2;
reg.resetInitialValue();

Change-Id: Ibc5454e2945cc6aff943e6599043edd8ca442f5f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/67917
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
2023-02-15 02:07:09 +00:00
Matthew Poremba
ea9239ae09 dev-amdgpu: Update deprecated ports
Change-Id: Icbc5636c33b437c7396ee27363eed1cf006f8882
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/67837
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
2023-02-14 18:57:33 +00:00
Alexandru Dutu
bb8f370e4d arch-vega: Implementing global_atomic_smax
Change-Id: Id4053424c98eec1e98eb555bb35b48f0b5d2407b
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/64513
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2023-02-14 18:57:14 +00:00
Alexandru Dutu
8375058e73 arch-vega: Implementing global_atomic_smin
Change-Id: Iffb366190f9e3f7ffbacde5dbb3abc97226926d4
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/64512
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
2023-02-14 18:57:14 +00:00
Alexandru Dutu
d7516a26dc arch-vega: Implementing global_atomic_or
Change-Id: I13065186313ca784054956e1165b1b2fd8ce4a19
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/64511
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
2023-02-14 18:57:14 +00:00
Matthew Poremba
39b5b5e511 dev-amdgpu: Fix address in POLL_REGMEM SDMA packet
The address for the POLL_REGMEM packet should not be shifted when the
mode is 1 (memory). Relevant driver code below is not shifting the
address. The shift is causing a page fault due to the incorrect address.

This changeset removes the shift so the correct address is translated.

https://github.com/RadeonOpenCompute/ROCK-Kernel-Driver/blob/
    roc-4.3.x/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c#L903

Change-Id: I7a0ec3245ca14376670df24c5d3773958c08d751
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/67877
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2023-02-14 15:36:56 +00:00
Zhengrong Wang
b6a591e203 mem-dram: Make sure SHOW_SIM_OUTPUT is in global namespace.
As stated in the comment, SHOW_SIM_OUTPUT is declared extern
in the DRAMSim2 print macros. Therefore, it should be defined
in the global namespace, not in gem5 namespace.

Change-Id: I05245a48ac706b46085ffa8d00db3725ce16a89e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/67859
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2023-02-13 20:50:06 +00:00
Zhengrong Wang
39e813374c ext: Fix typo in DRAMSIM2 Sconscript
ClockDoenv should be ClockDomain.

Change-Id: Ibcf3d0dc969624a4e20d86924ef834781b5bbf21
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/67759
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
2023-02-09 20:56:55 +00:00
Matthew Poremba
bc9e90d65e arch-vega: Make VGPR-offset for global SGPR-base signed
The VGPR-offset used when SGPR-base addressing is used can be signed in
Vega. These are global instructions of the format:
`global_load_dword v0, v1, s[0:1]`. This is not explicitly stated in the
ISA manual however based on compiler output the offset can be negative.

This changeset assigns the offset to a signed 32-bit integer and the
compiler takes care of the signedness in the expression which calculates
the final address. This fixes a bad address calculation in a rocPRIM
unit test.

Change-Id: I271edfbb4c6344cb1a6a69a0fd3df58a6198d599
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/67412
Reviewed-by: Bobby Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
2023-02-09 17:08:34 +00:00
Matthew Poremba
905b8ebd22 arch-vega: Implement ds_write_b8_d16_hi
Writes a byte to the upper 16-bit input word to an address.

Change-Id: I0bfd573526b9c46585d0008cde07c769b1d29ebd
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/67411
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2023-02-09 17:08:34 +00:00
zhongchengyong
89c49d1ab0 arch-riscv: Fix the CSR instruction behavior.
The RISC-V spec clarifies the CSR instruction operation, some of them
shall not read or write CSR by the hints of RD/RS1/uimm, but the
original version use the 'data != oldData' condition to determine
whether write or not, and always read CSR first.
See CSR instruction in spec:
Section 9.1 Page 56 of https://github.com/riscv/riscv-isa-manual/releases/download/Ratified-IMAFDQC/riscv-spec-20191213.pdf

Change-Id: I5e7a43cf639474ae76c19a1f430d314b4634ce62
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/67717
Reviewed-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
2023-02-09 09:00:46 +00:00
Gabe Black
bd9e126d5e cpu: Add a generic model_reset port on the BaseCPU.
This port will stop execution on the CPU when raised. When lowered, it
will allow execution to reset the state of the CPU and allow execution
to resume. The state could theoretically be reset when the reset state
starts, but then it wouldn't reflect the most up to date condition of
the CPU when resuming. For instance, if a reset vector was set
somehow, that wouldn't be updated if it was changed while reset was
asserted. The tradeoff is that the state won't look like it will when
execution resumes while reset is held (to GDB for instance), but that
seems like a more obvious and less common sort of problem.

This signal is managed by the BaseCPU itself, but is backed by a
virtual method which can be overridden by other CPU types which may
not work the same way or have the same components. For instance, a
fast model CPU could toggle reset lines on the underlying model and
let it handle resetting all the state.

The fast models in particular already have a generic reset line with
the same name, but they have it at the level of the fast model which
may have multiple cores within it, each represented by a gem5 CPU.

It isn't implemented here, but there could be some sort of cooperation
between these signals where the reset at the core level is considered
an "or" of the cluster level reset and the individual core level
resets. At least in the A76 model, there are resets for each individual
core within the cluster as well, which the generic reset toggles.

Another option would be to get rid of the whole cluster reset pin, and
make the user gang the resets for each of the cores together to
whatever reset signal they're using. That's effectively what the
cluster level reset is doing, but within the C++ of the model wrapper
instead of in the python config.

Change-Id: Ie6b4769298ea224ec5dc88360cbb52ee8fbbf69c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/67574
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Roger Chang <rogerycchang@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Reviewed-by: Yu-hsin Wang <yuhsingw@google.com>
2023-02-09 02:04:25 +00:00
Gabe Black
d1f76741c6 dev: Add a definition for VectorResetResponsePort.
This is just a simple extension of the regular ResetResponsePort, and
is useful if there is a collection of reset pins on a device.

Change-Id: I6ccb21e949d3a51bf8b788ffd23e4b2b02706da9
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/67576
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Yu-hsin Wang <yuhsingw@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
2023-02-09 02:04:10 +00:00
Melissa Jost
aee282b79f tests: Update testing documentation
This edits the documentation regarding the usage of the --isa
tag, as this has fallen out of date in regards to the new
'ALL' isa.

Change-Id: I3b672ac2c03dd109bba458db688af05ed4135a91
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/65651
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
2023-02-08 21:23:16 +00:00
Earl Ou
e44cbe724b sim: handle async events in main thread only
In the current implementation pollqueue is not thread safe. The design
of multi threads handle async events is thus causing issue in parallel
environment. Given the low rate of async events, it should be OK to only
handle them in the main thread to avoid unexpected racing issues.

Change-Id: Iddd512235e84e9d77f60985bb1771aa4cc693004
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/67533
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Yu-hsin Wang <yuhsingw@google.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2023-02-08 00:28:02 +00:00
Earl Ou
7371e46822 mem: use default backdoor behavior for thread_bridge
The original backdoor implementation is incorrect. We use simply
fallback to default (disable backdoor) as backdoor across threads is not
thread-safe in most of cases.

Change-Id: Ia39be0dda4f16917cc3565eb5b012270e6d7697a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/67531
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Yu-hsin Wang <yuhsingw@google.com>
2023-02-08 00:27:54 +00:00
Gabriel Busnot
8a774e07b2 dev-amdgpu: Patch forgotten port after mem port owner deprecation
Change-Id: I82f88b8962d9f04521e549ca1383c42f2b5b3ffc
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/67631
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby Bruce <bbruce@ucdavis.edu>
2023-02-07 13:29:55 +00:00
Gabe Black
a513e06a1b fastmodel: Export the reset signals of the GIC.
These are the "reset" and "po_reset" lines. It seems reasonable that
these are the normal reset and the power on reset signals, but that's
not spelled out in the fast model "lisa" file, nor does it explain
exactly what the difference is between them.

Change-Id: I686b4d973fc3cfff8a3ec05f8c95ee2cb6ff6698
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/67575
Reviewed-by: Jui-min Lee <fcrh@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2023-02-04 07:30:32 +00:00
Wei-Han Chen
59e16b5695 fastmodel: forward stream ID to gem5
This CL enables forwarding stream ID from amba_pv to gem5 world.

The stream ID information is originally stored in master_id of
pv::TransactionAtrribute, then it will be stored to m_id of
amba_pv::amba_pv_extension.

This CL brings the information to stream ID field of
Gem5SystemC::ControlExtension. Then the information can be set to stream
ID of the gem5 packet's request.

After bringing the information to gem5, we can identify the packet's
stream ID from gem5 side. One example usage is PL330. In PL330_DMAC, each
transaction is associated with a stream ID. If we can identitfy the
stream ID, we can, for example, set attribute to specific DMAC channel.

Change-Id: I943ce49fde57b0bcfc18b58c7566eec61cc676f4
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/67591
Reviewed-by: Yu-hsin Wang <yuhsingw@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
2023-02-04 06:23:03 +00:00
Wei-Han Chen
a2d321d475 fastmodel: change the constructor of bridges
This CL changes the construction of bridges between amba and tlm. This
enables us to add parameters when using this bridge.

Change-Id: I4bbbe8fb1c2573a796a3a0a7976adf3553bbaa86
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/67297
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Yu-hsin Wang <yuhsingw@google.com>
2023-02-04 06:23:03 +00:00