Commit Graph

8 Commits

Author SHA1 Message Date
Shivani Parekh
392c1ced53 misc: Replaced master/slave terminology
Change-Id: I4df2557c71e38cc4e3a485b0e590e85eb45de8b6
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33553
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-09-10 23:02:28 +00:00
Shivani Parekh
cf43bc3c8b mem: Update port terminology
Change-Id: Ib4fc8cad7139d4971e74930295a69e576f6da3cf
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32314
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-08-26 16:48:13 +00:00
Nikos Nikoleris
35d9bf99a8 mem: Fix latency handling in MemDelay
MemDelay wouldn't consume pre-existing delays in the packet and
therefore the latency it adds would overlap with them. This patch
fixes the MemDelay to properly account for them.

Change-Id: I7330fbf1c8161a21523a0b4aab31c72e34bce650
Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/30055
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-06-16 16:13:43 +00:00
Gabe Black
921a72f4f3 mem: Delete authors lists from mem files.
Change-Id: I439d64d01950463747446a8177086eb276b8db55
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25443
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
2020-02-17 21:51:08 +00:00
Gabe Black
cdcc55a6a8 mem: Minimize the use of MemObject.
MemObject doesn't provide anything beyond its base ClockedObject any
more, so this change removes it from most inheritance hierarchies.
Occasionally MemObject is replaced with SimObject when I was fairly
confident that the extra functionality of ClockedObject wasn't needed.

Change-Id: Ic014ab61e56402e62548e8c831eb16e26523fdce
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18289
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Gabe Black <gabeblack@google.com>
2019-04-28 01:19:40 +00:00
Gabe Black
d3d24835bc arch, cpu, dev, gpu, mem, sim, python: start using getPort.
Replace the getMasterPort, getSlavePort, and getEthPort functions
with getPort, and remove extraneous mechanisms that are no longer
necessary.

Change-Id: Iab7e3c02d2f3a0cf33e7e824e18c28646b5bc318
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17040
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-03-19 10:22:50 +00:00
Robert Kovacsics
2f17062dd9 mem: Rename Packet::checkFunctional to trySatisfyFunctional
Packet::checkFunctional also wrote data to/from the packet depending
on if it was read/write, respectively, which the 'check' in the name
would suggest otherwise. This renames it to doFunctional, which is
more suggestive. It also renames any function called checkFunctional
which calls Packet::checkFunctional. These are

- Bridge::BridgeMasterPort::checkFunctional
  - calls Packet::checkFunctional
- MSHR::checkFunctional
  - calls Packet::checkFunctional
- MSHR::TargetList::checkFunctional
  - calls Packet::checkFunctional
- Queue<>::checkFunctional
  (of src/mem/cache/queue.hh, not src/cpu/minor/buffers.h)
  - Instantiated with Queue<WriteQueueEntry> and Queue<MSHR>
- WriteQueueEntry
  - calls Packet::checkFunctional
- WriteQueueEntry::TargetList
  - calls Packet::checkFunctional
- MemDelay::checkFunctional
  - calls QueuedSlavePort/QueuedMasterPort::checkFunctional
- Packet::checkFunctional
- PacketQueue::checkFunctional
  - calls Packet::checkFunctional
- QueuedSlavePort::checkFunctional
  - calls PacketQueue::doFunctional
- QueuedMasterPort::checkFunctional
  - calls PacketQueue::doFunctional
- SerialLink::SerialLinkMasterPort::checkFunctional
  - calls Packet::doFunctional

Change-Id: Ieca2579c020c329040da053ba8e25820801b62c5
Reviewed-on: https://gem5-review.googlesource.com/11810
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
2018-07-23 11:57:50 +00:00
Andreas Sandberg
0f33b2c1d5 mem: Add a memory delay simulator
Add a memory system component that delays traffic. The base
functionality to delay packets is implemented in the abstract MemDelay
class. This class exposes three methods that control packet delays:

  * delayReq(pkt)
  * delayResp(pkt)
  * delaySnoopResp(pkt)

These methods should be specialized to implement delays for specific
packet types.

The class SimpleMemDelay uses the MemDelay base class to implement
constant delays for read/write requests and responses.

The intention is that these classes can be used for rapid prototyping
of components that add a small fixed delay and the same throughput as
the interconnect. I.e., any buffering done in the base class will be
small and proportional to the introduced delay.

Change-Id: I158cb85f20e32bfdbcbfed66a785b4b2dd47b628
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Nicholas Lindsey <nicholas.lindsay@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/11521
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-06-28 16:12:53 +00:00