Commit Graph

15418 Commits

Author SHA1 Message Date
Giacomo Travaglini
7ce081d583 misc: Remove any reference to the ALPHA ISA
Change-Id: Ie761cd69ae0e8e632ca2b92e63a404e8804f0e6f
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/30015
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-06-08 09:00:55 +00:00
Tommaso Marinelli
872cb227fd mem-cache: prevent prefetcher from saturating the write buffer
When the write buffer is full, it still has space to store an additional
number of entries (reserve) equal to the number of MSHRs so that if any
of them requires a writeback this can be handled. Even if the slave port
is blocked, a prefetcher can generate new MSHR entries that may lead to
additional writebacks and eventually saturate the reserve space. This is
solved by checking if the cache is blocked for accesses before
prefetching data.

Change-Id: Iaad04dd6786a09eab7afae4a53d1b1299c341f33
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29615
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-06-04 22:35:15 +00:00
Gabe Black
1d081f5054 systemc: Replace include of eventq_impl.hh with eventq.hh.
eventq_impl.hh has been merged back into eventq.hh, but that change
passed another change which started using eventq_impl.hh in systemc.

Change-Id: I2e9be5f993fe6a6712a121cd955b0c56a33c87e3
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/30014
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-06-04 17:59:31 +00:00
Gabe Black
415abb3a3c sim,mem,dev: Merge eventq_impl.hh into eventq.hh.
Having some methods (which are supposed to be inline) defined in another
file which is only included sometimes creates a lot of opportunities for
errors. They no longer need to be separate, so merge them together.

Change-Id: I5846e55f53f59b9c2081680a6441659265a765f7
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29409
Maintainer: Gabe Black <gabeblack@google.com>
Reviewed-by: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-06-04 01:54:19 +00:00
Gabe Black
d64173549b base,sim: Move DTRACE into base/debug.hh.
All other considerations aside, DTRACE probably fits best in trace.hh
where it is now, but unfortunately that creates an awkward dependence
between that file and eventq.hh and eventq_impl.hh. DTRACE only depends
on flags in the Debug namespace and a universal macro TRACING_ON, so
even though it won't be alongside the things it's most logically
associated with, it will be alongside all of its dependencies.

An alternative would be to re-implement DTRACE in eventq_impl.hh which
wouldn't be too big of a problem because it's so simple, but it's
cleaner and less error prone to still keep a single definition.

Because base/trace.hh includes base/debug.hh, any consumers expecting to
find DTRACE in base/trace.hh will still get that definition, even though
it's no longer direct.

Change-Id: I0dac83295891630686c3a8038eb54138cf40ab44
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29411
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
2020-06-03 22:32:45 +00:00
Gabe Black
89f2d5eb54 misc: Make many includes explicit.
A future change will adjust how some includes can be included
transitively. This change fixes up those files so that they include the
headers they need directly, instead of expecting to have them by
accident through other files.

Change-Id: I1f79aa11df2b46bb7018f39c964294c41db4fdac
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29407
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-06-03 19:42:46 +00:00
Tiago Mück
8c47c0dd63 cpu-o3: fix IQ missing mem barriers
After commit e2a5063e5f some
memory references now tracked as barriers were not having
their completion properly notified to the MemDepUnit.

This patch fixes InstructionQueue and changes MemDepUnit's
completeBarrier to completeInst, which now should be called
for both memory references and barrier instructions.

Change-Id: I28b5f112b45778f6272e71bb3766b364c3d2e7db
Signed-off-by: Tiago Mück <tiago.muck@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29654
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-06-02 18:39:14 +00:00
Bobby R. Bruce
43512da4b2 misc: Merge branch version update into develop 2020-06-02 00:20:23 -07:00
Bobby R. Bruce
332a9de33d misc: Updated release notes and version to v20.0.0.1 2020-06-02 00:16:28 -07:00
Bobby R. Bruce
5e3158d593 misc: Merge in 'hotfix-m5-tick-rounding-error' 2020-06-01 22:46:51 -07:00
Hoa Nguyen
4e484ca33e python: Fix m5's tick rounding mechanism
Partially reverts:
https://gem5-review.googlesource.com/c/public/gem5/+/29372 where the
`math.ceil` function was used to fix an issue where 0.5 was rounded to
zero in python3. This has the side effect of giving incorrect clock
frequences due to rounding errors. To demonstrate:

```
>>> import math
>>> 1e-9*1000000000000
1000.0000000000001
>>> int(math.ceil(1e-9*1000000000000))
1001
```

The solution to this problem is to use Python's `decimal` module to
round values.

Issue-on: https://gem5.atlassian.net/browse/GEM5-616
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Change-Id: Ic76736ccb4b6b8c037103a34493aff7d9731d314
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29577
Reviewed-by: Tiago Mück <tiago.muck@arm.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-06-01 19:40:49 +00:00
adarshpatil
0a5ed3076a mem-ruby: Fix for Invalid transition in MOESI_CMP_directory
Send the correct sharer count from the memory directory to the requesting
L2 cache in data message reply.

Jira issue: https://gem5.atlassian.net/browse/GEM5-613

Change-Id: If76de630fd0001816e8836d9bf77961a94faaa7c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29552
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Pouya Fotouhi <pfotouhi@ucdavis.edu>
Reviewed-by: Tiago Mück <tiago.muck@arm.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-05-29 19:31:47 +00:00
Onur Kayiran
5587dd94f0 mem-ruby: Generate address with masking cacheline bits
makeLineAddress function uses m_block_size_bits to create
masked addresses. m_block_size_bits is used to specify
cache, directory, and memory controller interleaving,
and it can be larger than the cache line size.
To generate addresses that can align with the cache line
rather than the interleaving granularity, a version of
makeLineAddress is created to specify bits that need to
be masked.

Change-Id: I06deec4949da7fa46f1d6f7575334f18ee61c786
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28135
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Reviewed-by: Onur Kayıran <onur.kayiran@amd.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
2020-05-28 23:07:08 +00:00
Onur Kayiran
dee6b07006 configs: Specify cache, dir, and mem cntrl interleaving
This changeset allows setting a variable for interleaving.
That value is used together with the number of directories to
calculate numa_high_bit, which is in turn used to set up
cache, directory, and memory controller interleaving.
A similar approach is used to set xor_low_bit, and calculate
xor_high_bit for address hashing.

Change-Id: Ia342c77c59ca2e3438db218b5c399c3373618320
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28134
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-05-28 23:07:08 +00:00
Tuan Ta
e071f60011 mem-ruby: add function to check for stalled msgs of addr
This patch allows a cache controller to check if there
is any stalled message of a specific address in the
stall_map of an input message buffer.

Change-Id: Id2f9bb98a9201a562f2a8cc371e9bb896ac836af
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28133
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-05-28 23:07:08 +00:00
Tuan Ta
524c22041d mem-ruby: add slicc stm to defer enqueueing a message
This patch enables cache controllers to make response
messages in advance, store them in a per-address saved
map in an output message buffer and enqueue them altogether
in the future. This patch introduces new slicc statement
called defer_enqueueing. This patch would help simplify
the logic of state machines that deal with coalesing
multiple requests from different requestors.

Change-Id: I566d4004498b367764238bb251260483c5a1a5e5
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28132
Reviewed-by: Tuan Ta <qtt2@cornell.edu>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-05-28 23:07:08 +00:00
Bobby R. Bruce
90332c45b5 Merge branch 'release-staging-v20.0.0.0' into develop 2020-05-28 15:52:09 -07:00
Giacomo Travaglini
b1b8af0443 system: Remove CNTFRQ_EL0 write from arm64 boot
We don't need this anymore since this is initialized at gem5
construction.

JIRA: https://gem5.atlassian.net/browse/GEM5-611

Change-Id: I42a3d53a4defba498a23d9a7c192dfff5852c1c7
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29613
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: Bobby R. Bruce <bbruce@ucdavis.edu>
2020-05-28 22:44:12 +00:00
Giacomo Travaglini
3dd3c1e893 dev-arm: Make CNTFRQ a GenericTimer parameter
This register should be in theory initialized by the highest
priviledged software. We do this in gem5 to avoid KVM
complications (the gem5 firmware won't run at highest EL)

JIRA: https://gem5.atlassian.net/browse/GEM5-611

Change-Id: I62d368105af48584f2fe9671de7c70b484b40c12
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29612
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: Bobby R. Bruce <bbruce@ucdavis.edu>
2020-05-28 22:44:12 +00:00
Bobby R. Bruce
e53de444f6 misc: Merge branch 'release-staging-v20.0.0.0' into develop 2020-05-28 01:04:16 -07:00
Jason Lowe-Power
e2abf6c157 misc: Update release notes
Change-Id: I3851a3780aae283d4dba5ab5afa20a4a02bc8e6d
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29067
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-05-28 07:49:44 +00:00
Bobby R. Bruce
fc856981d8 misc: Fixed null-pointer arithmetic error
Doing arithmetic on a null pointer is undefined behavior in C/C++. Clang
compilers complain when this occurs. As this MACRO is used twice, and
does nothing important, it has been removed in favor of a more simple
solution. A comment has been added explaining the MACRO's removal.

Change-Id: I42d9356179ee0fa5cb20f827af34bb11780ad1a9
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29534
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-05-28 04:48:54 +00:00
Bobby R. Bruce
a8fb7a0c1d gpu-compute,misc: Removed unused 'vaddr' capture
Clang compilers return a `error: lambda capture 'vaddr' is not used`
error when compiling HSAIL_X86/gem5.opt. This unused lambda capture has
therefore been removed.

Change-Id: I2a7c58174a9ef83435099ab4daf84c762f017dd4
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29533
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
2020-05-28 04:48:54 +00:00
Bobby R. Bruce
e5a2fbb860 mem-ruby,misc: Fixed clang template def error
Without this fix `error: call to function 'operator<<' that is neither
visible in the template definition nor found by argument-dependent
loopup` is thrown  when compiling HSAIL_X86 using a clang compiler (at
`base/cprintf_formats.hhi:139`).

This error is due to a "<<" operator in a template declared prior to its
definition in the code. The operator is used in
`base/cprintf_formats.hh`, included in `base/cprintf.hh`, and defined in
`mem/ruby/common/BoolVec.hh`. Therefore, for clang to compile without
error, `mem/ruby/common/BoolVec.hh` must be included before
`base/cprintf.hh` when generating the
`mem/ruby/protocol/RegionBuffer_Controller.cc` in
`mem/slicc/symbols/StateMachine.py`.

Due to the gem5 style-checker, an overly-verbose solution was required
to permit this patch to be committed to the codebase.

Change-Id: Ie0ae4053e4adc8c4e918e4a714035637925ca104
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29532
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
2020-05-28 04:48:54 +00:00
Bobby R. Bruce
5ad159ea32 python,test: Fixed boot test in python3 by removing map
In Python3 `map(lambda c: c.createThreads(), self.cpu)` does not
execute `c.createThreads()`. This has been replaced with a for-loop
which does work. Without this fix, the boot tests do not run in python3.

Change-Id: I50d6c85ec4435ee04e248ea8bc4a3b4cc17c88fa
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29456
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
2020-05-28 04:48:54 +00:00
Bobby R. Bruce
1f292ed846 scons: "no-defautled-function-deleted" flag moved to only clang8+
It has been onserved that clang does not function with the
"-Wno-defaulted-function-deleted" for versions below clang8.

Change-Id: I6e6d1476350ae2b46b4de971fe3456697b39e43c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29454
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-05-28 04:48:54 +00:00
Bobby R. Bruce
280363ec6a arch-arm,misc: Add M5_CLASS_VAR_USED to faultTick
Clang compilers returned an error that faultTick was unused. Adding
M5_CLASS_VAR_USED resolves this.

Change-Id: I97657b45997d2f1c7416b973cd9c02ae2d92b725
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29453
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-05-28 04:48:54 +00:00
Matthew Poremba
14e349c729 mem-ruby,mem-garnet: Multiple networks per RubySystem
Add support for multiple networks per RubySystem. This is done by
introducing local IDs to each network and translating from a global ID
passed around through Ruby and SLICC code. The local IDs represents the
NodeID of a MachineType in the network and are ordered the same way
that NodeIDs are ordered using MachineType_base_number. If there are
not multiple networks in a RubySystem the local and global IDs are the
same value.

This is useful in cases where multiple isolated networks are needed to
support devices with Ruby caches which do not interact with other
networks. For example, a dGPU device will have a cache hierarchy that
will not interact with the CPU cache hierachy.

Change-Id: I33a917b3a394eec84b16fbf001c3c2c44c047f66
JIRA: https://gem5.atlassian.net/browse/GEM5-445
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27927
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Bradford Beckmann <brad.beckmann@amd.com>
Maintainer: Bradford Beckmann <brad.beckmann@amd.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-05-27 17:06:31 +00:00
Richard Cooper
49ae60abe4 misc: Fix util/gem5img.py for new versions of sfdisk
Newer versions of sfdisk have changed the format of the dump output,
as well as the options for partitioning a disk.

Updated the gem5img.py script to work with the new version of sfdisk.
The script should still work with older versions of sfdisk, but this
has not been tested (see https://askubuntu.com/a/819614).

Tested on Ubuntu 18.04.2 LTS with sfdisk from util-linux 2.31.1.

Change-Id: I1197ecacabdd7caaab00327977fb9ab6eae06654
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29472
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-05-27 10:03:36 +00:00
Bobby R. Bruce
d342e03095 arch-riscv,misc: Added M5_VAR_USED to MiscRegNames
Clang compilers return an error about MiscRegNames being unused.
M5_VAR_USED fixes this.

Change-Id: I515c5d1e8837020b674de49039c0525f896b7e37
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29452
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-05-27 07:07:04 +00:00
Bobby R. Bruce
77482d59a5 scons,python: Update makeTheGPUISA to Python3
This function was causing an error to occur when trying to compile HSAIL
and GCN in a Python3 environment. It has now been upgraded to work in
both Python2 and Python3.

Change-Id: If8d6ee1e08c47d5a36182afc10cf86a8e905bda0
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29410
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-05-26 09:14:09 +00:00
Gabe Black
7cea164392 systemc: Disable some warnings generating false positives.
These false positives break the build. The error is below, and is bogus
as best I can tell. The constructor for the sc_unsigned and sc_signed
types, defined with some macro goop in sc_nbcommon.inc, have a call to
vec_copy_and_zero to copy over some data and zero the data that isn't
copied. That only happens if the source is smaller than the destination.
Then in vec_copy_and_zero, it calls vec_zero to set the last elements to
zero. Because of the check back at the constructor, only values that
exist should ever be set.

Also, in gem5, SC_MAX_NBITS is not set, so the definition of the array
it's bounds checking is declared right near where it's used and is sized
based on the variable being passed into vec_copy_and_zero.

In file included from build/ARM/systemc/ext/dt/bit/../int/../fx/sc_fxdefs.hh:52,
                 from build/ARM/systemc/ext/dt/bit/../int/sc_length_param.hh:63,
                 from build/ARM/systemc/ext/dt/bit/sc_bv_base.hh:56,
                 from build/ARM/systemc/dt/int/sc_unsigned.cc:83:
In function 'void sc_dt::vec_zero(int, int, sc_dt::sc_digit*)',
    inlined from 'void sc_dt::vec_copy_and_zero(int, sc_dt::sc_digit*, int, const sc_digit*)' at build/ARM/systemc/ext/dt/bit/../int/../fx/../int/sc_nbutils.hh:407:13,
    inlined from 'sc_dt::sc_unsigned::sc_unsigned(sc_dt::small_type, int, int, sc_dt::sc_digit*, bool)' at build/ARM/systemc/dt/int/sc_nbcommon.inc:2285:26:
build/ARM/systemc/ext/dt/bit/../int/../fx/../int/sc_nbutils.hh:379:14: error: 'void* __builtin_memset(void*, int, long unsigned int)' offset [12, 15] is out of the bounds [0, 12] [-Werror=array-bounds]
  379 |         u[i] = 0;
      |

Change-Id: Ica721178b24de56dbeabf4af7d3422dea6336a23
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29432
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-05-26 02:24:20 +00:00
Gabe Black
1e2f4a8aa6 sim: Fix a possible memory error in copyOutStatfsBuf.
When memcpy-ing, we need to be sure not to read beyond the end of the
source, or write beyond the end of the target.

Change-Id: I3cf259bedce4c6e88aef47ef5379aab198338cb7
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29404
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-05-26 00:12:10 +00:00
Gabe Black
4076a79fc1 systemc: Include eventq_impl.hh in scheduler.hh.
This ensures that we also get the inline definitions of some of the
methods defined in the EventQueue class. In certain circumstances gem5
won't link properly otherwise.

Change-Id: Ie0dfef207a165095bdfe1199cd1f690cebc4cbbf
Issue-on: https://gem5.atlassian.net/projects/GEM5/issues/GEM5-597
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29397
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-05-25 23:17:14 +00:00
Gabe Black
92711fe8e9 scons: Disable some warnings in clang.
The defaulted-function-deleted warning triggers in generated code which
would be very tricky to address.

The c99-designator refers to using an array index to specify which
element of an array is being initialized. This makes the code more
clear and is supported by both g++ and clang++. Designated initializers
for structures are being introduced in C++20, but there is no word I
could find on arrays. This warning option seems to only exist in clang
versions 10 and up, so we can only use it on those versions.

Change-Id: I8fb858e643814638c552a49336db2672be8e43c8
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29396
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-05-25 23:17:14 +00:00
Gabe Black
074e230dd2 Revert "systemc: Fix clang9 linker error"
This reverts commit 80a2636983.

Change-Id: I24c69d1a5a54ac8b8d5713314f6e91e5a6263c26
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29395
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-05-25 23:17:14 +00:00
Gabe Black
ce8a6a0cec sim: Fix the Ticked class constructor's event wrapper.
This uses a "name()" method which is not defined by the Ticked class,
and isn't a global method. This was probably originally supposed to be
the name() method of the Serializable class that Ticked inherits from,
but a while ago that was removed. It's not clear how this has been
compiling.

Instead, use the name() method of the ClockedObject which is the first
constructor argument.

Change-Id: Icfb71732c58ea9984ef7343bbaa46097a25abf28
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29406
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-05-25 21:21:33 +00:00
Gabe Black
997b74166b cpu: Fix a = that was supposed to be a == in an assert.
The KVM CPU has a _status field which is checked by an assert, but
rather than checking it with an ==, it accidentally used a =.

Change-Id: Ic1970d232786af6666c4ec2719c70f3f1509277c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29405
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-05-25 21:05:41 +00:00
Gabe Black
72ed8c6e76 sim,dev: Get rid of the global retryTime constant.
This constant isn't in normalized units, ie doesn't scale when the time
value of a Tick changes, is global, has an extremely generic name even
though it's only used by a few ethernet devices, and has an arbitrary
value.

Get rid of it, and replace it with 1ns, what it would typically be
equivalent to when using the default 1ps time scale.

Change-Id: I31d9dad438f854b4152cd53c9a7042a25d13e0a6
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29398
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-05-25 12:44:38 +00:00
Bobby R. Bruce
7ffd684334 tests,python: Upgrading testlib to function with Python2
Change-Id: I9926b1507e9069ae8564c31bdd377b2b916462a2
Issue-on: https://gem5.atlassian.net/browse/GEM5-395
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29088
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-05-24 23:29:52 +00:00
Gabe Black
1425640eda cpu: Remove the ancient do_quiesce config option.
This option has existed for a very long time, defaults to True, and is
not used in any of the checked in configs. It enables the "quiesce"
mechanism, originally just pseudo instructions, and it's not clear
why you'd ever want to turn it off.

Change-Id: I92c7e5af22157e8435c7326634857d30bb5d7254
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25143
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Reviewed-by: Matthew Poremba <matthew.poremba@amd.com>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-05-23 07:04:59 +00:00
Jason Lowe-Power
80a2636983 systemc: Fix clang9 linker error
Likely a compiler bug, but if this function is allowed to be inlined,
clang9 throws a linker error. Fix this error by making sure the function
isn't inlined.

Change-Id: I4bfade889796915e7bb4b224eafa6e72d4ec59da
Issue-on: https://gem5.atlassian.net/projects/GEM5/issues/GEM5-597
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29394
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-05-23 05:27:23 +00:00
Nadia Etemadi
729543159e arch-arm: Fixed spacing issue in ARM_MOESI_hammer
Change-Id: I5e38d1fb0b3c61ae40d26db21b8d20cc3199b391
Jira: https://gem5.atlassian.net/browse/GEM5-594
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29393
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-05-23 01:24:41 +00:00
Nadia Etemadi
ad7e297fba arch-arm: Fixed issue building ARM_MESI_Three_Level
Change-Id: I1ef200cd282e189d142a5902b6ddbd33119c4173
Jira: https://gem5.atlassian.net/browse/GEM5-594
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29352
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
2020-05-23 01:24:41 +00:00
Jason Lowe-Power
51600749cc misc: Remove GCN3 as a build target
This target currently doesn't compile, so remove it from the list of
supported ISAs for the gem5-20 release. We can add this target back
after the compilation errors have been fixed.

Change-Id: I2b121824fcfee59b62d7d24600ddd0eece884c6b
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29392
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-05-23 01:09:04 +00:00
Bobby R. Bruce
fc3112d4bd misc: Fixed HSAIL_X86 compilation errors
HSAIL_X86 fail to compile. This patch enables compilation.

Issue-on: https://gem5.atlassian.net/browse/GEM5-556

Change-Id: I663e529622ed90254eaf8be01e23991ed8271b5b
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29293
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-05-23 01:08:55 +00:00
Hoa Nguyen
e5b92bc857 tests: Update memory tests to be compatible with python3
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Change-Id: I9bb7444c62e6b29e9c91dbf30320a38718f08b8c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29353
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-05-22 09:16:29 +00:00
Hoa Nguyen
7aa1395877 python: Change m5's tick mechanism of rounding non intergral ticks
This commit changes m5's tick rounding mechanism from python's round()
to python's ceil() function.

Currently, non intergral ticks are rounded by round() function in python.
In python2, this function rounds values >= 0.5 to 1. However, in python3,
0.5 is rounded to 0. This causes the function to return 0 ticks for
non-zero second values, which doesn't make sense, and also causes
several tests to fail.

ceil() function is now used to round up the tick values. This makes more
sense as non-zero second values won't be rounded to zero in any cases.

Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Change-Id: I14c43e38e8c678f77baf13407f7eeff4b86f1014
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29372
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-05-22 09:15:59 +00:00
Polydoros Petrakis
7695a21404 mem-garnet: Remove extraneous loop in Router resetStats.
This outer loop makes no sense.

Change-Id: Ibe4b8b50c5843fba2119906f59ea1cb6c1d8c762
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29254
Reviewed-by: Srikant Bharadwaj <srikant.bharadwaj@amd.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-05-21 20:56:49 +00:00
Polydoros Petrakis
8fdad96b7c mem-garnet,mem-ruby: Properly reset garnet2.0 statistics.
Statistics for crossbar activity, and link related statistics were not getting reset when using m5_reset_stats.

Change-Id: Ib84c55200e4a86c6f9190de28498112bd43dde9d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29253
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Srikant Bharadwaj <srikant.bharadwaj@amd.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-05-21 20:56:25 +00:00