Commit Graph

1087 Commits

Author SHA1 Message Date
Ciro Santilli
5ede3d6497 sim-se: don't wake up SE futex syscalls on ARM events
Before this commit:

* SEV events were not waking neither WFE (wrong) nor futex WAIT (correct)
* locked memory events (LLSC) due to LDXR and STXR were waking up both
  WFE (correct) and futex WAIT (wrong)

This commit fixes all wrong behaviours mentioned above.

The fact that LLSC events were waking up futexes leads to deadlocks,
as shown in the test case described at:
https://gem5.atlassian.net/browse/GEM5-537
because threads woken up by SVE are not removed from the waiter list
for the futex address they are sleeping on.

A previous fix atttempt was done at:
1531b56d605d47252dc0620bb3e755b7cf84df97
in which only sleeping threads are woken up. But that is not sufficient,
because the futex sleeping thread that was being wrongly woken up on SEV
can start to sleep on a second futex.

As an example, consider the case where 4 threads are fighting over two
critical sections protected by futex1 and futex2 addresses. In this case,
one thread wakes up the other thread after it is done with the section.

Suppose the following sequence of events:

* thread1 is awake and all others are suspended on futex1

* thread1 SEV wakes thread2 from the futex1 while in the critical region 1.

  This is the wrong behaviour that this patch prevents, because
  now thread2 is still in the sleeper list for futex1

* thread1 then futex wakes tread3, then proceeds to critical region 2.

* thread3 wakes up, but because thread2 has critical region, it sleeps
  again.

* thread2 finishes its work, futex wakes thread3, and then proceeds to
  futex2

  When it reaches futex2, thread1 is still working there, so it sleeps on
  futex2.

* thread3 futex wakes thread2, because it is still wrongly on the sleeper
  list of futex1. But thread2 is in futex2 now.

  If it weren't for this mistake, it should have awaken the final thread4
  instead.

Outcome: thread4 sleeps forever, no other thread ever wakes it, because all
other threads have woken from futex1 and awoken another thread.

The problem is fixed by adding the waitingTcs unordered_set FutexMap,
which is basically an inverse map to FutexMap, which tracks (addr,
tgid) -> ThreadContext. This allows us allow to quickly check
if a given ThreadContext is waiting on a futex in any address.

Then the SEV wakeup code path
now checks if the thread is k

Change-Id: Icec5e30b041f53e5aa3b6e0d291e77bc0e865984
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29777
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Brandon Potter <Brandon.Potter@amd.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-08-10 08:52:03 +00:00
Ciro Santilli
9c9fea575a sim-se: factor out FutexMap::suspend and FutexMap::suspend_bitset
Both methods do basically the same, especially since they don't handle the
timeout which is basically the only difference between both modes of the
syscall (one uses absolute and the other relative time).

Remove the WaiterState::WaiterState(ThreadContext* _tc) constructor,
since the only calls were from FutexMap::suspend which does not use them
anymore. Instead, set the magic 0xffffffff constant as a parameter to
suspend_bitset.

Change-Id: I69d86bad31d63604657a3c71cf07e5623f0ea639
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29776
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
Maintainer: Brandon Potter <Brandon.Potter@amd.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-08-10 08:52:03 +00:00
Ciro Santilli
aa219dba7a sim-se: split futex_map.cc into header and source files
To speed up development when modifying the implementation.

Change-Id: I1b3c67c86f8faa38ed81a538521b08e256d21a5a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29775
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
Maintainer: Brandon Potter <Brandon.Potter@amd.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-08-10 08:52:03 +00:00
Ian Jiang
d60f649819 sim: Add checkpoint parameters for VMA list
Add checkpoint parameters (together with corresponding serialization
and unserialization) for VMA list of class MemState into a separate
section named 'vmalist'.

Without these VMA list parameters, a page table fault will occur when
running with --restore-simpoint-checkpoint, because of an empty VMA
list. For example:

  $ ./build/RISCV/gem5.debug --debug-flags=Exec configs/example/se.py \
      -c tests/test-progs/hello/bin/riscv/linux/hello \
      --cpu-type=NonCachingSimpleCPU --restore-simpoint-checkpoint \
      --checkpoint-dir m5out/ -r 2
  ...
  2404000: system.switch_cpus: T0 : @_int_malloc+3392    : sd a5, 8(a0) \
      : MemWrite :  D=0x000000000001ed21 A=0x862e8
  panic: Page table fault when accessing virtual address 0x862e8
  ...

Example checkpoint output:

  [system.cpu.workload.vmalist]
  size=3

  [system.cpu.workload.vmalist.Vma0]
  name=stack
  addrRangeStart=...
  addrRangeEnd=...

  [system.cpu.workload.vmalist.Vma1]
  name=heap
  addrRangeStart=...
  addrRangeEnd=...

  [system.cpu.workload.vmalist.Vma2]
  ...

Change-Id: Ib2fa7ad2c34fe667ce95bc4b10a1affcf60d9c1f
Signed-off-by: Ian Jiang <ianjiang.ict@gmail.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31875
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Alexandru Duțu <alexandru.dutu@amd.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-08-07 01:10:41 +00:00
Gabe Black
02c023eebb sim: Convert stat functions to use VPtr.
Change-Id: I1fe43ad7508b5fbbcbf6c84195858455fc8f3e85
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29402
Reviewed-by: Matthew Poremba <matthew.poremba@amd.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-08-05 23:52:17 +00:00
Gabe Black
cbefc453c4 arch,sim,misc: Add a new m5 op "sum" which just sums its inputs.
This very simple and mostly useless operation has no side effects, and
can be used to verify that arguments are making it into gem5, being
operated on, and then that a result can be returned into the simulation.

Change-Id: I29bce824078526ff77513c80365f8fad88fef128
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27557
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-07-24 03:59:49 +00:00
Gabe Black
536ea331b0 sim: Add a ProxyPtr test.
Change-Id: If71cc374030a5ef0dab62d351bc83960ff509af7
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29401
Reviewed-by: Matthew Poremba <matthew.poremba@amd.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-07-17 01:01:13 +00:00
Bobby R. Bruce
191212a6dc sim: Added M5_VAR_USED to unused cpu var
The `BaseCPU cpu` variable unused when compiling gem5.fast. This
causes the compilation to fail. Adding the M5_VAR_USED resolves this
issue.

Change-Id: I62588563e9cde384e30755742d6bc754e819d7f4
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31214
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-07-16 02:44:26 +00:00
Boris Shingarov
f7e5985e7b mem: Optionally share the backing store
This patch adds the ability for a host-OS process external to gem5
to access the backing store via POSIX shared memory.
The new param shared_backstore of the System object is the filename
of the shared memory (i.e., the first argument to shm_open()).

Change-Id: I98c948a32a15049a4515e6c02a14595fb5fe379f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/30994
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-07-08 17:42:25 +00:00
Tony Gutierrez
57a78b2115 sim: Add M5_VAR_USED to var used in dprint
Change-Id: I8f8654b8546ee8df3d4acd1ccbc5080ad38764c1
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/30896
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-07-06 15:58:16 +00:00
Gabe Black
30666c20ba sim: Retrofit the VPtr type.
Rename it to be ProxyPtr and ConstProxyPtr, merge it with the
functionality of BufferArg and TypedBufferArg, etc., as described in
this design doc.

https://docs.google.com/document/d/1BYHBJcf7dB2Z25zAZ9snbeRKfstK9uERYH_3h66w_tc/

Change-Id: I2fddde20cc0ece257685bc50bd3419a4e9a00145
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29400
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
Reviewed-by: Matthew Poremba <matthew.poremba@amd.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-07-04 17:53:54 +00:00
Matthew Poremba
675e01216d mem-ruby: Support device memories
Adds support for device memories in the system and RubySystem classes.
Devices may register memory ranges with the system class and packets
which originate from the device MasterID will update the device memory
in Ruby. In RubySystem functional access is updated to keep the packets
within the Ruby network they originated from.

Change-Id: I47850df1dc1994485d471ccd9da89e8d88eb0d20
JIRA: https://gem5.atlassian.net/browse/GEM5-470
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29653
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-07-01 14:38:11 +00:00
Giacomo Travaglini
2edcd3dbc8 sim: Fix -Werror=maybe-uninitialized in system.cc
The patch is simply initializing when to 0 before unserializing
the real value

Change-Id: I4e19eeafa9334116b440948af1943f3835803671
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/30594
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
2020-06-25 22:40:56 +00:00
Gabe Black
5b6f0b56f9 fastmodel,cpu,sim: Eliminate EndQuiesceEvent and plumbing.
Change-Id: Ifca504bc298c09cbc16ef7cded21da455fb1e118
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25146
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-06-24 01:25:42 +00:00
Gabe Black
634c2963f5 sim: Move guts of quiesce and quiesceTick from ThreadContext to System.
The functions in ThreadContext are now just convenience wrappers.

Change-Id: Ib56c4bdd27e611fb667a8056dfae37065f4034eb
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25145
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-06-24 01:25:25 +00:00
Michiel W. van Tol
3853d78594 sim: Add faulting flag to instruction tracing interface
This patch adds a faulting flag to InstRecord.
This allows tracers to identify that the traced instruction has
faulted, when ExecFaulting is enabled. It can be set with
InstRecord::setFaulting() and read with Instrecord::getFaulting().

Change-Id: I390392d59de930533eab101e96dc4d3c76500748
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/30134
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-06-22 12:15:39 +00:00
Matthew Poremba
3ca404da17 sim: Initialize stackSize and stackMin in MemState
Initialize _stackSize and _stackMin to the maximum stack size values.
The are setup in each arch's Process::initState and may be uninitialized
until then. If a stack fixup occurs before these are setup, addresses
which are not in the stack might be allocated on the stack. This
prevents that until they are initialized in Process::initState. If an
access occurs before that with these initial values, the stack fixup
will simply allocate a page of memory in the stack space. However, it
will not print the typical info messages about growing the stack during
this time.

Change-Id: I9f9316734f4bf1f773fc538922e83b867731c684
JIRA: https://gem5.atlassian.net/browse/GEM5-629
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/30394
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-06-19 14:19:36 +00:00
Gabe Black
187ba10c92 arch,cpu,sim: Eliminate the now empty kernel statistics classes.
This includes the base and ISA specific Kernel::Statistics classes, the
plumbing through ThreadContext to access them, and the switching
header file associated with them.

Change-Id: Ia511a59325b629aa9ccc0e695ddd47ff11916499
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25149
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-06-17 19:54:41 +00:00
Gabe Black
44f787ae97 arch,kern,sim: Move the stats in Kernel::Statistics to Workload.
These are the stats in the base class, not in any derived classes. Only
Alpha has an additional stats. These were not really "kernel"
statistics, they were just applicable primarily in FS. They are
potentially applicable to any simulation, but will probably not be
incremented in SE simulations.

Also this merges these stats from being per thread to being per
workload, ie operating system instance. This is probably more relevant
since exactly what thread within a workload runs which particular
instruction is not very important/predictable, but the aggregate
behavior is. If necessary, this could be adjusted in the future to
split things back out again into stats per thread while keeping them
inside the single workload object.

Change-Id: I130e11a9022bdfcadcfb02c7995871503114cd53
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25147
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-06-17 19:54:13 +00:00
Gabe Black
d3024accaf sim: Add some helpers to catch and reporting using unbound ports.
If a port is unbound, trying to call its peer will likely cause a
segfault. Rather than check if a port is bound every time you go to use
it, we can instead bind to a default peer which just throws an exception
back to the caller. The caller can catch the exception and report the
error.

This change adds a common new class to throw as the exception, and also
a small utility function which reports the error and dies.

Change-Id: Ia58a2030922c73e2fd7d139822bce38d9b0f2171
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/30295
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-06-16 02:35:41 +00:00
Gabe Black
9757529064 sim: Delete an unused member in the System class.
This was supposed to be deleted as part of the change titled:
arch,cpu,dev,sim,mem: Collect System thread elements into a subclass.

but it was left out of the checked in version somehow.

Change-Id: I0dbb0b4fa6ae29649a80d1cb883e48ad50116c31
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/30194
Maintainer: Gabe Black <gabeblack@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-06-11 03:00:33 +00:00
Gabe Black
0dfa59f0bb arch,cpu,dev,sim,mem: Collect System thread elements into a subclass.
The System class has a few different arrays of values which each
correspond to a thread of execution based on their position. This
change collects them together into a single class to make managing them
easier and less error prone. It also collects methods for manipulating
those threads as an API for that class.

This class acts as a collection point for thread based state which the
System class can look into to get at all its state. It also acts as an
interface for interacting with threads for other classes. This forces
external consumers to use the API instead of accessing the individual
arrays which improves consistency.

Change-Id: Idc4575c5a0b56fe75f5c497809ad91c22bfe26cc
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25144
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-06-09 23:37:29 +00:00
Gabe Black
5da62e6331 arch,base,cpu,kerm,sim: Build a symbol table for object files.
Instead of calling into object files after the fact and asking them to
put symbols into a target symbol table, this change makes object files
fill in a symbol table themselves at construction. Then, that table can
be retrieved and used to fill in aggregate tables, masked, moved,
and/or filtered to have only one type of symbol binding.

This simplifies the symbol management API of the object file types
significantly, and makes it easier to deal with symbol tables alongside
binaries in the FS workload classes.

Change-Id: Ic9006ca432033d72589867c93d9c5f8a1d87f73c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24787
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-06-09 23:37:29 +00:00
Gabe Black
415abb3a3c sim,mem,dev: Merge eventq_impl.hh into eventq.hh.
Having some methods (which are supposed to be inline) defined in another
file which is only included sometimes creates a lot of opportunities for
errors. They no longer need to be separate, so merge them together.

Change-Id: I5846e55f53f59b9c2081680a6441659265a765f7
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29409
Maintainer: Gabe Black <gabeblack@google.com>
Reviewed-by: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-06-04 01:54:19 +00:00
Gabe Black
d64173549b base,sim: Move DTRACE into base/debug.hh.
All other considerations aside, DTRACE probably fits best in trace.hh
where it is now, but unfortunately that creates an awkward dependence
between that file and eventq.hh and eventq_impl.hh. DTRACE only depends
on flags in the Debug namespace and a universal macro TRACING_ON, so
even though it won't be alongside the things it's most logically
associated with, it will be alongside all of its dependencies.

An alternative would be to re-implement DTRACE in eventq_impl.hh which
wouldn't be too big of a problem because it's so simple, but it's
cleaner and less error prone to still keep a single definition.

Because base/trace.hh includes base/debug.hh, any consumers expecting to
find DTRACE in base/trace.hh will still get that definition, even though
it's no longer direct.

Change-Id: I0dac83295891630686c3a8038eb54138cf40ab44
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29411
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
2020-06-03 22:32:45 +00:00
Gabe Black
89f2d5eb54 misc: Make many includes explicit.
A future change will adjust how some includes can be included
transitively. This change fixes up those files so that they include the
headers they need directly, instead of expecting to have them by
accident through other files.

Change-Id: I1f79aa11df2b46bb7018f39c964294c41db4fdac
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29407
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-06-03 19:42:46 +00:00
Bobby R. Bruce
e53de444f6 misc: Merge branch 'release-staging-v20.0.0.0' into develop 2020-05-28 01:04:16 -07:00
Gabe Black
1e2f4a8aa6 sim: Fix a possible memory error in copyOutStatfsBuf.
When memcpy-ing, we need to be sure not to read beyond the end of the
source, or write beyond the end of the target.

Change-Id: I3cf259bedce4c6e88aef47ef5379aab198338cb7
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29404
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-05-26 00:12:10 +00:00
Gabe Black
ce8a6a0cec sim: Fix the Ticked class constructor's event wrapper.
This uses a "name()" method which is not defined by the Ticked class,
and isn't a global method. This was probably originally supposed to be
the name() method of the Serializable class that Ticked inherits from,
but a while ago that was removed. It's not clear how this has been
compiling.

Instead, use the name() method of the ClockedObject which is the first
constructor argument.

Change-Id: Icfb71732c58ea9984ef7343bbaa46097a25abf28
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29406
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-05-25 21:21:33 +00:00
Gabe Black
72ed8c6e76 sim,dev: Get rid of the global retryTime constant.
This constant isn't in normalized units, ie doesn't scale when the time
value of a Tick changes, is global, has an extremely generic name even
though it's only used by a few ethernet devices, and has an arbitrary
value.

Get rid of it, and replace it with 1ns, what it would typically be
equivalent to when using the default 1ps time scale.

Change-Id: I31d9dad438f854b4152cd53c9a7042a25d13e0a6
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29398
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-05-25 12:44:38 +00:00
Ciro Santilli
66e598fa08 sim-se: implement the getcpu syscall
Change-Id: I63a1384646829b8cf68453c42aed6a7d12172787
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28590
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-05-20 07:58:05 +00:00
Gabe Black
337c586eab arch,base,cpu,sim: Statically allocate debugSymbolTable.
This singleton object is used thruoughout the simulator. There is
really no reason not to have it statically allocated, except that
whether it was allocated seems to sometimes be used as a signal that
something already put symbols in it, specifically in SE mode.

To keep that functionality for the moment, this change adds an "empty"
method to the SymbolTable class to make it easy to check if the symbol
table is empty, or if someone already populated it.

Change-Id: Ia93510082d3f9809fc504bc5803254d8c308d572
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24785
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-05-19 22:32:50 +00:00
Gabe Black
c5b2b8e19f arch,base,cpu,kern,sim: Encapsulate symbols in a class.
The SymbolTable class had been tracking symbols as two independent
pieces, a name and an address, and acted as a way to translate between
them. Symbols can be more complex than that, and so this change
encapsulates the information associated with a symbol in a new class.

As a step towards simplifying the API for reading symbols from a
binary, this change also adds a "binding" field to that class so that
global, local and weak symbols can all go in the same table and be
differentiated later as needed. That should unify the current API
which has a method for each symbol type.

While the innards of SymbolTable were being reworked, this change
also makes that class more STL like by adding iterators, and begin
and end methods. These iterate over a new vector which holds all the
symbols. The address and name keyed maps now hold indexes into that
vector instead of the other half of the symbol.

Change-Id: I8084f86fd737f697ec041bac86a635a315fd1194
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24784
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-05-19 22:32:21 +00:00
Bobby R. Bruce
65dbb3c69a misc,sim: Tagged API methods in sim/simobject.hh
Change-Id: I1d4f5b67828e3bef64d781831cec4b25d6fcb6b9
Issue-on: https://gem5.atlassian.net/browse/GEM5-172
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28407
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
2020-05-19 21:58:24 +00:00
Bobby R. Bruce
41e4bf5db7 misc,sim: Tagged API methods and variables in eventq.hh
Change-Id: I76018d4aa08f9bd42a152ec7e0222a0385d3b895
Issue-on: https://gem5.atlassian.net/browse/GEM5-172
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28388
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
2020-05-19 21:58:24 +00:00
Bobby R. Bruce
a257eef1d2 misc,sim: Tagged API methods in sim/serialize.hh
Within this some light refactoring has been carried out to avoid
accessing member variable directly and removing some unused/unneeded
ones from the codebase.

Change-Id: I458494f6466628b213816c81f6a8ce42fb91dc3f
Issue-on: https://gem5.atlassian.net/browse/GEM5-172
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27989
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-05-19 21:58:24 +00:00
Bobby R. Bruce
2a7c1decf1 misc: Tagged API methods in sim/drain.hh
Change-Id: Id584d0be027048064d5f650ae0f2ea5a7f075a47
Issue-on: https://gem5.atlassian.net/browse/GEM5-172
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27988
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-05-19 21:58:24 +00:00
Bobby R. Bruce
eaacf1b6b1 misc,sim: Fixed std::array bracket compiler error
For versions of Clang before 6.0, Clang returns an error if and
std::array initialization is not encompassed in two sets of
encompassing braces. This is a known compiler bug:
https://bugs.llvm.org/show_bug.cgi?id=21629.

As we support Clang 3.9 onwards, we are required to include these
redundant braces to ensure compilation. They do not produce any
ill-effects when using later clang compilers or with any GCC compiler
gem5 presently supports.

Change-Id: Ia512a9b9f583b1cfa28f9fc4c24f6e202e46b4cb
Issue-on: https://gem5.atlassian.net/browse/GEM5-563
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29294
Reviewed-by: Pouya Fotouhi <pfotouhi@ucdavis.edu>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-05-19 08:05:39 +00:00
Matthew Poremba
fae00cb175 sim: Fixes for mremap
Remapping memory was trying to map old pages to the same new page and
calling MemState mapRegion unnecessarily. Properly increment the new
page address and remove the redundant mapRegion as remapRegion covers
its functionality.

JIRA: https://gem5.atlassian.net/browse/GEM5-475
Change-Id: Ie360755cfe488b09cbd87cd0ce525b11ac446b51
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28948
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-05-14 00:29:17 +00:00
Mark Hildebrand
9957d71bf4 misc: Get gem5 to build with Clang 8
Added missing overrides:
- src/mem/token_port.hh
- src/sim/power/mathexpr_powermodel.hh

Remove Unused static constants:
- src/arch/x86/process.cc

Related Issue: https://gem5.atlassian.net/projects/GEM5/issues/GEM5-534

Change-Id: Icc725e2522dcee919e299f4ea7a9f1773f5dfa4d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28947
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-05-13 01:55:35 +00:00
Gabe Black
1e4a6b32b4 arm,x86,sim: Use the new return value suppression in GuestABI.
This gets rid of some dummy Return structure definitions. Also augment
the PseudoInst::pseudoInst dispatch function so it can store or not
store results, depending on what's needed at each call sight.

Change-Id: If4a53bc0a27e5214a26ef1a100c99948ca95418d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28289
Reviewed-by: Gabe Black <gabeblack@google.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-05-12 16:32:09 +00:00
Gabe Black
6554a9f181 sim: Convert GuestABI example signatures to comments.
In the base Result and Argument templates, there were private static
functions which weren't meant to be used, but which would act as
documentation for what those functions should look like. They were
marked as private to prevent them from being accidentally used and
causing confusing, hard to debug errors.

Unfortunately, that also meant that those functions exist, and
apparently cause inconsistent problems with SFINAE. I assume if the
functions don't exist at all, then SFINAE will work properly. When
they're private, that seems to cause a substitution failure which
actually is an error which makes the build fail.

Change-Id: I326e9e1d05eafe1b00732ae10264354b07426e74
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28308
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-05-12 16:32:09 +00:00
Nils Asmussen
97d45c5dc7 base,sim: allow m5writeFile with stdout/stderr.
If m5writeFile opens stdout/stderr, no file is registered in
OutputDirectory and thus we don't want to search for it on close.

In order to write multiple times to stdout/stderr in a reasonable way,
we also want to prevent seeking. Thus, don't seek if the offset is 0, in
which case this would be a noop anyway (we just opened the file without
append).

Finally, it is helpful for debugging if the stream is flushed on every
write.

Change-Id: I102f82dcd2c63420b6f3fe55d67f03c62349e69d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28727
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-05-08 17:36:21 +00:00
Nikos Nikoleris
e2e25f8139 sim: Inheritance fixes in varargs
Change-Id: I3c6027223893363df098d1990a4ad3d07c2ff5ff
Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28250
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-04-30 09:14:42 +00:00
Nikos Nikoleris
0830fcf97d sim: Fix mismatch between #ifndef and #define in varargs.hh
Change-Id: I558b6c3c69a5003a77cc95b414e620715c3dbbae
Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28169
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-04-30 09:14:42 +00:00
Nikos Nikoleris
bde88913a8 arch-arm, mem-ruby, sim: Add missing overrides
Change-Id: I5ab18960bd61953e68777746426adb657818f825
Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28168
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-04-30 09:14:42 +00:00
Gabe Black
41c88839a9 sim: Add an option to suppress the return value in invokeSimcall.
Sometimes when using the GuestABI mechanism, gem5 wants to know that a
function was called and with what arguments to do its own processing,
but doesn't want to return its own value since it will still let the
simulated system execute its own function. There are also situations
where gem5 wants to return a value, but not through the normal
mechanism. That happens when, for instance, a gem5 op is triggered by a
memory access, and that access is what should return the value, not a
particular fixed register.

This option is a template parameter rather than a function argument so
that if it's not going to be used, no "Return" type needs to be defined
since it's not present at all in the chain of functions invokeSimcall
expands to.

This will also make it easier to reuse generic ABIs in those situations
without having to make custom wrappers.

Change-Id: I969e78495c8f4e73f4de1a3dfb4d74c9b30f5af5
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28288
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-04-30 08:47:33 +00:00
Anouk Van Laer
cc2f48ccfc sim-power: Addition of PowerDomains
PowerDomains group multiple objects together to regulate their power
state. There are 2 types of objects in a PowerDomain: leaders and
followers. The power state of a PowerDomain is the most performant
power state of any of the leaders. The power state of the followers is
determined by the power state of the PowerDomain they belong to: they
need to be in a power state which is more or equally performant to the
power state of the PowerDomain.

Leaders can be ClockedObjects or other PowerDomains. Followers can
only be ClockedObjects. PowerDomains can be be nested but a
PowerDomain can only be a leader of another PowerDomain, NOT a
follower. PowerDomains are not present in the hierarchy by default,
the user needs to create and configure them in the configuration file.

The user can add an hierachy by setting the led_by parameter. gem5
will then create leaders and followers for each domain and calculate
the allowed power states for the domain.

Objects in a PowerDomain need to have at least the ON state in the
possible_states.

An example of a powerDomain config is:

pd = PowerDomain()
cpu0 = BaseCPU()
cpu1 = BaseCPU()
shared_cache = BaseCache()
cache.power_state.led_by = pd
pd.led_by = [cpu0, cpu1]

This will create a PowerDomain, where the CPUs determine their own
power states and the shared cache (via the PowerDomain) follows those
power states (when possible).

Change-Id: I4c4cd01f06d45476c6e0fb2afeb778613733e2ff
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Sascha Bischoff <sascha.bischoff@arm.com>
Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28051
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-04-29 21:03:31 +00:00
Anouk Van Laer
4b2f2b5ced sim-power: Specify the states a PowerState object can be in
This commit adds the concept of possible power states to the
PowerState SimObject. This is a list of the power states a specific
object can be in. Before transitioning to a power state, a PowerState
object will first check if the requested power states is actually an
allowed state. The user can restricted the power states a
ClockedObject can go to during configuration. In addition, this change
sets the power states, a CPU can be in.

Change-Id: Ida414a87554a14f09767a272b54b5d19bfc8e911
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28050
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-04-29 21:03:31 +00:00
Anouk Van Laer
818961969a sim-power: Creation of PowerState class
This commit does not make any functional changes but just rearranges
the existing code with regard to the power states. Previously, all
code regarding power states was in the ClockedObjects. However, it
seems more logical and cleaner to move this code into a separate
class, called PowerState. The PowerState is a now SimObject. Every
ClockedObject has a PowerState but this patch also allows for objects
with PowerState which are not ClockedObjects.

Change-Id: Id2db86dc14f140dc9d0912a8a7de237b9df9120d
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Sascha Bischoff <sascha.bischoff@arm.com>
Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28049
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-04-29 21:03:31 +00:00