arch-arm, mem-ruby, sim: Add missing overrides

Change-Id: I5ab18960bd61953e68777746426adb657818f825
Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28168
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

src/arch/arm/isa.hh

@@ -726,14 +726,14 @@ namespace ArmISA
                                            unsigned eCount);
 
         void
-        serialize(CheckpointOut &cp) const
+        serialize(CheckpointOut &cp) const override
         {
             DPRINTF(Checkpoint, "Serializing Arm Misc Registers\n");
             SERIALIZE_ARRAY(miscRegs, NUM_PHYS_MISCREGS);
         }
 
         void
-        unserialize(CheckpointIn &cp)
+        unserialize(CheckpointIn &cp) override
         {
             DPRINTF(Checkpoint, "Unserializing Arm Misc Registers\n");
             UNSERIALIZE_ARRAY(miscRegs, NUM_PHYS_MISCREGS);

src/mem/ruby/system/GPUCoalescer.hh

@@ -102,9 +102,9 @@ class GPUCoalescer : public RubyPort
     void wakeup(); // Used only for deadlock detection
 
     void printProgress(std::ostream& out) const;
-    void resetStats();
+    void resetStats() override;
     void collateStats();
-    void regStats();
+    void regStats() override;
 
     void writeCallback(Addr address, DataBlock& data);
 
@@ -157,18 +157,18 @@ class GPUCoalescer : public RubyPort
     void recordCPWriteCallBack(MachineID myMachID, MachineID senderMachID);
 
     // Alternate implementations in VIPER Coalescer
-    virtual RequestStatus makeRequest(PacketPtr pkt);
+    virtual RequestStatus makeRequest(PacketPtr pkt) override;
 
-    int outstandingCount() const { return m_outstanding_count; }
+    int outstandingCount() const override { return m_outstanding_count; }
 
     bool
-    isDeadlockEventScheduled() const
+    isDeadlockEventScheduled() const override
     {
         return deadlockCheckEvent.scheduled();
     }
 
     void
-    descheduleDeadlockEvent()
+    descheduleDeadlockEvent() override
     {
         deschedule(deadlockCheckEvent);
     }

src/mem/ruby/system/Sequencer.hh

@@ -86,9 +86,9 @@ class Sequencer : public RubyPort
 
     // Public Methods
     void wakeup(); // Used only for deadlock detection
-    void resetStats();
+    void resetStats() override;
     void collateStats();
-    void regStats();
+    void regStats() override;
 
     void writeCallback(Addr address,
                        DataBlock& data,
@@ -106,14 +106,14 @@ class Sequencer : public RubyPort
                       const Cycles forwardRequestTime = Cycles(0),
                       const Cycles firstResponseTime = Cycles(0));
 
-    RequestStatus makeRequest(PacketPtr pkt);
+    RequestStatus makeRequest(PacketPtr pkt) override;
     bool empty() const;
-    int outstandingCount() const { return m_outstanding_count; }
+    int outstandingCount() const override { return m_outstanding_count; }
 
-    bool isDeadlockEventScheduled() const
+    bool isDeadlockEventScheduled() const override
     { return deadlockCheckEvent.scheduled(); }
 
-    void descheduleDeadlockEvent()
+    void descheduleDeadlockEvent() override
     { deschedule(deadlockCheckEvent); }
 
     void print(std::ostream& out) const;

src/sim/kernel_workload.hh

@@ -98,7 +98,7 @@ class KernelWorkload : public Workload
     }
 
     bool
-    insertSymbol(Addr address, const std::string &symbol)
+    insertSymbol(Addr address, const std::string &symbol) override
     {
         return kernelSymtab->insert(address, symbol);
     }