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Author SHA1 Message Date
Bobby R. Bruce
28a871b037 scons: Re-add -Werror for gem5 develop branch 
This is removed from the stable branch to avoid build errors but should
included on the develop branch to aid developers.

This reverts commit 7dd61c8659.

Change-Id: I1fe249ce87aa8d70c1f092fc7db1554e6aee7355
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/67052
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
 2023-01-03 22:08:08 +00:00
Bobby Bruce
1d038cc77d Merge "misc: Merge branch stable into develop branch" into develop 2023-01-03 22:08:08 +00:00
Vishnu Ramadas
66d4a15820 gpu-compute,mem-ruby: Add support for GPU cache bypassing 
The GPU cache models do not support cache bypassing when the GLC or SLC
AMDGPU instruction modifiers are used in a load or store. This commit
adds cache bypass support by introducing new transitions in the
coherence protocol used by the GPU memory system. Now, instructions with
the GLC bit set will not cache in the L1 and instructions with SLC bit
set will not cache in L1 or L2.

Change-Id: Id29a47b0fa7e16a21a7718949db802f85e9897c3
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/66991
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
 2023-01-03 21:19:24 +00:00
Rocky Tatiefo
5db889572a base: Remove unused output.hh dependency from trace.cc 
Change-Id: Ie80ad5f3fb9fc7ee1e35f0624317e0e58cbf152d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/67011
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2022-12-31 09:50:15 +00:00
Roger Chang
083566d0c8 arch-riscv: add RV32 ADFIMU_Zfh instruction tests 
1. Add rv32 binary files into asmtests
2. Support Riscv CPU with 32 bits register to  simple_binary_run.py

Change-Id: I5cc4c2eeb7654a4acc2d167eb76d8b6522e65dd9
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/65533
Reviewed-by: Yu-hsin Wang <yuhsingw@google.com>
Reviewed-by: Bobby Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
 2022-12-30 22:56:01 +00:00
Bobby R. Bruce
218b3925be misc: Merge branch stable into develop branch 
This ensures both branches are in-sync and have not diverged.

Change-Id: Ib487d8596037017b9ec03d7e8a76229373c153db
 2022-12-30 20:43:00 +00:00
Bobby R. Bruce
5fa484e2e0 misc: Merge the v22.1 release staging into stable 2022-12-30 19:53:52 +00:00
Bobby R. Bruce
61aabd516e misc: Update RELEASE-NOTES.md for v22.1.0.0 
Change-Id: I28753f24742ca156e19ac2af4fb302f9de20e852
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/66391
Reviewed-by: Bobby Bruce <bbruce@ucdavis.edu>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Matthew Poremba <matthew.poremba@amd.com>
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
 2022-12-30 19:30:06 +00:00
Giacomo Travaglini
fcde59b245 util: ext/systemc is importing env Environment instead of main 
This got changed by [1]
With this patch we export env instead of main. There is no risk of
ext/systemc polluting the environment as its SConscript is cloning env
to the systemc variable anyway, so this double copy was redundant anyway

[1]: https://gem5-review.googlesource.com/c/public/gem5/+/56750

Change-Id: Ib6648e9b38416cac0bc7f06d90a337f32bdca6ca
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/66854
Maintainer: Daniel Carvalho <odanrc@yahoo.com.br>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
 2022-12-27 12:11:05 +00:00
Giacomo Travaglini
55fb8bf40e util: Update util-tlm to require C++17 
It's the version we currently use to compile gem5

Change-Id: I5d2d26e5ba32191d65a4a5ae58d29a16970d062d
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/66853
Maintainer: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Tested-by: kokoro <noreply+kokoro@google.com>
 2022-12-27 12:11:05 +00:00
Giacomo Travaglini
25b4defa6a util: Fix missing include of sim/core.hh in util-tlm 
Change-Id: I6dbf71dac903a660369bf8b33ae0c88d28d07457
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/66852
Reviewed-by: Matthias Jung <jungma@eit.uni-kl.de>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Daniel Carvalho <odanrc@yahoo.com.br>
 2022-12-27 12:11:05 +00:00
Giacomo Travaglini
8d117aad71 util: cxxConfigInit has been removed by gem5 
This was merged in [1]

[1]: https://gem5-review.googlesource.com/c/public/gem5/+/49455

Change-Id: Iba558dd01d5c8fbc05e4d3a106a3e3ff6b696333
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/66851
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Daniel Carvalho <odanrc@yahoo.com.br>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Matthias Jung <jungma@eit.uni-kl.de>
 2022-12-27 11:55:57 +00:00
Roger Chang
9cd61d000a arch-riscv: Correct the IllegalInstFault messege of instruction 
c.addi4spn

In Riscv Manual Volumn I: Unpriviledged ISA section 18.5, c.addi4spn
will not working if imm == 0, not machInst == 0. It is changed in the
https://gem5-review.git.corp.google.com/c/public/gem5/+/66732, and here is the additional patch to the CL.

Change-Id: I2a3c9660dc43f1399f68e03c4f59207f869807a0
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/66931
Reviewed-by: Yu-hsin Wang <yuhsingw@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2022-12-23 23:01:16 +00:00
Roger Chang
9ce8c9b81c arch-riscv: Refactor template JumpConstructor 
Add COPCODE == 4 condition to ensure the available instruction is either c_jr or c_jalr and the flag IsReturn should set for instruction c_jalr if RC1 == t0

Change-Id: I1b39a6c1dc52c8035f16cc64a1b4c494b14879c0
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/66811
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Yu-hsin Wang <yuhsingw@google.com>
 2022-12-23 00:28:11 +00:00
Roger Chang
6797c78942 arch-riscv: Refactor compressed instructions 
1. C.JAL should use CJOp format to generate code
2. Use sext function to handle MSB for immediate
3. Add IsCall flags to c.jal, c.jalr
4. Use JumpConstructor to CJOp format

Change-Id: Id01c0d7cc1a3e17776890268879c568fc9996bc5
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/66732
Reviewed-by: Yu-hsin Wang <yuhsingw@google.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2022-12-23 00:28:11 +00:00
Giacomo Travaglini
5447d55e39 dev: Fix -Wunused-variable in structured binding 
Change-Id: Ia244767dd9d1dd7b72c320fb78e48f206694f5a2
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/66891
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Yu-hsin Wang <yuhsingw@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
 2022-12-22 08:07:51 +00:00
Daniel R. Carvalho
7fb2fda841 base: Fix signature of SatCounter::saturate() 
The variants that use more than 8 bits were broken,
since the size of the difference in those cases
could be larger than 8 bits, and the return value
was only 8-bits long.

Change-Id: I8b75be48f924cc33ebf5e5aeff6d4045fac66bcc
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/66791
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2022-12-19 01:58:31 +00:00
Bobby R. Bruce
06f18242fe tests: Fix compiler-tests.sh build args passing 
Reverts this fix:
https://gem5-review.googlesource.com/c/public/gem5/+/66631

While this did fix the case where no build args were passed, it broke
the case where build args were passed.

This fix ensures the script works in both cases.

Change-Id: I6cc8cc0c2a10c801d4a59e54b070383ac8ee93ae
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/66772
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2022-12-17 20:50:13 +00:00
Melissa Jost
55d8219717 tests: Remove get_runtime_isa() from parsec_disk_run.py 
This change removes the call to get_runtime_isa(), as it has
been deprecated.

Change-Id: Ie1b0b5fb456fd8ed504a531841fe4ea8e211502c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/66611
Maintainer: Boris Shingarov <shingarov@labware.com>
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
Reviewed-by: Boris Shingarov <shingarov@labware.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2022-12-17 11:37:13 +00:00
Melissa Jost
4cae2ae4ad tests: Remove get_runtime_isa() from parsec_disk_run.py 
This change removes the call to get_runtime_isa(), as it has
been deprecated.

Change-Id: Ie1b0b5fb456fd8ed504a531841fe4ea8e211502c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/66612
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
 2022-12-17 11:36:59 +00:00
Matthew Poremba
af2cecf59e gpu-compute: Fix ABI init for DispatchId 
DispatchId should allocate two SGPRs instead of one. Allocating one was
causing all subsequent SGPR index values to be off by one, leading to
bad addresses for things like flat scratch and private segment. This
field is not used very often so it was not impacting most applications.

Change-Id: I17744e2d099fbc0447f400211ba7f8a42675ea06
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/66711
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2022-12-16 18:16:18 +00:00
Gabe Black
fbd0722de4 fastmodel,dev: Replace the reset port with a Signal*Port<bool>. 
The ResetRequestPort and ResetResponsePort have a few problems:

1. A reset signal should happen during the time a reset is asserted,
or in other words the device should stay in reset and not doing
anything while reset is asserted. It should not immediately restart
execution while the reset is still held.

2. These names are misleading, since there is no response. These names
are inherited from other port types where there is an actual response.

There is a new generic SignalSourcePort and SignalSinkPort set of port
classes which are templated on the type of signal they propogate, and
which can be used in place of reset ports in c++. These ports can
still have a specialized role which will ensure that only reset ports
are connected to each other for a form of type checking, although
the underlying c++ instances are more interoperable than that.

Change-Id: Id98bef901ab61ac5b200dbbe49439bb2d2e6c57f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/66675
Maintainer: Gabe Black <gabeblack@google.com>
Reviewed-by: Yu-hsin Wang <yuhsingw@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2022-12-16 07:19:05 +00:00
Gabe Black
0aaaa6b4ae fastmodel: Change the Signal proxies to use Signal*Port<bool>. 
Change-Id: Ia1aa32d5ea50ff4cc47d1d72a9c25dabd6c30de9
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/66674
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Yu-hsin Wang <yuhsingw@google.com>
 2022-12-16 07:19:05 +00:00
Gabe Black
89d5bfca7c fastmodel,dev: Rework the Int*Pin classes with Signal*Port. 
These are largely compatibility wrappers around the Signal*Port
classes. The python versions of these types enforce more specific
compatibility, but on the c++ side the Signal*Port<bool> classes can
be used directly instead.

Change-Id: I1325074d0ed1c8fc6dfece5ac1ee33872cc4f5e3
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/66673
Maintainer: Gabe Black <gabeblack@google.com>
Reviewed-by: Yu-hsin Wang <yuhsingw@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2022-12-16 07:19:05 +00:00
Gabe Black
7a21ecf15c dev: Implement a "Signal" port which has a templated State type. 
This port type transmits a value of the templated State type. When the
value changes, the sink port will call the registered callback with
the new value.

Change-Id: I72eaf74658a2c63bece95e48c1a72694874eaad8
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/66672
Maintainer: Gabe Black <gabeblack@google.com>
Reviewed-by: Jui-min Lee <fcrh@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Yu-hsin Wang <yuhsingw@google.com>
 2022-12-16 07:19:05 +00:00
Gabe Black
8b1688da34 dev: Introduce a reset() method on RegisterBank and Register classes. 
This will make it much easier to implement reset behaviors on devices
which have RegisterBanks in them.

Change-Id: I73fe9874fcb69feed33611a320dcca85c0de2d0e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/66671
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Reviewed-by: Yu-hsin Wang <yuhsingw@google.com>
Reviewed-by: Jui-min Lee <fcrh@google.com>
 2022-12-16 07:19:05 +00:00
Emin Gadzhiev
f96513fd04 sim,sim-se: Fix restoring of VMAs of memory-mapped files 
This patch fixes a problem that occurs when restoring from
a checkpoint where Mapped File Buffers are not restored. This
causes errors and unexpected behavior during further execution.
Since the checkpoint already has the size of the
area (address range) and the file name, only the offset is
missing to restore the Mapped File Buffer. Having the offset
value, it's possible to open those files for which an offset is
specified and create a VMA with a Mapped File Buffer.

Change-Id: Ib9dfa174cda6348b966b892184c36daeaba80e81
Signed-off-by: Emin Gadzhiev <e.gadzhiev.mhk@gmail.com>
Issue-On: https://gem5.atlassian.net/browse/GEM5-1302
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/66311
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
 2022-12-15 21:38:01 +00:00
Roger Chang
f7d0808a5c arch-riscv: Fork Zba, Zbb, Zbc, Zbs instructions into rv32 / rv64 
The following instructions will be supported for both rv32 and rv64

Zba extensions:
SLLI.UW
SH1ADD
SH2ADD
SH3ADD
ADD.UW
SH1ADD.UW
SH2ADD.UW
SH3ADD.UW

Zbb extensions:
CLZ
CTZ
CPOP
SEXT.B
SEXT.H
ORC.B
RORI
REV8
CLZW
CTZW
CPOPW
RORIW
ROL
MIN
XNOR
MINU
ROR
MAX
ORN
MAXU
ANDN
ROLW
ZEXT.H
RORW

Zbc extensions:
CLMUL
CLMULR
CLMULH

Zbs extensions:
BSETI
BCLRI
BINVI
BEXTI
BSET
BCLR
BINV
BEXT

Change-Id: I3f489a3a1bab8799e2d95218740e495313b9961d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/66211
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2022-12-14 01:53:08 +00:00
Bobby R. Bruce
2ed4323899 tests: Fix compiler-tests.sh for no build args passed case 
When a user ran "tests/compiler-tests.sh" without passing any arguments,
the compiler tests would fail with:

```
scons: Reading SConscript files ...
Error: No existing build directory and no variant for /gem5
```

However, when passed with arguments, such as:

```
./tests/compiler-tests.sh -j6
```

the tests passed.

The fix for this is to merge the "$build_out" and "$build_args" into a
single string when executing the docker. I do not know exactly why this
works, but it does fix the error.

Change-Id: Ibcd316668b60fb7706f0ee05ab6dadf56228319d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/66631
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2022-12-13 16:36:40 +00:00
Roger Chang
ad107116a1 arch-riscv: Support RV32 to remote gdb 
support rv32 cpu, fpu, csr registers to remote gdb.

Change-Id: Ib821a35ff2e95f6f47569b1f4cb35cd98fcca77d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/66131
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Reviewed-by: Gabe Black <gabeblack@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
 2022-12-13 05:21:27 +00:00
Roger Chang
dd04e70445 arch-riscv: Implement rv32 zicsr extension 
1. Add misc register mstatush, cycleh, timeh, instreth,
   hpmcounter03...hpmcounter31, pmpcfg1, pmpcfg3
2. Implement handling RV32 only registers
3. Implement methods of set time CSR

Change-Id: I5c55c18a0da91977d6e23da24ea3cbcba9f0509b
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/65733
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2022-12-13 05:21:27 +00:00
Roger Chang
fa34ebc853 arch-riscv: Fork ACDFIMU_Zfh instructions into rv32/rv64 
1. Add rvSelect for rv32 and rv64.
2. Add rvZext and rvSext for rv32 handle sign extension
3. Fork the following instructions into rv32/rv64 version

A extensions:
SC.W
LR.D
SC.D
AMOADD.D
AMOSWAP.D
AMOXOR.D
AMOOR.D
AMOAND.D
AMOMIN.D
AMOMAX.D
AMOMINU.D
AMOMAXU.D

C extensions:
C.ADDI4SPN
C.FLD
C.LW
C.FLW
C.LD
C.FSD
C.SW
C.FSW
C.SD
C.ADDI
C.JAL
C.ADDIW
C.ADDI16SP
C.SRLI
C.SRAI
C.ANDI
C.SUB
C.XOR
C.OR
C.AND
C.SUBW
C.ADDW
C.J
C.BEQZ
C.BNEZ
C.SLLI
C.FLDSP
C.LWSP
C.FLWSP
C.LDSP
C.JR
C.MV
C.EBREAK
C.JALR
C.ADD
C.FSDSP
C.SWSP
C.FSWSP
C.SDSPF

D extensions:
FCVT.L.D
FCVT.LU.D
FCVT.D.L
FCVT.D.LU
FMV.X.D
FCLASS.D
FMV.D.X

F extensions:
FSW
FCVT.L.S
FCVT.LU.S
FCVT.S.W
FCVT.S.WU
FCVT.S.L
FCVT.S.LU
FMV.X.W
FCLASS.S
FMV.W.X

I extensions:
LD
LWU
SLLI
ADDI
SLTI
SLTIU
XORI
SRLI
SRAI
ORI
ANDI
AUIPC
ADDIW
SLLIW
SRLIW
SRAIW
SD
ADD
SUB
SLL
SLT
SLTU
XOR
SRL
SRA
OR
AND
LUI
BEQ
BNE
BLT
BGE
BLTU
BGEU
JALR
JAL
ADDW
SUBW
SLLW
SRLW
SRAW

M extensions:
MUL
MULH
MULHSU
MULHU
DIV
DIVU
REM
REMU
MULW
DIVW
DIVUW
REMW
REMUW

ZFH extensions:
FSH
FCVT.L.H
FCVT.LU.H
FCVT.H.L
FCVT.H.LU

Change-Id: I8604324eadb700591db028aa3b013b060ba37de5
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/65111
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2022-12-13 05:21:27 +00:00
Bobby R. Bruce
d65173d596 tests: Move replacement policy tests to long/Nightly 
These tests require the compilation of NULL with the MI_Example cache
coherence protocol. This is a large overhead for these tests. They are
therefore better off being run nightly rather than as a
pre-commit/kokoro/quick test.

Change-Id: I87b25afa313ecca65c738e3a8692a9bf72b06620
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/66615
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
 2022-12-13 00:20:49 +00:00
Yu-hsin Wang
ce03482a39 mem: Implement and use the recvMemBackdoorReq func. 
In the previous change, we miss some model supporting atomic backdoor.
We should also implement the recvMemBackdoorReq to them.

Change-Id: I4706d215aa4a5d18fe4306b2387f9c8750cb4b4a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/66551
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2022-12-13 00:20:13 +00:00
Bobby R. Bruce
91f8f2b276 tests: Add missing _pre_instantiate() 
As of this change:
https://gem5-review.googlesource.com/c/public/gem5/+/65051, the
`_pre_instantiate` function must be called prior to `m5.instantiate`
when using the stdlib without the Simulator module. The
"test/gem5/replacement-policies/run_replacement_policy_test.py" lacked
this and was causing errors when running replacement policy tests.

In addition we also fix the incorrect type of size in`createArtifact'.
This was causing problems with the Kokoro build system.
The typing here was `int` but had a default value of `None`. The correct
type is therefore `Optional[int]`.

Change-Id: Ibaf63151196b15f68e643fa5c1b290439d6618c8
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/66371
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby Bruce <bbruce@ucdavis.edu>
(cherry picked from commit a3fd9631cc)
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/66613
 2022-12-13 00:20:13 +00:00
Bobby R. Bruce
81cb7c05b4 misc: Update .mailmap 
This commit updates the mailmap since the initial commit in mid-July
2020: https://gem5-review.googlesource.com/c/public/gem5/+/29672.

`sort -u` has been run on this file so some previous entries have been
moved.

Change-Id: I46df1e9675f6f7057b680ca2abbcebdffd50462a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/66531
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
 2022-12-08 18:11:17 +00:00
Bobby R. Bruce
1b2252cbc0 misc: Update .mailmap 
This commit updates the mailmap since the initial commit in mid-July
2020: https://gem5-review.googlesource.com/c/public/gem5/+/29672.

`sort -u` has been run on this file so some previous entries have been
moved.

Change-Id: I46df1e9675f6f7057b680ca2abbcebdffd50462a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/66517
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
 2022-12-08 00:26:01 +00:00
Jarvis
bd31956060 tests: Add replacement policy tests 
Add tests to test the correctness of replacement policies using
TrafficGen.
Enable debug-flags to print the hit and miss messages so that you
can compare the results with the comments in the tests. Even though
the tests are targeting specific replacement policies, they can be
reused to test all replacement policies.

Change-Id: I3a8013fbcb19adae25b0818ac9e4b0be60be0689
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/60389
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
 2022-12-07 23:18:23 +00:00
Bobby R. Bruce
e81aa1cd86 configs: Alter x86-npb-benchmarks.py to exit after WORKEND 
While the config script will still function without exiting the SimLoop
after the "WORKEND" exit event, there's no need for the simulation to
continue beyond this point.

Change-Id: I60691215e9516fa1eeb8b8502f2bc5a09de2969b
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/66513
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
 2022-12-07 18:56:09 +00:00
Bobby R. Bruce
a23641e01f configs: Fix x86-gapbs-benchmarks.py example 
With https://gem5-review.googlesource.com/c/public/gem5/+/64791 we
updated the configs/example/gem5_library to utilize the `m5.simulate`
module. The GAPBS benchmark example uses the "WORKBEGIN" and "WORKEND"
exit events to specify the ROI. The patch incorrectly assumed an "EXIT"
exit event were used.

As such, the
"test-gem5-library-example-x86-gapbs-benchmarks-ALL-x86_64-opt-MESI_Two_Level"
test was not properly running, causing the Nightly test to fail:
https://jenkins.gem5.org/job/nightly/444. This patch fixes this error.

Change-Id: I207fe3563c8d9c59bcb79428fe62d2d2bbccd013
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/66512
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
 2022-12-07 18:56:09 +00:00
Bobby R. Bruce
c765cfb64b configs: Alter x86-npb-benchmarks.py to exit after WORKEND 
While the config script will still function without exiting the SimLoop
after the "WORKEND" exit event, there's no need for the simulation to
continue beyond this point.

Change-Id: I60691215e9516fa1eeb8b8502f2bc5a09de2969b
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/66515
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
Reviewed-by: Bobby Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
 2022-12-07 18:56:01 +00:00
Bobby R. Bruce
5d475506d7 configs: Fix x86-gapbs-benchmarks.py example 
With https://gem5-review.googlesource.com/c/public/gem5/+/64791 we
updated the configs/example/gem5_library to utilize the `m5.simulate`
module. The GAPBS benchmark example uses the "WORKBEGIN" and "WORKEND"
exit events to specify the ROI. The patch incorrectly assumed an "EXIT"
exit event were used.

As such, the
"test-gem5-library-example-x86-gapbs-benchmarks-ALL-x86_64-opt-MESI_Two_Level"
test was not properly running, causing the Nightly test to fail:
https://jenkins.gem5.org/job/nightly/444. This patch fixes this error.

Change-Id: I207fe3563c8d9c59bcb79428fe62d2d2bbccd013
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/66514
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
 2022-12-07 18:56:01 +00:00
Gabe Black
00a893ad4e systemc: Enable DMI in the non-blocking/timing mode bridge. 
Change-Id: Ia618081e2dbf8b49f62480ac5dc29f87100cd4f1
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/65754
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Gabe Black <gabeblack@google.com>
 2022-12-07 12:23:35 +00:00
Yu-hsin Wang
985d9c641f systemc: replace the deprecated std::iterator 
std::iterator is deprecated in c++17. We can just declare the
required types for iterator traits directly without the helper.

Change-Id: I789e2c2b13e56cc391527686109df8b779474d09
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/66351
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2022-12-07 02:24:51 +00:00
Bobby R. Bruce
1e73beb620 python: Remove 'scheduleTickExit' in favor of 'exitSimLoop' 
The commit https://gem5-review.googlesource.com/c/public/gem5/+/66231
added an API to m5 for scheduling to-tick exit events. This added the
function `schedule_tick_exit`. It was later pointed out that this
`schedule_tick_exit` event is redundant given the existance of
`exitSimLoop`. This patch therefore removes `schedule_tick_exit` in
favor of `exitSimLoop`.

Change-Id: Ibecf00b98256a5da2868427d766bdc93f03c3f97
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/66511
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
 2022-12-06 22:41:58 +00:00
Bobby R. Bruce
ae20719576 python: Remove 'scheduleTickExit' in favor of 'exitSimLoop' 
The commit https://gem5-review.googlesource.com/c/public/gem5/+/66231
added an API to m5 for scheduling to-tick exit events. This added the
function `schedule_tick_exit`. It was later pointed out that this
`schedule_tick_exit` event is redundant given the existance of
`exitSimLoop`. This patch therefore removes `schedule_tick_exit` in
favor of `exitSimLoop`.

Change-Id: Ibecf00b98256a5da2868427d766bdc93f03c3f97
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/66451
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
 2022-12-06 18:04:46 +00:00
Gabe Black
9d1cc1bcc9 dev: Add an offset checking mechanism to RegisterBank. 
When adding a long list of registers, it can be easy to miss one which
will offset all the registers after it. It can be hard to find those
sorts of problems, and tedious and error prone to fix them.

This change adds a mechanism to simply annotate what offset a register
should have. That should also make the register list more self
documenting, since you'll be able to easily see what offset a register
has from the source without having to count up everything in front of it.

Change-Id: Ia7e419ffb062a64a10106305f875cec6f9fe9a80
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/66431
Reviewed-by: Yu-hsin Wang <yuhsingw@google.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2022-12-06 13:27:33 +00:00
Yu-hsin Wang
b9c0851120 systemc: fix the payload and packet association in Gem5ToTlm bridge 
If a request is initiated by systemc, passed through TlmToGem5 bridge
and Gem5ToTlm bridge, it wouldn't have the systemc extension about the
association. This feature is also used in TlmToGem5 bridge to detect if
the packet is allocated in the current instance in async interface. In
that case, we would lose the association in the Gem5ToTlm bridge async
interface. For not making wide change, we need an extra way to support
the association in Gem5ToTlm bridge async interface.

This change adds another map to record the association and clears when
the TLM transaction is completed.

Change-Id: I486441e813236ea2cabd1bd6cbb085b08d75ec8f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/66054
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2022-12-06 10:14:40 +00:00
Jarvis Jia
4fc690f6b7 mem-cache: Fix FIFO replacement 
Change FIFO from using curTicks() to using timeTicks counter to
avoid issues where multiple lines are considered to have entered
the cache at the same tick.

Change-Id: I5e0b894eb9bec4f0f8bc8f48ec2766a0fc5079c6
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/65952
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Maintainer: Daniel Carvalho <odanrc@yahoo.com.br>
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
 2022-12-06 02:59:46 +00:00
Bobby R. Bruce
e200ea1510 ext: Update ext/sst/README.md for v22.1 release 
Change-Id: I3221bbc4e4bf1d7a2bd7516873c7bfcf08bebde5
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/65924
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
 2022-12-05 20:25:53 +00:00