Commit Graph

16702 Commits

Author SHA1 Message Date
Gabe Black
20f41dfa93 scons: Update the Check(Cxx|Link)Flag checks to set their vars.
This avoids boilerplate where we check to see if flag X is supported,
and if so then set flag X. Since there are shared and static versions of
the linker flags but we only explicitly check the static ones, this
change also adds a parameter to CheckLinkFlag to set both flavors. This
defaults to true since I assume most of the time linking flags will
apply to both.

Change-Id: I983222169e9835aeb98570362f7004e2ef0240d0
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40855
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-02-10 11:34:51 +00:00
Gabe Black
51ca61dbf6 scons: Remove partial linking.
This feature didn't actually provide any benefit in the end, and
increased build directory size and scons complexity.

Change-Id: Ia5aa16a8dd008599645076cea8131799f6086e0f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40795
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-02-10 11:34:19 +00:00
Gabe Black
ca3670fbd1 cpu: Delete the empty, default off "nocpu".
This very nearly empty CPU directory does nothing except define a CPU at
the scons level which is off by default. It seems safe to delete it.

Change-Id: I5bd3a52062bbc67fb1ee7d350519cd85a3f8fdb8
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40871
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
2021-02-10 11:33:46 +00:00
Giacomo Travaglini
e2b0cecef9 dev-arm: Add VRAM to VExpress_GEM5_Base
Change-Id: Ibd3ae59730c6d00a6bd8b129f973b79a565f66e4
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40973
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-02-10 09:08:52 +00:00
Gabe Black
79db0bacdd scons: Add support for debug info compression.
If supported this will compress the debug information in object files,
libraries, and binaries. This decreases the size of the build/ARM
directory from 11GB to 7.2GB.

Because the benefit of this mechanism depends on the performance and
capacity of the build machine's storage, it can be disabled with the
--no-compress-debug scons flag. For instance if your storage is very
fast, writing out a larger binary may take less time than compressing
that same number of bytes, plus the time to write out the smaller
file.

This feature seems to make our presubmit test machine run out of memory
when trying to build gem5, and so is disabled in the testing scripts.

Change-Id: I71919062d23742b7658918b0fa9c4d91d0521fbf
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40715
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-02-10 09:05:53 +00:00
Hoa Nguyen
0367539e9f cpu: Remove units from stats description
A recent change https://gem5-review.googlesource.com/c/public/gem5/+/40622
allows units to be shown in stats dump; the units in stats
descriptions are nolonger necessary. This change removes units
from stats descriptions. However, for units that are multiples
of a supported unit (e.g. MegaBytes), the units

Change-Id: Ib63ea44e757f755f761b20b40e045bc37c90baff
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40735
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Gabe Black <gabe.black@gmail.com>
2021-02-10 09:03:09 +00:00
Hoa Nguyen
26d2731e5f arch-riscv: Fixed the style of stats variable names in TlbStats
The variable names should be of camel case style.

Change-Id: I397c9f165a53ecc120ec57f7214c90a65e12407e
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40695
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
2021-02-10 09:03:09 +00:00
Hoa Nguyen
42e0247507 dev,dev-arm: Remove units from stats description
A recent change https://gem5-review.googlesource.com/c/public/gem5/+/40622
allows units to be shown in stats dump; the units in stats
descriptions are nolonger necessary. This change removes units
from stats descriptions. However, for units that are multiples
of a supported unit (e.g. MegaBytes), the units in the descriptions
are kept until unit prefixes are supported.

Change-Id: I199afbf29fee13b08eeb323c4cb56c8a974dbe94
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40675
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Gabe Black <gabe.black@gmail.com>
2021-02-10 09:03:09 +00:00
Hoa Nguyen
5aaa392f2e mem: Remove units from stats description
The change https://gem5-review.googlesource.com/c/public/gem5/+/40622
allows units to be shown in stats dump, the units in stats
descriptions are nolonger necessary. This change removes units
from stats descriptions. However, for units that are multiples
of a supported unit (e.g. MegaBytes), the units in the descriptions
are kept until unit prefixes are supported.

Change-Id: I4d87139290a8458e87da776e4328edbd6c224546
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40655
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
2021-02-10 09:03:09 +00:00
Hoa Nguyen
67f5f1c3e3 base-stats: Print Units in Stats dump
Change-Id: I8fba4f19805c3149175ff730d014383dcaa1bf81
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40622
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-02-10 09:03:09 +00:00
Hoa Nguyen
489e72d509 mem: Change warmupCycle stat to warmupTick
Change-Id: I96399dc5c062479049e7bf0de91d9f4f97903c43
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40575
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
2021-02-10 09:03:09 +00:00
Hoa Nguyen
65bbd5fa2a cpu: Add Units to cpu stats
Change-Id: I387b2e9f6ecf62757242056f732bd443c457ebea
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39095
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
2021-02-10 09:03:09 +00:00
Hoa Nguyen
c5c0dd9a24 learning-gem5: Add units to stats
Change-Id: Iaff6c19b0b87250d15f5afb0763680fafe782d52
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39417
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
2021-02-10 09:03:09 +00:00
Hoa Nguyen
9625e90b8e arch-arm,arch-riscv,arch-x86: Add units to stats
Change-Id: I6bf506c223207306d71511491e024546b209030f
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39416
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
2021-02-10 09:03:09 +00:00
Hoa Nguyen
4ab768c54e dev,dev-arm: Add units to stats in /src/dev
Change-Id: I9d2449ef173f2f467717a9d233aef8d9a2f43f26
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39415
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
2021-02-10 09:03:09 +00:00
Hoa Nguyen
eade85fa50 sim: Add units to src/sim
Change-Id: I5fa147aa1319d62be1790bbd74fd097ac566f808
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39296
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
2021-02-10 09:03:09 +00:00
Hoa Nguyen
c720e26c85 mem: Add Units to mem stats
Add units to mem stats except mem-ruby stats

Change-Id: Iab214b5d08eb1accc2b35af0c3aed7d30df5b5f3
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39276
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-02-10 09:03:09 +00:00
Hoa Nguyen
1f1decd765 cpu,mem: Converting stats to supported units
There are several stats having unit being a multiple of supported
units. This change makes the following conversions:
  * MiB/s -> bytes/s
  * percentage -> ratio

Change-Id: I9832796e87698daa7f87f91fa39ce40bbf92e737
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/41013
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
2021-02-10 09:03:09 +00:00
Hoa Nguyen
14732c4f97 mem: Fix/Improve stats in src/mem
* Improved/Fixed the stat description of several stats.
* Fixed the value assigned to `warmupCycle` stat of cache tags,
it was set to curTick().
* Use ADD_STAT in CacheCmdStats.

Change-Id: Iabff7d42318fcc73df79ee7f3c5430f4c45555e5
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39975
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-02-10 09:03:09 +00:00
Hoa Nguyen
e331aa9718 base-stats: Add Units to Stats
This commit adds an option to add SI and its derived units to stats.

Units are now the third parameter of every Stat class constructor.

The following are convenient macros that could be used to add units
to stats,
   * UNIT_CYCLE: represents clock cycles.
   * UNIT_TICK: represents the count of gem5's Tick.
   * UNIT_SECOND: represents the base unit of time defined by SI.
   * UNIT_BIT: represents the number of computer bits.
   * UNIT_BYTE: represents 8 bits.
   * UNIT_VOLT: a SI derived unit measuring potential difference.
   * UNIT_JOULE: represents joule, a unit of energy, as defined by SI.
   * UNIT_WATT: represents 1 watt, where 1 watt = 1 joule / second.
   * UNIT_CELSIUS: represents 1 Celsius degree as defined by SI.
   * UNIT_RATE(T1, T2): represents the unit of a quantity of T1 divided
                        by a quantity of T2.
   * UNIT_RATIO: represents the unit of a quantity of unit T divided by
                 a quantity of unit T.
   * UNIT_UNSPECIFIED: the unit of the stat is unspecified. This type of
                       unit is mainly for backward compatibility. Newly
                       introduced stats should have the units specified.

This commit also alters the behavior of the ADD_STAT macro.
Specifically, ADD_STAT syntax is unchanged, but the unit of the stat
is hardcoded to be UNIT_UNSPECIFIED.

JIRA link: https://gem5.atlassian.net/browse/GEM5-849

This change is an effort towards supporting new stats schema:
https://github.com/gem5/stats-schema

Change-Id: I791704a6c4d9e06332797dbfc5eb611cb43f4710
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/38855
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
2021-02-10 09:03:09 +00:00
Gabe Black
134c37ca3e cpu: Track misc regs in vectors in the O3 CPU instruction class.
Most instructions won't actually write to misc regs, so the overhead
should be quite small, particularlly compared to the other overheads in
the O3.

Change-Id: I840d6002cc8151f91611cfcbe2bfa52acc284c0f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/38388
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
2021-02-10 06:25:12 +00:00
Gabe Black
776822d147 cpu: Track flat register indices in the Minor CPU with a vector.
That avoids having to know the maximum number of dest registers there
can be in any instruction, and will likely not affect the performance of
the Minor CPU overall.

Change-Id: I4e49695ba06365d52eb4ce128d5cbb30db665bd7
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/38387
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
2021-02-10 06:25:06 +00:00
Gabe Black
08aa5351c0 cpu: Factor MaxInst(SrcDest)Regs out of the trace CPU.
Manage register and ROB dependencies using lists instead of arrays to
better support random removals, and avoid having to know the global
maximum number of registers in an instruction.

Change-Id: Ie9f30c61bac52ad31745a1011f62c95622908d2f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/38386
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-02-10 06:07:09 +00:00
David Schall
f7e0115882 base: Add XOR and modulo operator to ChannelAddr
Channel address class did not offer bitwise
XOR and modulo operation. These two functions
where now added to the ChannelAddr class.

Change-Id: I02a5e49e9700cc5283415c921a25989a130e5d07
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39235
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-02-09 12:39:28 +00:00
Gabe Black
6e976fbb4b sim: Get rid of the IsConforming type trait template.
The idea of this template was to distinguish types which should
grow/shrink based on the native size of the ABI in question. Or in other
words, if the ABI was 32 bit, the type should also be 32 bit, or 64 bit
and 64 bit.

Unfortunately, I had intended for Addr to be a conforming type (since
local pointers would be conforming), but uint64_t not to be. Since Addr
is defined as a typedef of uint64_t, the compiler would make *both*
types conforming, giving incorrect behavior on 32 bit systems.

Local pointers will need to be handled in a different way, likely with
the VPtr template, so that they will be treated correctly and not like
an explicitly 64 bit data type.

Change-Id: Idfdd5351260b48bb531a1926b93e0478a297826d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40495
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-02-09 00:36:00 +00:00
Gabe Black
0e0183f1d9 arch,sim: Use VPtr<> instead of Addr in system call signatures.
This tells the GuestABI mechanism that these are guest pointers and not
uint64_ts, and that they should be treated as 32 bit or 64 bit values
depending on the size of pointers in the target ABI.

Change-Id: Ia9b5447848c52668a975d8b07b11ad457e756b13
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40498
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
2021-02-09 00:35:39 +00:00
Giacomo Travaglini
1ea62dcf80 dev-arm: Reduce boilerplate when read/writing to Pio devices
Change-Id: Id59ac950f37d7f4f2642daf324d501da1ee622de
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40775
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-02-08 14:54:39 +00:00
Daniel R. Carvalho
0a63e9ff0a dev: Fix register bank unit test in .debug
The lack of definition of this static variable was throwing
and undefined reference error when running

  scons build/X86/unittests.opt.

For more info, check

  https://stackoverflow.com/questions/
    8016780/undefined-reference-to-static-constexpr-char

Change-Id: Id736dc42a82aea871da6a53c06d89fd399d3559a
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40836
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-02-07 13:07:14 +00:00
Daniel R. Carvalho
b75ff8fcff base: Fix storage unit test in .fast
These tests depend on assertions being triggered, which
does not happen in .fast.

Change-Id: I0dd78f184809a453035046bc76640dfb5988bb5f
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40835
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-02-07 13:07:14 +00:00
Gabe Black
31bab6f6ac tests,base: Delete the SymbolTable::load method and symtest test.
This test expects to load a symbol file using the load method of gem5's
SymbolTable class, and then to search through it for a given symbol or
address.

Unfortunately, the type of file it expects to load has a format where
each line is of the form:

0x00000000, symbol_name

where the numerical part is the address of the symbol, and the part
after the comma is the symbol name. I have not been able to find any
tool which outputs a symbol file in this format, or any tool for
inspecting an existing object file which will output symbols in this
format. I looked at objdump, objcopy, nm, and the map file format output
by gnu's linker. nm has 3 different output formats, none of which match.
Usually when working with ELF files, one would just generate a new ELF
file which only had debugging information like the symbol table, and
then strip the symbols out of the original.

Since this file format seems to have been invented from thin air, there
isn't really a good way to generate a canonical file to test the loading
code against, nor is being able to load this obscure format likely to be
useful to anybody. If someone *did* want to load an external symbol
table, they would use the ELF loader and not this.

This CL deletes both this test, and the loading code in SymbolTable.

Change-Id: I20402e3f35e54d1e186a92d9c83d1c06ec86bf7d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40620
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-02-06 04:02:16 +00:00
Boris Shingarov
2df06e292a arch-power: Restore consistency with other platforms
The 32-bit POWER reference test binary was removed in c1ebdf66f
(as a nasty surprise for POWER users).

The remaining platforms split between two approaches:

MIPS rebuilds "hello" from source.
This fails for two reasons:
1) The trivial reason is that on POWER make abends due to no makefile.
2) The more fundamental reason is that gem5 is not completely bug-free
(especially the Decoder on POWER in this case), therefore regression
testing is only possible if we have not just some hello program, but
a very particular bit sequence to serve as an immutable reference.

ARM and X86 follow the reference-bit-sequence approach.  POWER will
be consistent with same.  Including the sha1 for hello32,
77b27b67393311546e768b5ff35202490bad71aa, as a simple immutability
assurance.  I have also renamed hello to hello32 in anticipation to
merge Sandipan's e52dbcb.

Change-Id: I77ef31349c9e50b987c6f58bb23324844527366d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40635
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Sandipan Das <sandipan@linux.ibm.com>
Reviewed-by: Pratik Sampat <pratik.r.sampat@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-02-06 02:39:24 +00:00
Gabe Black
16727d1709 sim: Add a void * analogue to VPtr.
The default type for VPtr is now void, and the void partial
specialization of VPtr is basically just a fancy container for Addr. Its
purpose is to distinguish guest addresses from actual uint64_t-s in the
signature of simcalls so that types which are purposefully 64 bits will
stay that way, and addresses will scale to the size of pointers in the
target ABI.

Change-Id: I71e2201f5917005861ba678c6675dbcbaa0965b3
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40497
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
2021-02-06 01:13:58 +00:00
Gabe Black
c1ec1c2aba arch,sim: Add a UintPtr type to the ABI types for GuestABI.
This type is primarily used to determine the size of a pointer when
using that ABI, similar to the uintptr_t type, but also less directly
to determine the "native" size of the ABI. For instance, for 32 bit ARM
ABIs, it should be defined as uint32_t since that's both the size of a
uintptr_t, and, less directly, the size of a 32 bit ARM register and
"naturally" sized types in that ABI.

This type can be used by the VPtr template to retrieve its actual value
from a simcall's parameters. In general, when accepting or returning a
pointer or address in a simcall, the VPtr template should be used so
that it's managed correctly by GuestABI. Addr will be treated as a
uint64_t allways which will be incorrect for 32 bit ABIs.

Change-Id: I3af046917387541d6faff96a21a1f1dbf7317e06
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40496
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
2021-02-06 01:13:50 +00:00
Daniel R. Carvalho
1055e187cc base: Initialize storage params on constructor
Force error checking on storage params by imposing it on construction.

Change-Id: I66a902cd5a7c809d3ac5be65b406de29fc0acf1c
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25426
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
2021-02-05 19:01:41 +00:00
Daniel R. Carvalho
0f7441fa2d base: Fix storage params safe_cast
Although they provide the exact same behavior, the params
created in the tests did not have the type expected by the
internal safe cast.

The following error was triggered:

storage.test.debug: build/NULL/base/cast.hh:47: T safe_cast(U)
 [with T = const Stats::SampleStor::Params*;
  U = const Stats::StorageParams*]:
 Assertion `ret' failed.

Change-Id: I4f2ba51f3ccdb44589e61f235997245e7d9bf3c9
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40555
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
2021-02-05 18:51:43 +00:00
Daniel R. Carvalho
3c915a2e84 base: Make read-only functions const in ScalarBase
These functions do not need to modify their storage's contents.

ScalarBase's non-const value() has been removed.

Change-Id: I4dd3899a29a741a7d8cd199ccd254b346d86ae07
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27084
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
2021-02-05 14:10:31 +00:00
Gabe Black
5ca6b83944 tests: Delete the now unused unittest/unittest.[cc|hh].
These files were originally used to provide a more gtest like mechanism
for the UnitTest executables, many of which didn't actually test
anything. With the definitions in those files, the tests could check
whether their expectations were met, and either pass or fail without a
human having to inspect the output and knowing what output to expect.

Change-Id: Ie0601391b994859eb544b37201333838fa3ba02a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40618
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
2021-02-05 09:34:39 +00:00
Gabe Black
8d92183669 base,tests: Convert cprintftime from a "UnitTest" to a normal bin.
This "UnitTest" was really not a unit test, it was a timing utility for
measuring the performance of gem5's cprintf implementation. The name was
misleading, but more than that, it was linked against all of gem5 which
created a approximately 1.5 gigabyte binary for what is a very small
program.

Instead, the new version of cprintftime, which has the same
functionality as the old version, weighs in at a svelte 500k with debug
information.

This also trims down the number of misleading "UnitTest" entries to 3,
getting us closer to the point where we can eliminate that type of
entity entirely.

Change-Id: Id30d094f2844e948fe67e820c89412f8667aaa52
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40617
Maintainer: Gabe Black <gabe.black@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
2021-02-05 09:34:21 +00:00
Gabe Black
2af0d1e9e8 scons: Remove the "abstract" tag from Executable classes.
That tag was intended to mark an Executable subclass as abstract, aka
only suitable for using as bases for other Executable subclasses and not
for direct instantiation. The only place it was used was the base
Executable class however, and that class is actually directly useful
when setting up a generic executable from other gem5 sources.

Change-Id: I70204b63c03bb45bf21b8c312a7b8581be5e0cab
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40616
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
2021-02-05 09:34:12 +00:00
Gabe Black
877d63b3d2 base: Replace a "panic" in cprintf with an M5_UNREACHABLE.
The panic was just to signal that a point in the code should be
unreachable, and brought with it a thread of dependencies which would
bring in more and more extra files as it was followed.

Change-Id: I46fb99b91929dca78a6547bdc7635aab9a63a9f3
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40615
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
2021-02-05 08:36:14 +00:00
Boris Shingarov
a116ff6bc7 util,python: Ignore ELF binary blobs in pre-commit
Change-Id: I60554b2ae7536687a6c0a883a7678f793c3c77d4
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40636
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-02-05 04:09:54 +00:00
Gabe Black
a2a24b3396 base: Remove unnecessary includes from base/loader/symtab.[cc|hh].
These were either completely unnecessary, or headers in the .cc which
had already been included in the .hh and were not needed beyond their
use in the .hh.

Change-Id: Ic95e29f3fdd8cab00ab93d254d2e1c25aacf4632
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40619
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-02-05 04:01:52 +00:00
Gabe Black
b3254e142f arch,cpu: Move a Decode DPRINTF into the arch Decoder classes.
This DPRINTF accesses the ExtMachInst typed machInst member of the
StaticInst class, and so is ISA dependent. Move the DPRINTF to where the
instructions are actually decoded where that type doesn't have to be
disambiguated.

Also, this change makes this DPRINTF more accurate, since microops are
not really "decoded" when they are extracted from a macroop. The process
of unpacking them to feed into the rest of the CPU should be fairly
trivial, so really they're just being retrieved. With the DPRINTF in
this new position, it will only trigger when an instruction is actually
decoded from memory.

Change-Id: I14145165b93bb004057a729fa7909cd2d3d34d29
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40099
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-02-05 03:06:00 +00:00
Gabe Black
344ea0330a cpu: Replace fixed sized arrays in the O3 inst with variable arrays.
The only way to allocate fixed sized arrays which will definitely be big
enough for all source/destination registers for a given instruction is
to track the maximum number of each at compile time, and then size the
arrays appropriately. That creates a point of centralization which
prevents breaking up decoder and instruction definitions into more
modular pieces, and if multiple ISAs are ever built at once, would
require coordination between all ISAs, and wasting memory for most of
them.

The dynamic allocation overhead is minimized by allocating the storage
for all variable arrays in one chunk, and then placing the arrays there
using placement new. There is still some overhead, although less than it
might be otherwise.

Change-Id: Id2c42869cba944deb97da01ca9e0e70186e22532
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/38384
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-02-05 03:04:56 +00:00
Gabe Black
57dd228cad cpu: Style fixes in the trace CPU.
Change-Id: I3ef51aa8667926f3c4fab3c11e188102dd4bab3c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/38385
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
2021-02-04 14:35:06 +00:00
Bobby R. Bruce
5eaff959da misc: Revert version info for develop branch
Change-Id: Ie01f41cb40b025ef31028bff4d59023e380fcf07
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40536
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-02-04 05:01:00 +00:00
Bobby R. Bruce
063d58fd71 Merge "misc: Merge branch v20.1.0.3 hotfix into develop" into develop 2021-02-04 05:01:00 +00:00
Earl Ou
03fc457b86 fastmodel: fix cntfrq in A76
Change-Id: I7d1167e8b61d6768039c34fe1ee54560f7845dfa
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40355
Reviewed-by: Ahbong Chang <cwahbong@google.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-02-04 01:48:13 +00:00
Alexandru Dutu
14d6e8fac4 arch-gcn3: Implementation of s_sleep
This changeset implements the s_sleep instruction in a similar
way to s_waitcnt.

Change-Id: I4811c318ac2c76c485e2bfd9d93baa1205ecf183
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39115
Maintainer: Matthew Poremba <matthew.poremba@amd.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-02-04 00:07:10 +00:00
Kyle Roarty
4060208a04 arch-x86: Make JRCXZ instruction do 64-bit jump
Per the AMD64 Architecture Programming Manual:

The size of the count register (CX, ECX, or RCX) depends on the
address-size attribute of the JrCXZ instruction. Therefore, JRCXZ can
only be executed in 64-bit mode

and

In 64-bit mode, the operand size defaults to 64 bits. The processor
sign-extends the 8-bit displacement value to 64 bits before adding it
to the RIP.

This patch also renames the instruction from JRCX to JRCXZ to match the
language in the programming manual.

Change-Id: Id55147d0602ff41ad6aaef483bef722ff56cae62
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40195
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-02-04 00:06:59 +00:00