Commit Graph

26 Commits

Author SHA1 Message Date
Bobby R. Bruce
ddf6cb88e4 misc: Run pre-commit run --all-files
This is reflect the updates made to black when running `pre-commit
autoupdate`.

Change-Id: Ifb7fea117f354c7f02f26926a5afdf7d67bc5919
2023-10-10 14:01:58 -07:00
Roger Chang
e41184fafc util: Update the RISC-V PCState checkpoint
Change-Id: I64b6a3e1706173a001f5f8fb06756bd50d65f5bd
2023-09-12 17:54:35 +08:00
Adrià Armejach
f777cc143c util: fix cpt upgrader for rvv changes in PR #83
* Solves issue #106 by updating the cpts with the necessary vector
    registers.

Change-Id: Ifeda90e96097f0b0a65338c6b22a8258c932c585

util: clear vector_element field

Change-Id: I6c9ec4e71f66722b26de030fa139cd626bdb24dc
2023-08-04 13:59:23 +02:00
Giacomo Travaglini
e73655d038 misc: Use python f-strings for string formatting
This patch has been generated by applying flynt to the
gem5 repo (ext has been excluded)

JIRA: https://gem5.atlassian.net/browse/GEM5-831

Change-Id: I0935db6223d5426b99515959bde78e374cbadb04
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/68957
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby Bruce <bbruce@ucdavis.edu>
2023-03-16 09:05:29 +00:00
Hoa Nguyen
eac06ad681 python: Fix multiline quotes in a single line
An example case,
```python
mem_side_port = RequestPort(
    "This port sends requests and " "receives responses"
)
```

This is the residue of running the python formatter.
This is done by finding all tokens matching the regex `"\s"(?![.;"])`
and manually replacing them by empty strings.

Change-Id: Icf223bbe889e5fa5749a81ef77aa6e721f38b549
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/66111
Reviewed-by: Bobby Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-11-29 23:44:38 +00:00
Bobby R. Bruce
2bc5a8b71a misc: Run pre-commit run on all files in repo
The following command was run:

```
pre-commit run --all-files
```

This ensures all the files in the repository are formatted to pass our
checks.

Change-Id: Ia2fe3529a50ad925d1076a612d60a4280adc40de
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/62572
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
2022-08-24 21:47:07 +00:00
Gabe Black
3d7d426fa5 cpu: Generalize how register files are serialized.
Instead of explicitly serializing each type of register explicitly, and
using custom types, etc, store them as generic blocks of data. This lets
us get rid of the final use of TheISA::VecRegContainer and
TheISA::VecPredRegContainer.

Change-Id: I61dbd7825ffe35c41e1b7c8317590d06c21b4513
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/50252
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
2022-08-04 20:22:32 +00:00
Bobby R. Bruce
787204c92d python: Apply Black formatter to Python files
The command executed was `black src configs tests util`.

Change-Id: I8dfaa6ab04658fea37618127d6ac19270028d771
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/47024
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-08-03 09:10:41 +00:00
Gabe Black
1a1ba692c3 sim: Move the MemPools object out of System and into SEWorkload.
This removes the need for all the FullSystem checks in the System class,
and simplifies that class in general.

Change-Id: Ie8a3bc67db9195027d2111009b15ca59221bdeb2
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/50348
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-09-30 00:30:49 +00:00
Gabe Black
61a6ec7b71 sim: Move serialization logic for MemPools out of System.
And move it into the MemPools class itself. The MemPools class should be
self contained, and be able to manage its own state. That should not be
the responsibility of another containing class.

Change-Id: Ib0bf70b57e92698f15bea0cc217dd98ee816d57b
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/50340
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
2021-09-29 12:17:35 +00:00
Gabe Black
afee6296b5 util: Add a fallback when checking for root.isa in checkpoints.
The upgraders in util/cpt_upgraders have been able to check the
root.isa element of checkpoints to determine what "the" ISA is for a
simulation, as a quick way to bail out of that particular updater
applies only to specific ISAs. We are moving away from the idea that
there is a single ISA, and so this mechanism will no longer work.

Fortunately, these cpt_upgraders are only relevant for old checkpoints.
If a checkpoint doesn't have a root.isa element inside it at all, we
know (as of this writing) that it is newer than all of these upgraders
and hence they do not apply. Any new upgraders will have to be written
to not rely on the root.isa field which will be removed. If that sort
of field is still needed, it can be added somewhere else in the
hierarchy, perhaps at the system level, or as part of the actual ISA
object.

The simplest way to implement this new behavior is to add a fallback
option when an upgrader looks for root.isa, specifically ''. If the
root.isa element does not exist, the script will get '' back, and this
will not match whatever ISA it's trying to check against. The one even
remotely more complicated script is isa-is-simobject.py which has
several behaviors for different ISAs. In that case, we just explicitly
check for '' and return early if that's what we found.

Jira Issue: https://gem5.atlassian.net/browse/GEM5-1056

Change-Id: Ie78deccb2bac51f38224e62a28dd733cefd63ed7
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/48883
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
2021-07-31 09:56:40 +00:00
Daniel R. Carvalho
19c7429520 sim,util: Remove event dependencies from serialize.hh
With this change serialize.hh is no longer responsible
for the (un)serialization of events. As a general rule,
rules to (un)serialize non-basic types should be defined
at the file that introduces that type. Therefore,
(UN)SERIALIZE_EVENT have been moved to eventq.hh.

Globals has a single instance which must be serialized
and unserialized. Instead of having a stray global
variable handled by Serialization, we pass its management
to Root. As a side effect, Globals is assigned its own
files: sim/globals.(cc/hh).

Finally, 'unserializeGlobals()' is removed, so that
Root can fully handle Globals' serialization. This
breaks checkpoint compatibility, so a checkpoint
upgrader is added.

Change-Id: I9c8e57306f83f9cc30ab2b745a4972755191bec4
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/43586
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
2021-06-16 10:50:26 +00:00
Giacomo Travaglini
2a2bc262f3 util: Port util to python3
This commit is the result of running 2to3 converter on the util
subdirectory

JIRA: https://gem5.atlassian.net/browse/GEM5-832

Change-Id: I4e7e2d2b1b99f7bcc5fe0f6dc5d25880323616eb
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/37797
Reviewed-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-11-27 15:17:30 +00:00
Giacomo Travaglini
7ce081d583 misc: Remove any reference to the ALPHA ISA
Change-Id: Ie761cd69ae0e8e632ca2b92e63a404e8804f0e6f
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/30015
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-06-08 09:00:55 +00:00
Giacomo Travaglini
58a797d36c util: Make cpt_upgraders python3 compatible
It won't be possible to build gem5 in a python3 only environment
otherwise since the cpt_upgrader.py script is automatically run at the
end of compilation

Change-Id: Iea4217e5cd64ca44b99aa0db5dabfdced7aeb3ea
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28587
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-05-06 08:15:15 +00:00
Gabe Black
52b3f58a8c util: Delete authors lists from files in util.
Change-Id: I2a165d3130c1464a73823046e4c7b03ba0355459
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25457
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
2020-02-18 10:24:43 +00:00
Giacomo Gabrielli
c4cc3145cd arch-arm,cpu: Add initial support for Arm SVE
This changeset adds initial support for the Arm Scalable Vector Extension
(SVE) by implementing:
- support for most data-processing instructions (no loads/stores yet);
- basic system-level support.

Additional authors:
- Javier Setoain <javier.setoain@arm.com>
- Gabor Dozsa <gabor.dozsa@arm.com>
- Giacomo Travaglini <giacomo.travaglini@arm.com>

Thanks to Pau Cabre for his contribution of bugfixes.

Change-Id: I1808b5ff55b401777eeb9b99c9a1129e0d527709
Signed-off-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/13515
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-03-14 10:42:27 +00:00
Curtis Dunham
2f14baaabc arm, dev: refactor GIC Pl390 GICD_ITARGETSRn handling
The aforementioned registers (Interrupt Processor Targets Registers) are
banked per-CPU, but are read-only.  This patch eliminates the per-CPU
storage of these values that are simply computed.

Change-Id: I52cafc2f58e87dd54239a71326c01f4923544689
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/2442
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Weiping Liao <weipingliao@google.com>
2017-04-03 16:51:46 +00:00
Curtis Dunham
b7d072b235 dist, dev: fix etherswitch upgrade script
The aforementioned upgrader in [1] assumes every option in [system]
has a delimiting '.', and also seems to do its rewriting work a bit too
unconditionally.  Most checkpoints in the wild don't have this device,
in which case this script should be a safe no-op.

[1] 2aa4d7b  dist, dev: Fixed the packet ordering in etherswitch

Change-Id: Icfd0350985109df1628eb9ab864cda42c54060a8
Reviewed-by: Gabor Dozsa <gabor.dozsa@arm.com>
2016-12-19 12:12:28 -06:00
Curtis Dunham
19d90956eb arm: update AArch{64,32} register mappings
Change-Id: Idaaaeb3f7b1a0bdbf18d8e2d46686c78bb411317
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
2016-12-19 11:03:27 -06:00
Curtis Dunham
fc8fd0fd18 arm: bank GIC registers per CPU
Updated according to GICv2 documentation.

Change-Id: I5d926d1abf665eecc43ff0f7d6e561e1ee1c390a
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
2016-08-02 13:35:45 +01:00
Mohammad Alian
e5b7b6780f dist, dev: Fixed the packet ordering in etherswitch
This patch fixes the order that packets gets pushed into the output fifo
of etherswitch. If two packets arrive at the same tick to the etherswitch,
we sort and push them based on their source port id.
In dist-gem5 simulations, if there is no ordering inforced while two
packets arrive at the same tick, it can lead to non-deterministic simulations

Committed by Jason Lowe-Power <power.jg@gmail.com>
2016-06-08 09:12:41 -05:00
Karthik Sangaiah
6fa936b021 dev, arm: Add gem5 extensions to support more than 8 cores
Previous ARM-based simulations were limited to 8 cores due to
limitations in GICv2 and earlier. This changeset adds a set of
gem5-specific extensions that enable support for up to 256 cores.

When the gem5 extensions are enabled, the GIC uses CPU IDs instead of
a CPU bitmask in the GIC's register interface. To OS can enable the
extensions by setting bit 0x200 in ICDICTR.

This changeset is based on previous work by Matt Evans.
2015-09-18 16:49:28 +01:00
Mitch Hayenga
a5c4eb3de9 isa,cpu: Add support for FS SMT Interrupts
Adds per-thread interrupt controllers and thread/context logic
so that interrupts properly get routed in SMT systems.
2015-09-30 11:14:19 -05:00
Andreas Sandberg
f7055e9215 dev, arm: Rewrite the HDLCD controller
Rewrite the HDLCD controller to use the new DMA engine and pixel
pump. This fixes several bugs in the current implementation:

   * Broken/missing interrupt support (VSync, underrun, DMA end)
   * Fragile resolution changes (changing resolutions used
     to cause assertion errors).
   * Support for resolutions with a width that isn't divisible by 32.
   * The pixel clock can now be set dynamically.

This breaks checkpoint compatibility. Checkpoints can be upgraded with
the checkpoint conversion script. However, upgraded checkpoints won't
contain the state of the current frame. That means that HDLCD
controllers restoring from a converted checkpoint immediately start
drawing a new frame (i.e, expect timing differences).
2015-09-11 15:55:46 +01:00
Curtis Dunham
87b9da2df4 sim: tag-based checkpoint versioning
This commit addresses gem5 checkpoints' linear versioning bottleneck.
Since development is distributed across many private trees, there exists
a sort of 'race' for checkpoint version numbers: internally a checkpoint
version may be used but then resynchronizing with the external tree causes
a conflict on that version.  This change replaces the linear version number
with a set of unique strings called tags.  Now the only conflicts that can
arise are of tag names, where collisions are much easier to avoid.

The checkpoint upgrader (util/cpt_upgrader.py) upgrades the version
representation, as one would expect. Each tag version implements its
upgrader code in a python file in the util/cpt_upgraders directory
rather than adding a function to the upgrader script itself.

The version tags are stored in the 'Globals' section rather than 'root'
(as the version was previously) because 'Globals' gets unserialized
first and can provide a warning before any other unserialization errors
can occur.
2015-09-02 15:23:30 -05:00