Implementation of the Access Map Pattern Matching prefetcher
Based in the description of the following paper:
Access map pattern matching for high performance data cache prefetch.
Ishii, Y., Inaba, M., & Hiraki, K. (2011).
Journal of Instruction-Level Parallelism, 13, 1-24.
Change-Id: I0d4b7f7afc2ab4938bdd8755bfed26e26a28530c
Reviewed-on: https://gem5-review.googlesource.com/c/15096
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Prefetchers can be configured to operate with virtual or physical addreses.
The option can be configured through the "use_virtual_addresses" parameter
of the Prefetcher object.
Change-Id: I4f8c3687988afecc8a91c3c5b2d44cc0580f72aa
Reviewed-on: https://gem5-review.googlesource.com/c/14416
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Trying to read MPIDR(_EL1) from EL1, should return the value of
VMPIDR_EL2 if EL2 is enabled. This patch is modifying the utility
function for reading MPIDR in order to match this behaviour for both
AArch32 and AArch64.
Change-Id: I32c2d4d5052f509e6e0542a5314844164221c6a3
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/15617
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Implement the Interrupts SimObject for RISC-V. This basically just
handles setting and getting the values of the interrupt-pending and
interrupt-enable CSRs according to the privileged ISA reference chapter
3.1.14. Note that it does NOT implement the PLIC as defined in chapter
7, as that is used for handling external interrupts which are defined
based on peripherals that are available.
Change-Id: Ia1321430f870ff5a3950217266fde0511332485b
Reviewed-on: https://gem5-review.googlesource.com/c/14377
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
In addition to fixing some style issues with resetting, this patch fixes
what happens on reset. The RISC-V privileged ISA reference manual says
that,
on reset:
1. Privilege mode is set to M
2. mstatus.mie <- 0; mstatus.mprv <- 0
3. PC <- reset vector
4. mcause <- reset cause (0 if there is no distinguishing causes)
5. Everything else is undefined
Because of 5, everything else will be left alone
Change-Id: I81bdf7a88b08874e3c3d5fc6c7f3ca2d796496b8
Reviewed-on: https://gem5-review.googlesource.com/c/14376
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
The error checking in that function used an if/else structure where
one of the two branches would be the error condition which would cause
the function to exit. Because the function would exit if an error was
detected, there's no reason to have the non-error condition guarded in
the other half of the if.
This change de-nests the non-error cases to make the function simpler
and easier to read.
Change-Id: Idedf54e84a178fa5a2a47f96373374152e420cf3
Reviewed-on: https://gem5-review.googlesource.com/c/15516
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Recent MacOS versions are distributed with python 2.7.
This version of python is sufficient to compile and run gem5.
This patch allows to use the default python instead of the version provided
by third-party tools (e.g., brew)
The default MacOS LLDB debugger is linked against the default python
installation, which conflicts with Python framework provided by third-party
package systems.
This patch removes the need of gem5 to have multiple python installations
on MacOS, if not explicitly installed.
Change-Id: I98f24804149cb2e04ca432c66d2f57e0296af7b2
Reviewed-on: https://gem5-review.googlesource.com/c/15475
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
The default python on MacOS doesn’t have an alias to python2.
The official python version supported in gem5 is Python2.7.
This patch updates the shabang according to the version required in gem5.
Change-Id: I9533c0f7858b5b3cab0ef101be1ee5cd718105b0
Reviewed-on: https://gem5-review.googlesource.com/c/15375
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Some parts of clone are architecture dependent. In some cases, we are
able to use architecture-specific helper functions or register
aliases. However, there is still some architecture-specific that is
protected by ifdefs in the common clone implementation.
Move these architecture-specific bits to the architecture-specific OS
class instead to avoid these ifdefs and make the code a bit more
readable.
Change-Id: Ia0903d738d0ba890863bddfa77e3b717db7f45de
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Cc: Giacomo Travaglini <giacomo.travaglini@arm.com>
Cc: Javier Setoain <javier.setoain@arm.com>
Cc: Brandon Potter <Brandon.Potter@amd.com>
Reviewed-on: https://gem5-review.googlesource.com/c/15435
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Brandon Potter <Brandon.Potter@amd.com>
The __to_number helper function defined in base/str.hh is used by
unserializing code. Its purpose is to convert a string into an
integral/floating point number. Since enums underlying type can only be
an integer type, it makes sense to extend the helper function for enums
as well. In this way it will be possible to unserialize Enums and
containers of Enums without the need of casting.
Change-Id: I74069cc4c04ec8b5eb80939acea7ab18fb366dd4
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/15336
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
The sc_event_finder class in Accellera's implementation has a
non-standard report_error function that it uses internally. The TLM
headers were calling that function in their own event finder subclass.
This change replaces that call with what should be an equivalent bit of
code which is based on the report_error implementation.
Change-Id: Id57d26791df01403a77e70d5f4a00f650dc33599
Reviewed-on: https://gem5-review.googlesource.com/c/15063
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
The former is either the same as the later, or a custom wrapper if
C++11 isn't supported. Since we generally expect C++11 support, we can
skip the indirection.
Change-Id: I9a45e3854bb7cc56d094e3fe2773fe4b5c94403b
Reviewed-on: https://gem5-review.googlesource.com/c/15297
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
This makes those files more consistent with other headers in gem5. The
top level headers (tlm and tlm.h) and the tlm_utils headers were left
alone since the user might reasonably expect those to have a well known
name. The tlm_core headers by comparison are an implementation detail,
and users shouldn't include them directly by name.
Change-Id: Ibc82e8159e47717c79d76f50ed96fdd619294a06
Reviewed-on: https://gem5-review.googlesource.com/c/15067
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
One TLM test will complain if argc isn't 1 or 2, assuming that that
must mean that argc > 2. If it's 0 then the test will also complain and
fail. We therefore need to pass it at least a dummy value in argv/argc.
Change-Id: I5c64856f46d1459d7238e88ad8ba06933c7c38b8
Reviewed-on: https://gem5-review.googlesource.com/c/15065
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
A lot of TLM implementation assumes the string functions (memcpy,
memset, etc) are available, but don't include cstring. Lets do that
for them to avoid having to fix up a lot of places.
Change-Id: I1f26d3a227fe2cefc2613e24cbb0333216e46ee9
Reviewed-on: https://gem5-review.googlesource.com/c/15060
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
We already know those files belong to tlm because of the directory
they're in. Removing the prefix makes the paths of the headers less
enormously long.
Change-Id: I869e58fae904162f353bb31f4c0919fba08dffa6
Reviewed-on: https://gem5-review.googlesource.com/c/15059
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
The TLM event finder class was calling implementation specific
functions from the Accellera version of systemc. This change replaces those
calls with equivalent calls which match the gem5 implementation.
Change-Id: I0ecdb0a4bf09aeb1aad823a01105fbd88edb4601
Reviewed-on: https://gem5-review.googlesource.com/c/15075
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
Both basic systemc and tlm tests were present, but scons only looked
in the systemc directory when populating the test json. This change
makes it also look in the tlm directory so that those tests can be run.
Change-Id: Id65b744664350f6105fb3a4f28cbc7ab91d8c82e
Reviewed-on: https://gem5-review.googlesource.com/c/15056
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
These headers will need to be cleaned up and have some Accellera
specific quirks ironed out of them, but I'll do that in a later change
to make it clear what those changes are.
Change-Id: Ia4e08633ab552b4c616c66c9b7e2bbd78ebfe7b9
Reviewed-on: https://gem5-review.googlesource.com/c/15055
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
Up until Apple LLVM version 10.0.0 (clang-1000.11.45.5), partial
linked objects do not expose symbols that are marked with the hidden
visibility and consequently building gem5 on Mac OS fails. As a
workaround, we disable partial linking, however, we may want to
revisit in the future.
Change-Id: I0a26dae082bf723c2bd49d90e4497e44ecab9c41
Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/15235
Reviewed-by: Andrea Mondelli <andrea.mondelli@ucf.edu>
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
The PL011 spec specifies a DMACR register at offset 0x48, which isn't
implemented in the model. Currently any attempt to access the register
results in a panic.
This change swaps the panic for a warning only when software writes into
DMACR to disable DMA, keeping the panic otherwise.
Change-Id: I04586b52df8d5d174536276fd7ae19e77ff4681a
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/15279
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
