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arch-arm: Added TLBI_ALL EL2 instruction

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This patch is adding TLBI_ALLE2(IS) operations to the arm ISA.

Change-Id: I8e35cff9a2cc414f4c5fbbc5aa0cfe5023a3f011
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Anouk Van Laer <anouk.vanlaer@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/15616
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
This commit is contained in:
Anouk Van Laer
2018-09-03 12:17:27 +01:00
committed by Giacomo Travaglini
parent b47b123b32
commit 671840615b
1 changed files with 11 additions and 3 deletions
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14
src/arch/arm/isa.cc
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@@ -1338,9 +1338,17 @@ ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc)
tlbiOp.broadcast(tc);
return;
}
// @todo: uncomment this to enable Virtualization
// case MISCREG_TLBI_ALLE2IS:
// case MISCREG_TLBI_ALLE2:
// AArch64 TLB Invalidate All, EL2, Inner Shareable
case MISCREG_TLBI_ALLE2:
case MISCREG_TLBI_ALLE2IS:
{
assert64(tc);
scr = readMiscReg(MISCREG_SCR, tc);
TLBIALL tlbiOp(EL2, haveSecurity && !scr.ns);
tlbiOp(tc);
return;
}
// AArch64 TLB Invalidate All, EL1
case MISCREG_TLBI_ALLE1:
case MISCREG_TLBI_VMALLE1: