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dev, arm: Warn on PL011 DMA disable

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The PL011 spec specifies a DMACR register at offset 0x48, which isn't
implemented in the model. Currently any attempt to access the register
results in a panic.

This change swaps the panic for a warning only when software writes into
DMACR to disable DMA, keeping the panic otherwise.

Change-Id: I04586b52df8d5d174536276fd7ae19e77ff4681a
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/15279
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
This commit is contained in:
Jan-Peter Larsson
2018-12-20 15:55:56 +00:00
committed by Giacomo Travaglini
parent 272e4aa26d
commit 1a4a617c7e
2 changed files with 13 additions and 0 deletions
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12
src/dev/arm/pl011.cc Normal file → Executable file
View File

@@ -133,6 +133,10 @@ Pl011::read(PacketPtr pkt)
DPRINTF(Uart, "Reading Masked Int status as 0x%x\n", maskInt());
data = maskInt();
break;
case UART_DMACR:
warn("PL011: DMA not supported\n");
data = 0x0; // DMA never enabled
break;
default:
if (readId(pkt, AMBA_ID, pioAddr)) {
// Hack for variable size accesses
@@ -239,6 +243,14 @@ Pl011::write(PacketPtr pkt)
dataAvailable();
}
break;
case UART_DMACR:
// DMA is not supported, so panic if anyome tries to enable it.
// Bits 0, 1, 2 enables DMA on RX, TX, ERR respectively, others res0.
if (data & 0x7) {
panic("Tried to enable DMA on PL011\n");
}
warn("PL011: DMA not supported\n");
break;
default:
panic("Tried to write PL011 at offset %#x that doesn't exist\n", daddr);
break;

1
src/dev/arm/pl011.hh Normal file → Executable file
View File

@@ -135,6 +135,7 @@ class Pl011 : public Uart, public AmbaDevice
static const int UART_RIS = 0x03C;
static const int UART_MIS = 0x040;
static const int UART_ICR = 0x044;
static const int UART_DMACR = 0x048;
static const uint16_t UART_RIINTR = 1 << 0;
static const uint16_t UART_CTSINTR = 1 << 1;