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dev-arm: Added VGIC GICV_IIDR response

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Change-Id: I60e8eadbbbf07c0f8b726213fd580aeb0dd0e00b
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Anouk Van Laer <anouk.vanlaer@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/15278
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
This commit is contained in:
Anouk Van Laer
2018-11-07 14:04:47 +00:00
committed by Giacomo Travaglini
parent 90ed58bcb1
commit 272e4aa26d
2 changed files with 9 additions and 5 deletions
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11
src/dev/arm/vgic.cc
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@@ -1,5 +1,5 @@
/*
* Copyright (c) 2013 ARM Limited
* Copyright (c) 2013,2018 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -47,9 +47,9 @@
#include "mem/packet_access.hh"
VGic::VGic(const Params *p)
: PioDevice(p), platform(p->platform), gic(p->gic), vcpuAddr(p->vcpu_addr),
hvAddr(p->hv_addr), pioDelay(p->pio_delay),
maintInt(p->ppint)
: PioDevice(p), gicvIIDR(p->gicv_iidr), platform(p->platform),
gic(p->gic), vcpuAddr(p->vcpu_addr), hvAddr(p->hv_addr),
pioDelay(p->pio_delay), maintInt(p->ppint)
{
for (int x = 0; x < VGIC_CPU_MAX; x++) {
postVIntEvent[x] = new EventFunctionWrapper(
@@ -127,6 +127,9 @@ VGic::readVCpu(PacketPtr pkt)
lr->VirtualID, lr->CpuID, i, lr->EOI);
}
} break;
case GICV_IIDR:
pkt->setLE<uint32_t>(gicvIIDR);
break;
default:
panic("VGIC VCPU read of bad address %#x\n", daddr);
}

3
src/dev/arm/vgic.hh
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@@ -1,5 +1,5 @@
/*
* Copyright (c) 2013 ARM Limited
* Copyright (c) 2013,2018 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -103,6 +103,7 @@ class VGic : public PioDevice
static const uint32_t LR_PENDING = 1;
static const uint32_t LR_ACTIVE = 2;
const uint32_t gicvIIDR;
/** Post interrupt to CPU */
void processPostVIntEvent(uint32_t cpu);