Commit Graph

16343 Commits

Author SHA1 Message Date
Xiongfei
088c8a224c cpu-minor: this is a bug fix for MinorCPU for thread cloning.
Inside the code of cloneFunc(…)  //syscall_emul.hh

    cp->initState();  //line 1483
    p->clone(tc, ctc, cp, flags);  //line 1484
    …
    ctc->clearArchRegs(); //line 1503

    OS::archClone(flags, p, cp, tc, ctc, newStack, tlsPtr); //line 1505
    …

At line 1483, initState() is called and the activateContext() of the
corresponding MinorCPU is eventually called. The actual architecture
clone happens at line 1505 where PC of the new thread could have a
correct value.

In the existing implementation of MinorCPU::activateContext(ThreadID
thread_id), the below line 275 is called
    pipeline->wakeupFetch(thread_id);
to start fetching instruction with current value of PC, which is 0x0,
leading to panic “Page table fault when accessing virtual address 0”.

This is because the OS::archClone() is not yet called. So, the below bug
fix handles the wakeup fetch for a thread for two scenarios:
   ...
    if (!threads[thread_id]->getUseForClone())
    { //the thread is not cloned
        pipeline->wakeupFetch(thread_id);
    } else {//the thread from clone
        if (fetchEventWrapper != NULL)
            delete fetchEventWrapper;
        fetchEventWrapper = new EventFunctionWrapper([this, thread_id]
          {pipeline->wakeupFetch(thread_id);}, "wakeupFetch");
        schedule(*fetchEventWrapper, clockEdge(Cycles(0)));
    }
    ...
If a thread is not cloned, pipeline->wakeupFetch() is called
immediately.
For the cloned thread, the above bug fix delays the execution of
    pipeline->wakeupFetch()
after the OS::archClone is done. ThreadContext::getUseForClone() return
true if a thread is cloned.

A member variable fetchEventWrapper is added to MinorCPU class for
delayed fetch event.

A member variable useForClone and its corresponding get/set methods are
added to ThreadContext class. This approach allows future reuse of this
useForClone variable by other CPU models if needed and also avoid lots
of changes resulted by modifying parameters of activateContext () and
activate() which are defined as override.

Inside the syscall cloneFunc, the useForClone member of a ThreadContext
object is set via its set method right before Process's initState() is
called, shown as below.
    ctc->setUseForClone(true);
    cp->initState();
    p->clone(tc, ctc, cp, flags);

A few previously failed RISC-V ASM tests have been open in tests.py file
after the bug fix works.

JIRA issue: https://gem5.atlassian.net/browse/GEM5-374

Change-Id: Ibffe46522e2617443d29f49df180692c54830f14
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/37315
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-11-19 02:47:48 +00:00
Gabe Black
7039662eeb x86: Fix object scope in the CPUID code.
The original version of the code takes a pointer from a temporary object
which gets destroyed before the pointer is used.

Change-Id: I16af4eefdf202f769a672e230330d8e0bfce3bb7
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/37695
Reviewed-by: Matthew Poremba <matthew.poremba@amd.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-11-19 01:40:30 +00:00
Bobby R. Bruce
710ff0e99d arch-gcn3,misc: Added missing overrides to gpu_thread.hh
Compiling GCN3 with clang will result in errors within this change.

Change-Id: I05fea6f84f988cb22505281fa24e72d615959f7a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/37538
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Matthew Poremba <matthew.poremba@amd.com>
2020-11-18 18:50:11 +00:00
Gabe Black
9fc5344c0a cpu: Access src and dest reg indexes using a pointer to member.
This will eventually let subclasses provide their own appropriately
sized storage for these indexes. By using a pointer to member instead of
a regular pointer, we ensure that even if the StaticInst is copied/moved
somewhere, it will still find its indexes correctly, without any
additional performance overhead or maintenance.

Unfortunately C++ has decided that arrays with known bounds are not
convertible/compatible with arrays with unknown bounds. I've found at
least two standards proposals in various stages of acceptance which say
that that's dumb and they should change that (because it's dumb and they
should change that), but in the mean time we can get everything to
compile by using the reinterpret_cast hammer. While this is
*technically* undefined behavior, it's basically not and should be
pretty safe.

Change-Id: Id747b0cf68d1a0b4809ebb66a32472187110d7d8
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36876
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
2020-11-18 11:52:24 +00:00
Bobby R. Bruce
95a8cf76a5 arch-gcn3, misc: Added missing override to protocol_tester.hh
Clang will return a missing-override error when compiling X86_GCN4
without this change.

Change-Id: Ib5fd9ba5c27ddc15561198bfc90d27b7599a7923
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/37537
Reviewed-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-11-17 22:46:40 +00:00
Bobby R. Bruce
a1ac9df60a arch-sparc,misc: Added M5_VAR_USED to SparcProcess var
Compiling sparc/gem5.fast fails without specifying this variable is
used.

Change-Id: I86aa5c6495de111421458c2b62200ddb2a89076e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/37536
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-11-17 22:46:40 +00:00
Bobby R. Bruce
20456a4d34 mem-cache,misc: Added missing override to operator
Clang compilation was failing in error due to this missing override.

Change-Id: I92f1774cd2f1f5ef90ab1d72d038f6c65cba70ad
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/37535
Reviewed-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-11-17 22:46:40 +00:00
Gabe Black
7811d01f07 dev: Delete the unused DLAB member in the 8250 UART.
This value is never actually used. The value is computed from the LCR
each time it's needed instead.

Change-Id: I6dc5580eb03174f32b8a381cd2974f742b8eb472
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36817
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-11-17 22:26:06 +00:00
Gabe Black
07c234f0f3 dev: Convert the IDE controller to use the RegisterBank types.
Also get rid of the "ideConfig" register which does not actually show up
in the spec corresponding to this device's PCI IDs.

Change-Id: Id5d109403f49d956c696371b4d93d26150cc96dc
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36816
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-11-17 22:25:56 +00:00
Kyle Roarty
9e1f543407 arch-gcn3: Explicitly sign-extend simm16
In some instructions, simm16 needs to be sign extended. Previous code
simply casted the simm16 to a 32-bit or 64-bit datatype, however this
didn't actually sign-extend the value.

This patch explicitly calls sext<16> on simm16 whenever it's supposed
to be sign-extended.

Change-Id: I32f02e51fbab220d1a73dc7e68c7410937db21c7
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/37495
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Reviewed-by: Matthew Poremba <matthew.poremba@amd.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-11-17 17:08:24 +00:00
Kyle Roarty
a107f62b41 mem-ruby: Fix deadlock in VIPERCoalescer
Certain instructions (some atomics and buffer_wbinvl1_vol) deadlock
in the coalescer, where sendTimingReq fails, fails a retry, and then
never retries again.

This fix sets m_cache_inv_pkt to null before calling
completeHitCallback(), as that allows the failed packets to be retried
again.

Change-Id: I4a51c741360f385f8b4c3f2a31a9410f18e095d9
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/37477
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Reviewed-by: Matthew Poremba <matthew.poremba@amd.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-11-17 17:08:24 +00:00
Kyle Roarty
5f6ebe752e arch-gcn3: Implement flat_load_sbyte instruction
Change-Id: I3aa7547a393b9ecb4b3d4d107394c54d690a0ac2
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/37476
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Reviewed-by: Matthew Poremba <matthew.poremba@amd.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-11-17 17:08:24 +00:00
Kyle Roarty
c1ddd01b66 arch-gcn3: Implement s_setreg_imm32_b32 instruction
Change-Id: I5383243403156dc17d4997106085a62fb0483fec
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/37475
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Reviewed-by: Matthew Poremba <matthew.poremba@amd.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-11-17 17:08:24 +00:00
Jordi Vaquero
b0dbc09b3f arch-arm: Implementation ARMv8.1 RDMA
Adding RDMA implementation for ARMv8.1
    + isa/formats/*: Adding decoding of Aarch64 and aarch32 instructions
    + isa/insts/neon.isa\neon64.isa: Adding function instructions

Change-Id: I430e8880723f373ffffa50079a87fd4ecc634d86
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36015
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-11-17 11:45:35 +00:00
Isaac Sánchez Barrera
caf6a507cb base: Prevent undefined behavior in not interleaved AddrRanges.
If an `AddrRange` is not interleaved, return the input address in
`removeIntlvBits` and `addIntlvBits` to prevent undefined behavior.  It
allows to use these methods in all cases without having to check
manually whether the range is interleaved.

Change-Id: Ic6ac8c4e52b09417bc41aa9380a24319c34e0b35
Signed-off-by: Isaac Sánchez Barrera <isaac.sanchez@bsc.es>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/37617
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
2020-11-17 10:46:30 +00:00
Gabe Black
2f8b5acba1 fastmodel: Wrap the PL330 DMA controller fast model.
Change-Id: I0290e52ede4dca1252ca224abcc85c2c8086ea3c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/37216
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-11-17 06:48:13 +00:00
Daniel Gerzhoy
9a01d3e927 dev-hsa,gpu-compute: Agent Packet handler implemented.
HSA packet processor will now accept and process agent packets.

Type field in packet is command type.
For now:
        AgentCmd::Nop = 0
        AgentCmd::Steal = 1

Steal command steals the completion signal for a running kernel.
This enables a benchmark to use hsa primitives to send an agent
packet to steal the signal, then wait on that signal.

Minimal working example to be added in gem5-resources.

Change-Id: I37f8a4b7ea1780b471559aecbf4af1050353b0b1
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/37015
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Reviewed-by: Matthew Poremba <matthew.poremba@amd.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-11-16 16:12:48 +00:00
Ciro Santilli
a0cff8b945 arch-arm: move serialize and unserialize definition to cpp file
Change-Id: I9ac64184d3fe36617f474a714b228b55b9a90976
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36115
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-11-16 09:16:14 +00:00
Daniel R. Carvalho
833a60a7aa base,cpu,mem: Use templatized SatCounter
Change the deprecated SatCounter instances to the new type-size-
aware SatCounters.

Jira: https://gem5.atlassian.net/browse/GEM5-813

Change-Id: Ie943c553dd8a8c24c80e737783708b033ce001da
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/37095
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
2020-11-14 10:01:43 +00:00
Daniel R. Carvalho
37add2103c base: Templatize SatCounter
Allow SatCounter to have larger unsigned types to accomodate
larger counters.

The template decision was taken because some predictors will
generate huge arrays of small counters, so smaller types will
lessen their overhead; however, isolated counters may require
any counter size.

Jira: https://gem5.atlassian.net/browse/GEM5-813

Change-Id: I5475a565ea7b97d1dfc176fa9d7cf827560fbe39
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/37135
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-11-14 10:01:43 +00:00
Gabe Black
8e34e0b920 scons: Add support for GRPC protobuf files.
These files are used to generate stubs for calling across GRPC
protocols, an RPC mechanism which is based around the protocol buffer
system.

The support for these files is heavily based on and calls into the
existing protobuf file support, but with the extra step which generates
the additional .grpc.pb.cc and .grpc.pb.h files.

Change-Id: I89022928c08aa9f7ed024b7380ddcc54ca75b55e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/37277
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-11-12 22:08:42 +00:00
Gabe Black
6bbdfa370c scons: Convert ProtoBuf to use a scons Builder and Scanner.
There are several benefits to using a Builder. First, the action we're
executing is shared between all uses of the Builder. The number of
times this particular builder is called is small, but it should still
be a little more efficient.

Second, we can use SCons's emitter mechanism to generate the .pb.cc and
.pb.h target files in a little more general way.

Also, this change adds a Scanner for .proto files which will scan them
for imports and let SCons manage those implicit dependencies properly.
The scanner is a bit simplistic as described in a comment in the
source, but should work pretty well in practice with reasonably
formatted files, and in particular some files I'm working with that
include imports.

Change-Id: Iaf2498e61133d6f713d6ccaf199422b882c5894f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/37276
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-11-12 22:08:21 +00:00
Gabe Black
0957ab118c scons: Consolidate the ProtoBuf code.
The ProtoBuf support in src/SConscript was split into two parts, one
where the ProtoBuf sources were declared, and the other where scons was
told how to buld the .cc and .hh files and the .cc was added to the
build.

As far as I can tell, there was no real reason to have things split up
like that, at least not currently. This change moves everything into
the ProtoBuf class definition, and this should behave the same as
before but be a little easier to understand and maintain.

Change-Id: I02320f50ece53d90c14b5062bd6b1167210f46c3
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/37275
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-11-12 22:08:02 +00:00
Gabe Black
598f15cf24 scons: Fix how directories are handled for protobuf files.
There were two issues with how paths were handled for these files.

1. The code in the ProtoBuf class would drop the subdirectory part of
the path name when generating the name of the .cc and .h files the
protoc compiler would output. Since protoc wouldn't generate files
where scons expected, it would fail when it tried to build the .cc.

2. protoc will use the --proto_path and --cpp_out settings to figure
out what path to use for generated files. It will remove the
--proto_path prefix it found the .proto file with from the files path,
and then add the rest to the --cpp_out prefix.

The input files should come from the build directory using symlinks
set up by scons, and the output files should end up alongside them.
That means the --proto_path setting should be the build directory, and
so should --cpp_out. That's fortunately simpler than what was there
before, since it doesn't depend on what the source or targets are.

Change-Id: I69692d2fe3813011982f0c1c9824589a132f93ed
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/37218
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-11-12 22:07:42 +00:00
Gabe Black
760e18e35b mem-cache: Remove "inline" from a method in one of the prefetchers.
The function was defined in a .cc file but marked as inline. gcc seems
to often figure out what it should do, but in clang it doesn't export
the function (since it's marked as inline), and during linking external
references, which don't have a local copy since it's not defined in the
.hh file, will fail.

This failure looks particularly odd because the funciton is virtual,
and so the failure is reported as being unable to compose the vtable
in places where the object is constructed, relatively obscure code
which is generated by the build system and obscured by templates from
an external code base (pybind11).

Change-Id: Ib51aefbf9005e4ca8dfebef32c5def472175f115
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/37436
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-11-12 22:04:42 +00:00
Daniel R. Carvalho
97a766100b mem-cache: Override print function of sector and super blocks
Pass management of printing sector and super block's contents to them.

Change-Id: Ided8d404450a0fa39127ac7d2d6578d95691f509
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36582
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-11-12 21:46:43 +00:00
Daniel R. Carvalho
c8f3ff5e18 mem-cache: Use the compression factor to co-allocate
The compression factor of a block is measured according to the maximum
achievable compression ratio.

For example, if up to 4 blocks can co-allocate in a superblock, and
a cache line has 512 bits, the possible compression factors are 1
(uncompressed, <=512 bits), 2 (compressed, <=256 bits), 4 (compressed,
<=128 bits).

This is an approach similar to the one described in "Yet Another
Compressed Cache", by Sardashti et al.

Change-Id: I52ef36989f3eeef6fc8890132a57f995ef9c5258
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36581
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-11-12 21:46:43 +00:00
Daniel R. Carvalho
90de6ec221 mem-cache: Set compression bit with its size
When setting the size of a compressed block, its compressibility
needs to be recalculated based on that, so move such functionality
to be done after the block has been inserted, within setSizeBits.

As a side effect, insertBlock does not need to be overridden
anymore.

Change-Id: I608f876cd2110ac5e394ffad5b29941ba458ba91
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36580
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-11-12 21:46:43 +00:00
Daniel R. Carvalho
68698e0bfd mem-cache: Add data expansion and compaction checking functions
Data expansion and compaction are determined according to the compaction
method being used. Therefore, do the verification on the blocks instead
of the cache.

Change-Id: I652418a5f4c6d5b946a9925d6287a995f262f02a
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36579
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-11-12 21:46:43 +00:00
Daniel R. Carvalho
f6d2db4b93 mem-cache: Allow moving data contractions
Data contractions happen when a block passes from a less compressed
(e.g., uncompressed) to a more compressed (e.g., compressed) state.

Some compaction methods enforce that a block can only be allocated
in a location matches an exact compression factor, thus on data
contractions such blocks must be moved to another location, or
they must be padded to fake a bigger size.

For compaction methods that do not have that limitation, performance
can be improved if the contracted block is moved to co-allocate with
another existing entry, since it frees up an entry.

Change-Id: I302bc561b897f9d3ce1426331fe4b5c2df76f4b5
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36578
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-11-12 21:46:43 +00:00
Daniel R. Carvalho
a2b7f9544c mem-cache: Use RP for data expansion victimization
When searching for victims of a data expansion a simple approach to
make room for the expanded block is to evict every co-allocatable
block. This, however, ignores replacement policies and tends to be
inefficient. Besides, some cache compaction policies do not allow
blocks that changed their compression ratio to be allocated in the
same location (e.g., Skewed Compressed Caches), so they must be
moved elsewhere.

The replacement policy approach asks the replacement policy which
block(s) would be the best to evict in order to make room for the
expanded block. The other approach, on the other hand, simply evicts
all co-allocated entries. In the case the replacement policy selects
the superblock of the block being expanded, we must make sure the
latter is not evicted/moved by mistake.

This patch also allows the user to select which approach they would
like to use.

Change-Id: Iae57cf26dac7218c51ff0169a5cfcf3d6f8ea28a
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36577
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-11-12 21:46:43 +00:00
Daniel R. Carvalho
f415f27414 mem-cache: Add function to move blocks in the tags
Add a function to allow moving a block's metadata from a source
entry to an invalid destination entry.

Change-Id: I7c8adbcd1133c907f1eea7f69dca983215bc3960
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36576
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-11-12 21:46:43 +00:00
Daniel R. Carvalho
65122a29b6 mem-cache: Add move assign and delete move constr of blk
Some cache techniques may need to move a block's metadata information
into another block. This must have some limitations to avoid mistakes:
- The destination entry must be invalid, otherwise the replacement
  policy steps would be skipped.
- The source entry must be valid, otherwise there would be no point
  in moving their metadata contents.
- The entries locations (set, way, offset...) must not be moved, since
  they are fixed. The same principle is applied to the location specific
  variables, such as the replacement pointer

Why it would be used:
For example, when using compression, and a block goes from uncompressed
to compressed state due to an overwrite, after the tag lookup
(sequential access) it can be decided whether to store the new data in
the old location, or, since we might have already found the block's co-
allocatable blocks, move it to co-allocate.

Other examples of techniques that could use this functionality are
Skewed Compressed Caches, and ZCaches.

Change-Id: I96e4f8cc8c992c4b01f315251d1a75d51c28692c
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36575
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-11-12 21:46:43 +00:00
Bobby R. Bruce
c03462e16c misc: Updated MAINTAINERS.yaml
Change-Id: Ibda441858a22c9e8bb22e132c165e7724aaf7539
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/37356
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Reviewed-by: Matthew Poremba <matthew.poremba@amd.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-11-12 02:08:21 +00:00
Bobby R. Bruce
2aa37d1d77 dev-arm,misc: Added missing override to scmi_platform functions
The missing overrides on the "raiseInterrupt" and "clearInterrupt"
resulted in compilation failures when using Clang.

Change-Id: Ic77e8587cd622f8f0cb819c3230893a1b169a2a2
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/37355
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-11-11 21:03:07 +00:00
Andreas Sandberg
cc9f3649a7 util: Add a library to parse MAINTAINERS.yaml
Add a very simple library to parse MAINTAINERS.yaml. There are
currently no tools that use the library, but it can be tested using
`python3 -m "maint.lib.maintainers"` from within the util directory.

Change-Id: Id2edff94451f27e0b601994d198d0647325e4b35
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/37036
Maintainer: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-11-11 09:50:22 +00:00
Boris Shingarov
eb778327b3 arch-power: Implement mcrxr
Implement the mcrxr instruction (Move to Condition Register from XER
X-form) as defined on p.132 of the green-cloth book:
The contents of XER<0:3> are copied into the Condition Register field
designated by BF.  XER<0:3> are set to zero.

Change-Id: I82ae3d98e1eaf9182e90c0c86afe0f13d4a052e4
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/37295
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Boris Shingarov <shingarov@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-11-10 15:23:14 +00:00
Gabe Black
b12422c79b cpu: Make the NonCachingSimpleCPU use a back door for fetch.
If the memory system can provide a back door to memory, store that, and
use it for subsequent accesses to the range it covers. For now, this
covers only fetch. That's because fetch will generally happen more than
loads and stores, and because it's relatively simple to implement since
we can ignore atomic operations, etc.

Some limitted benchmarking suggests that this speeds up x86 linux boot
by about 20%, although my modifications to the config to remove caching
(which blocks the back door mechanism) also made gem5 crash, so it's
hard to say for sure if that's a valid result. The crash happened in the
same way before and after, so it's probably at least relatively
representative.

While this gives a pretty substantial performance boost, it will prevent
statistics from being collected at the memory, or on intermediate objects
in the interconnect like the bus. That is to be expected with this
memory mode, however.

Change-Id: I73f73017e454300fd4d61f58462eb4ec719b8d85
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36979
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-11-10 13:43:19 +00:00
Matthew Poremba
56a549080f util: Update python version for GCN3
The Python version installed in the Dockerfile for GCN3 by apt-get is
too old to build gem5. This bumps the version to the most recent Python
to avoid needing to update this file too much.

Python 3.9 is install via PPA since it is not available in the official
Ubuntu 16.04 repository. Likewise, pip is installed from "source" as it
is not available for Python 3.9 in from neither the PPA nor Ubuntu.

Change-Id: Ia919f31cf9c9063e1df091cea15590526715739b
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/37219
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Reviewed-by: Daniel Gerzhoy <daniel.gerzhoy@gmail.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-11-09 16:45:33 +00:00
Isaac Sánchez Barrera
5586484344 base: Fix AddrRange::addIntlvBits(Addr) and new test.
The methods `AddrRange::removeIntlvBits(Addr)` and
`AddrRange::addIntlvBits(Addr)` should be the inverse of one another,
but the latter did not insert the blanks for filling the removed bits in
the correct positions.  Since the masks are ordered increasingly by the
position of the least significant bit of each mask, the lowest bit that
has to be inserted at each iteration is always `intlv_bit`, not needing
to be shifted to the left or right.  The bits that need to be copied
from the input address are `intlv_bit-1..0` at each iteration.

The test `AddrRangeTest.AddRemoveInterleavBitsAcrossRange` has been
updated have masks below bit 12, making the old code not pass the test.
A new `AddrRangeTest.AddRemoveInterleavBitsAcrossContiguousRange` test
has been added to include a case in which the previous code fails.  The
corrected code passes both tests.

This function is not used anywhere other than the tests and the class
`ChannelAddr`.  However, it is needed to efficiently implement
interleaved caches in the classic mode.

Change-Id: I7d626a1f6ecf09a230fc18810d2dad2104d1a865
Signed-off-by: Isaac Sánchez Barrera <isaac.sanchez@bsc.es>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/37175
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
2020-11-09 14:50:37 +00:00
Giacomo Travaglini
c306cb071f tests: Add realview64-kvm.py test to quick regressions
By using the valid_host parameter we can make sure the test is
run on a aarch64 host only

Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Change-Id: I3cdb35967e85377f26adf73ad147cb2479162ca1
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31219
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
2020-11-09 09:46:03 +00:00
Giacomo Travaglini
6f64f6f1e2 tests: Add realview64-kvm.py testing platform
Change-Id: If9952563413b4c7462a3ddf46c40358023d5bc60
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31218
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-11-09 09:46:03 +00:00
Giacomo Travaglini
1fa8d0d58c tests: Update guest binaries used by regressions
The new tarball (aarch-system-20200611.tar.bz2) contains the
m5_exit_addr.squashfs.arm64 disk image to be used by KVM regressions

This disk image is based on a memory mapped m5 exit

Change-Id: I23c4a2fa8f969c98dd319cbfa51bca0bcbc9e890
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/37177
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-11-09 09:46:03 +00:00
mupton
9f7d7ac26f arch-x86, kvm: clean up x86 long regresion kvm code
This commit cleans up the code for x86 kvm long regressions.
Somehow the old version went is as the last patchset.
This is the intended code, which should match the last comments.

Change-Id: I9af02a51ce8ed5098887fb0a6b9240db95227bc3
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/37120
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-11-08 01:26:50 +00:00
Kyle Roarty
76ab87c809 arch-x86: include system syscall header in syscall table files
The getdents syscall is only implemented on hosts that define
SYS_getdents, which is located in <sys/syscall.h>.

That header was missed when splitting the syscall tables into their own
files; this patch adds the header to the syscall table files.

Change-Id: I28d54f6ea2874aa533c89ed7520561e19fe5e5f9
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/37195
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Reviewed-by: Matthew Poremba <matthew.poremba@amd.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-11-07 05:44:21 +00:00
Kyle Roarty
e61ef19e83 util: Specify version of rocm-cmake in gcn3 Dockerfile
This patch updates the gcn3 Dockerfile to use the version of rocm-cmake
that MIOpen specifies in its dev-requirements.txt. This fixes a build
conflict with newer versions of rocm-cmake that require a higher version
of SCons than we have in the Dockerfile.

Change-Id: I70887fd91807b77e5015037830cfe96560ac8a31
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/37155
Maintainer: Gabe Black <gabe.black@gmail.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-11-06 18:22:00 +00:00
michaelupton
04b87cc29a arch-x86, cpu-kvm: add x86 kvm test to long regression
revised patch based on reviews

Change-Id: I18d219080ff8ab1c42c9e1a12aadd89606802b25
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34855
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: mike upton <michaelupton@gmail.com>
2020-11-06 18:21:39 +00:00
Andreas Sandberg
92ed623e04 misc: Convert MAINTAINERS to YAML
Convert MAINTAINERS to YAML and rename it to MAINTAINERS.yaml.

Change-Id: I0965b89e7afceb53f6c2a6a183cc1514f5a9d7a0
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/37035
Reviewed-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-11-06 14:38:48 +00:00
Gabe Black
22e27e1d61 mem,sim: Get the page size from the page table in SE mode.
The page table already knows the size of a page without having to
directly use any ISA specific constants.

Change-Id: I68b575e194697065620a2097d972076886766f74
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34172
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Gabe Black <gabe.black@gmail.com>
2020-11-06 08:16:40 +00:00
Gabe Black
5bedc520fe cpu: Style fixes in the AtomicSimpleCPU.
Change-Id: I42391e5a75c55022077f1ef78df97c54fa70f198
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36976
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-11-06 05:54:36 +00:00