Some ISAs (like Arm) have moved most of the translation logic into
the MMU and use the TLB simply as translation storage. It makes
sense to use the MMU debug flag for that logic and reduce the
scope of the TLB flag to TLB insertion/hits/misses
Change-Id: I2a164545c711d83d3e87075b0cb5c279eed274c9
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
This commit is moving some MMU methods definition in the
source file from the header to avoid including tlb.hh
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Change-Id: I8fb1aeccd9c38c48b09583b4dc5d152acd09c3e6
It is a simple enum to distinguish between short and big
descriptors. By moving it away from the ArmFault we can
avoid including fault.hh from mmu.hh
Change-Id: Ib556b577c62f5ea3e4c8c9e0d4560a3e99c96778
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
We are implementing derived classes of SignalSinkPort that does some
additional logic after it's triggered (set() invoked by SignalSourcePort
peer), and before executing the callback that a device provides (in
onChange_). The logic is like additional logging, or providing debugging
features. However, set() itself directly calls the onChange_ callback.
Making the set() virtual could provide the flexibility to achieve this
feature.
This demo board is a preset arm board, that can be used to run example
gem5 simulations. This board doesnt simulate any known hardware.
The board will be used to run benchmarks such as gapbs and npb to
collect stats. The plan is to show these stats on the gem5 resources
website to provide more details about the resources.
1. Implement Zcmp(cm.push, cm.pop, cm.popret, cm.popretz, cm.mva01s,
cm.mvsa01) instructions
2. The Zcd instructions overlap the Zcmp and Zcmt instruction. This
option is used to enable/disable Zcd extension, implies enable Zcmp/Zcmt
extension. If Zcd is enable, the Zcmp and Zcmt is disabled. Otherwise,
Zcmp and Zcmt is enabled.
Spec: https://github.com/riscv/riscv-isa-manual/blob/main/src/zc.adoc
- This change updates syntax of constructors of Template Classes from
`class<T>()` to `class()`
- Initializes coherence to 0 in `src/mem/cache_blk.hh`
The above changes are made to solve the errors when compiling gem5 in
gcc 14
This commit modifies X86DemoBoard so it has numbers more similar to that
of RiscvDemoBoard and ArmDemoBoard. It also adds SE mode to
X86DemoBoard. Note that the changes here depend on the changes in PR
1579.
**Note**: This PR was created so @BobbyRBruce could add his commits to
#1600
---------
Co-authored-by: Erin Le <ejle@ucdavis.edu>
There were a number of variables in the arm and x86 decoders that are
static (e.g., the decode cache). It's a bit interesting that this
doesn't cause problems with multiple cores since each core has its own
decoder.
However, this causes segfaults if you run different cores on different
*host* threads. We are experimenting with running gem5 with multiple
host thread (i.e., in parallel), and removing these static variables
resolves the segfault.
This change also adds const to any other static variables to ensure that
they cannot be modified.
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
The Zcd instructions overlap the Zcmp and Zcmt instruction
This option is used to enable/disable Zcd extension, implies enable
Zcmp/Zcmt extension. If Zcd is enable, the Zcmp and Zcmt is disabled.
Otherwise, Zcmp and Zcmt is enabled.
Spec: https://github.com/riscv/riscv-isa-manual/blob/main/src/zc.adoc#zc-overview
Change-Id: I3788eb6539e13a210c9946efc43ca1fef4639560
There are two issues related to setting an element in PackedReg where
the element spans multiple dwords. First, the mask value is wrong and is
clobbering both dwords. Second, a portion of the value is shifted out of
the narrower input type.
Fix this by using the correct mask to clear the bits where the value
will be placed and use a larger data type to shift the value into place.
* Deprecates the setting of FS/SE mode via the `Simulator` module.
* Moved the creation of the `Root` object from the `Simulator` to the
board.
* Moved the setting of `sim_quantum` from the `Simulator` to the
processor.
* Allows for easier development of boards which support both SE and FS
mode simulation by moving board setup function calls to occur after the
set_workload function is call which sets a boards stats `is_fs` status.
This pops up in kernel 6.8.0. The device it is trying to write is
currently unknown but does not cause problems ignoring the device,
therefore change the panic to a warning and responding to the request
with the default PCI latency.
Change-Id: I4c1229753a75a94a255d8cfd411ac7311283366b
'ext' is set as a Python source path for gem5, like 'src/python'. It
helps vscode users to have vscode aware of this to better analytics and
reduce warnings (most comminly "unable to resolve import).
'tests' isn't in the Python source path when compiling gem5 but it is
when running `tests/main.py`. Though somewhat unideal as is lets vscode
think files in 'src' can import from files in 'test', adding this helps
vscode Python analytics parse the test files which reduces warnings and
aids in betters navigation of the testing code. This is particularly
helpful given the complexity of the testlib testing infrastructure.
With this patch the pannotia tests now:
1. Download the resources to 'gpu-pannotia' in the
'tests/gem5/resources' directory. This is where other test resources are
store.
2. Download thr USA-road-d.NY.gr dataset from Google cloud bucket in a
decompressed state.
2. Avoid re-download the resources if they are already present on the
host machine.
`edited` is what forces a re-run of our tests when the PR title is
updated and other minor metadata stuff. I believe all changes to the
code are covered by the remainder. `synchronize` is means the PR is
triggered with the when the this PR is from (in this case my forked gem5
repo) is synced with the PR branch here. This covers the vast majority
of cases we care about. `opended` covers for the case where the PR is
created and `ready_for_review` for when something moves out of a draft.
Ruby requires each machine type to have a continuous set of version
numbers starting at 0. We were hiding this from users/developers by
using a Python class variable in the stdlib. Unfortunately, with
multiple ruby systems this doesn't work anymore.
As a stop-gap this change adds "resetting" these versions to the
beginning of `incorporate_caches`. It would be better to fix this in the
C++ code (and assign these numbers in C++ probably via the RubySystem),
but that's a bigger change than is needed right now.
---------
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Co-authored-by: pre-commit-ci[bot] <66853113+pre-commit-ci[bot]@users.noreply.github.com>
Add decoder and function of AArch32 VRINTN, VRINTX, VRINTA, VRINTZ,
VRINTM, and VRINTP (Advanced SIMD) instructions. Support both 16-bit and
32-bit variants.
Add vfpFPRint in vfp.hh to perform the behavior of round-to-integer.
Only support A32 encoding.
Change-Id: Icb9b6f71edf16ea14a439e15c480351cd8e1eb88
Add decoder and function of AArch32 VCVTA, VCVTP, VCVTN and VCVTM
instructions. Support both 16-bit and 32-bit variants.
Only support A32 encoding.
Change-Id: I6ece0e1b779f9a7cc9d709894a49a7fdcda28373
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
This PR fixes the bug where simInsts and simOps don't reset when
m5.stats.reset() is called. The stats hostInstRate and hostOpRate are
affected by this change as well, as they depend on simInsts and simOps
respectively.
This is related to issue 1443 linked
[here](https://github.com/gem5/gem5/issues/1443).
This allows vscode to resolve python imported from "src/python".
Warnings regarding these imports are numerous and the issue stops users
of vscode to utilizubg features like navigating the codebase though "Go
to Definition" queries on imported classes/functions.
Previously, whether the board object or the memory_system returned
the memory ports was not consistent in the cache_hierarchies
This commit makes it consistently use the board. Note: the board
is a better place so it can customize the ports (e.g., add I/O
components or other things.
This commit also makes the arm board consistent with the other
boards and removes the specialized `get_mem_ports` that was not
used.
This change allows for the `_setup_memory_range` and `_setup_board`
functions to know if the board is to run a FS or SE workload, thus
allowing for a baord to handle both cases considerably easier than
before. With this change all functions are called after FS or SE
is declared via the `_set_fullsystem` function and thus all can
accomodate for SE and FS workloads.
Where appropriate utilize caching of ALL/gem5.opt or VEGA_X86/gem5.opt.
The cache key is just the date returned by the runner. This is unlikely
the most efficient solution but it is simple and difficulties were
encountered when attempting to create a hash of This solution will do
for now.
The previous https://github.com/gem5/gem5/pull/1617 introduce the CLINT
reset feature. When reset, we changed the mtime to 0 and keep mtimecmp
unchanged by default, we also need to check mtime & mtimecmp regiter to
update the MTI signal. However, the mtime register will be incremented
to 1 by `raiseInterruptPin`.
In the PR, we introduced the interrupt ID for CLINT, the mtime will be
incremented only if received the RTC signal
---------
Co-authored-by: Jason Lowe-Power <jason@lowepower.com>
There are several parts to this PR to work towards #1349 .
(1) Make RubySystem::getBlockSizeBytes non-static by providing ways to
access the block size or passing the block size explicitly to classes.
The main changes are:
- DataBlocks must be explicitly allocated. A default ctor still exists
to avoid needing to heavily modify SLICC. The size can be set using a
realloc function, operator=, or copy ctor. This is handled completely
transparently meaning no protocol or config changes are required.
- WriteMask now requires block size to be set. This is also handled
transparently by modifying the SLICC parser to identify WriteMask
types and call setBlockSize().
- AbstractCacheEntry and TBE classes now require block size to be set.
This is handled transparently by modifying the SLICC parser to
identify these classes and call initBlockSize() which calls
setBlockSize() for any DataBlock or WriteMask.
- All AbstractControllers now have a pointer to RubySystem. This is
assigned in SLICC generated code and requires no changes to protocol
or configs.
- The Ruby Message class now requires block size in all constructors.
This is added to the argument list automatically by the SLICC parser.
(2) Relax dependence on common functions in
src/mem/ruby/common/Address.hh
so that RubySystem::getBlockSizeBits is no longer static. Many classes
already have a way to get block size from the previous commit, so they
simply multiple by 8 to get the number of bits. For handling SLICC and
reducing the number of changes, define makeCacheLine, getOffset, etc. in
RubyPort and AbstractController. The only protocol changes required are
to change any "RubySystem::foo()" calls with "m_ruby_system->foo()".
For classes which do not have a way to get access to block size but
still used makeLineAddress, getOffset, etc., the block size must be
passed to that class. This requires some changes to the SimObject
interface for two commonly used classes: DirectoryMemory and
RubyPrefecther, resulting in user-facing API changes
User-facing API changes:
- DirectoryMemory and RubyPrefetcher now require the cache line size as
a non-optional argument.
- RubySequencer SimObjects now require RubySystem as a non-optional
argument.
- TesterThread in the GPU ruby tester now requires the cache line size
as a non-optional argument.
(3) Removes static member variables in RubySystem which control
randomization, cooldown, and warmup. These are mostly used by the Ruby
Network. The network classes are modified to take these former static
variables as parameters which are passed to the corresponding method
(e.g., enqueue, delayHead, etc.) rather than needing a RubySystem object
at all.
Change-Id: Ia63c2ad5cf0bf9d1cbdffba5d3a679bb4d3b1220
(4) There are two major SLICC generated static methods:
getNumControllers()
on each cache controller which returns the number of controllers created
by the configs at run time and the functions which access this method,
which are MachineType_base_count and MachineType_base_number. These need
to be removed to create multiple RubySystem objects otherwise NetDest,
version value, and other objects are incorrect.
To remove the static requirement, MachineType_base_count and
MachineType_base_number are moved to RubySystem. Any class which needs
to call these methods must now have a pointer to a RubySystem. To enable
that, several changes are made:
- RubyRequest and Message now require a RubySystem pointer in the
constructor. The pointer is passed to fields in the Message class
which require a RubySystem pointer (e.g., NetDest). SLICC is modified
to do this automatically.
- SLICC structures may now optionally take an "implicit constructor"
which can be used to call a non-default constructor for locally
defined variables (e.g., temporary variables within SLICC actions). A
statement such as "NetDest bcast_dest;" in SLICC will implicitly
append a call to the NetDest constructor taking RubySystem, for
example.
- RubySystem gets passed to Ruby network objects (Network, Topology).
There was a bug exposed by a recent PR [1] where until recently the O3
CPU was executing an instruction even if it did not have the required
functional unit in the FU pool.
We are adding the matrix descriptors to the Default FU pool in the O3
cpu so that no panic is encountered upon executing of a matrix
instruction
[1]: https://github.com/gem5/gem5/pull/1516
Change-Id: I04250255a2cbb2ee6f3ef204b62bc2c1ee2d4d2c
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
There was a bug exposed by a recent PR [1] where until recently the O3
CPU was executing an instruction even if it did not have the required
functional unit in the FU pool.
We are adding the crypto descriptors to the Default FU pool in the O3
cpu so that no panic is encountered upon executing of a crypto
instruction
[1]: https://github.com/gem5/gem5/pull/1516
Change-Id: Ifaf2f8e4780dfb8ba825a99a02dd587f011dbd23
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
The Daily tests have been failing as the learning-gem5 Ruby test now
exits at tick 9831 instead of tick 9981.
**Note**: The cause of this change is currently unknown. I'm not sure if
this is symptomatic of something bigger but for now I only observe this
bug failure and this patch at least silences the error.
