arch-arm: Add support of AArch32 VCVTA/P/N/M instructions. (#1533)
Add decoder and function of AArch32 VCVTA, VCVTP, VCVTN and VCVTM instructions. Support both 16-bit and 32-bit variants. Only support A32 encoding. Change-Id: I6ece0e1b779f9a7cc9d709894a49a7fdcda28373 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
This commit is contained in:
Giacomo Travaglini
@@ -1,6 +1,6 @@
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// -*- mode:c++ -*-
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// Copyright (c) 2010-2011, 2016-2019 ARM Limited
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// Copyright (c) 2010-2011, 2016-2019, 2024 ARM Limited
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// All rights reserved
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//
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// The license below extends only to copyright in the software and shall
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@@ -1891,6 +1891,150 @@ let {{
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return new NVrsqrteD<uint32_t>(machInst, vd, vm);
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}
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}
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} else if ((b & 0x1c) == 0x00) {
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if (bits(b, 1)) {
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switch(size) {
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case 1:
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if (q) {
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return new NVcvt2uhAQ<uint16_t>(machInst, vd, vm);
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} else {
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return new NVcvt2uhAD<uint16_t>(machInst, vd, vm);
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}
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case 2:
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if (q) {
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return new NVcvt2usAQ<uint32_t>(machInst, vd, vm);
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} else {
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return new NVcvt2usAD<uint32_t>(machInst, vd, vm);
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}
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default:
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return new Unknown(machInst);
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}
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} else {
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switch (size) {
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case 0b01:
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if (q) {
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return new NVcvt2shAQ<int16_t>(machInst, vd, vm);
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} else {
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return new NVcvt2shAD<int16_t>(machInst, vd, vm);
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}
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case 0b10:
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if (q) {
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return new NVcvt2ssAQ<int32_t>(machInst, vd, vm);
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} else {
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return new NVcvt2ssAD<int32_t>(machInst, vd, vm);
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}
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default:
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return new Unknown(machInst);
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}
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}
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} else if ((b & 0x1c) == 0x04) {
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if (bits(b, 1)) {
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switch (size) {
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case 0b01:
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if (q) {
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return new NVcvt2uhNQ<uint16_t>(machInst, vd, vm);
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} else {
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return new NVcvt2uhND<uint16_t>(machInst, vd, vm);
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}
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case 0b10:
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if (q) {
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return new NVcvt2usNQ<uint32_t>(machInst, vd, vm);
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} else {
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return new NVcvt2usND<uint32_t>(machInst, vd, vm);
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}
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default:
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return new Unknown(machInst);
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}
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} else {
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switch (size) {
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case 0b01:
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if (q) {
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return new NVcvt2shNQ<int16_t>(machInst, vd, vm);
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} else {
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return new NVcvt2shND<int16_t>(machInst, vd, vm);
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}
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case 0b10:
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if (q) {
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return new NVcvt2ssNQ<int32_t>(machInst, vd, vm);
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} else {
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return new NVcvt2ssND<int32_t>(machInst, vd, vm);
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}
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default:
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return new Unknown(machInst);
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}
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}
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} else if ((b & 0x1c) == 0x08) {
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if (bits(b, 1)) {
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switch (size) {
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case 0b01:
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if (q) {
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return new NVcvt2uhPQ<uint16_t>(machInst, vd, vm);
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} else {
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return new NVcvt2uhPD<uint16_t>(machInst, vd, vm);
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}
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case 0b10:
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if (q) {
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return new NVcvt2usPQ<uint32_t>(machInst, vd, vm);
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} else {
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return new NVcvt2usPD<uint32_t>(machInst, vd, vm);
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}
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default:
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return new Unknown(machInst);
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}
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} else {
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switch (size) {
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case 0b01:
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if (q) {
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return new NVcvt2shPQ<int16_t>(machInst, vd, vm);
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} else {
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return new NVcvt2shPD<int16_t>(machInst, vd, vm);
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}
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case 0b10:
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if (q) {
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return new NVcvt2ssPQ<int32_t>(machInst, vd, vm);
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} else {
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return new NVcvt2ssPD<int32_t>(machInst, vd, vm);
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}
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default:
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return new Unknown(machInst);
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}
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}
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} else if ((b & 0x1c) == 0x0c) {
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if (bits(b, 1)) {
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switch (size) {
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case 0b01:
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if (q) {
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return new NVcvt2uhMQ<uint16_t>(machInst, vd, vm);
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} else {
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return new NVcvt2uhMD<uint16_t>(machInst, vd, vm);
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}
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case 0b10:
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if (q) {
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return new NVcvt2usMQ<uint32_t>(machInst, vd, vm);
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} else {
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return new NVcvt2usMD<uint32_t>(machInst, vd, vm);
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}
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default:
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return new Unknown(machInst);
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}
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} else {
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switch (size) {
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case 0b01:
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if (q) {
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return new NVcvt2shMQ<int16_t>(machInst, vd, vm);
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} else {
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return new NVcvt2shMD<int16_t>(machInst, vd, vm);
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}
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case 0b10:
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if (q) {
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return new NVcvt2ssMQ<int32_t>(machInst, vd, vm);
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} else {
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return new NVcvt2ssMD<int32_t>(machInst, vd, vm);
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}
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default:
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return new Unknown(machInst);
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}
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}
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} else {
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return new Unknown(machInst);
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}
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@@ -1,6 +1,6 @@
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// -*- mode:c++ -*-
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// Copyright (c) 2010-2011, 2015, 2019 ARM Limited
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// Copyright (c) 2010-2011, 2015, 2019, 2024 ARM Limited
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// All rights reserved
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//
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// The license below extends only to copyright in the software and shall
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@@ -3579,6 +3579,128 @@ let {{
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'''
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twoRegLongMiscInst("vcvt", "NVcvth2s", "SimdCvtOp", ("uint16_t",), vcvth2sCode)
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vcvthp2hCode = '''
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FPSCR fpscr = (FPSCR) FpscrExc;
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VfpSavedState state = prepFpState(fpscr.rMode);
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__asm__ __volatile__("" : "=m" (srcElem1) : "m" (srcElem1));
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float mid = vcvtFpHFpS(fpscr, fpscr.dn, fpscr.ahp, srcElem1);
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if (flushToZero(mid))
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fpscr.idc = 1;
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destElem = vfpFpToFixed<float>(mid, %s, 16, 0, true, %s);
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__asm__ __volatile__("" :: "m" (destElem));
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finishVfp(fpscr, state, true);
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FpscrExc = fpscr;
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'''
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vcvtahp2uhCode = vcvthp2hCode % ("false", "VfpRoundAway")
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twoRegMiscInst("vcvta.u16.f16", "NVcvt2uhAD", "SimdCvtOp",
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("uint16_t",), 2, vcvtahp2uhCode)
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twoRegMiscInst("vcvta.u16.f16", "NVcvt2uhAQ", "SimdCvtOp",
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("uint16_t",), 4, vcvtahp2uhCode)
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vcvtnhp2uhCode = vcvthp2hCode % ("false", "VfpRoundNearest")
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twoRegMiscInst("vcvtn.u16.f16", "NVcvt2uhND", "SimdCvtOp",
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("uint16_t",), 2, vcvtnhp2uhCode)
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twoRegMiscInst("vcvtn.u16.f16", "NVcvt2uhNQ", "SimdCvtOp",
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("uint16_t",), 4, vcvtnhp2uhCode)
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vcvtphp2uhCode = vcvthp2hCode % ("false", "VfpRoundUpward")
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twoRegMiscInst("vcvtp.u16.f16", "NVcvt2uhPD", "SimdCvtOp",
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("uint16_t",), 2, vcvtphp2uhCode)
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twoRegMiscInst("vcvtp.u16.f16", "NVcvt2uhPQ", "SimdCvtOp",
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("uint16_t",), 4, vcvtphp2uhCode)
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vcvtmhp2uhCode = vcvthp2hCode % ("false", "VfpRoundDown")
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twoRegMiscInst("vcvtm.u16.f16", "NVcvt2uhMD", "SimdCvtOp",
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("uint16_t",), 2, vcvtmhp2uhCode)
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twoRegMiscInst("vcvtm.u16.f16", "NVcvt2uhMQ", "SimdCvtOp",
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("uint16_t",), 4, vcvtmhp2uhCode)
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vcvtahp2shCode = vcvthp2hCode % ("true", "VfpRoundAway")
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twoRegMiscInst("vcvta.s16.f16", "NVcvt2shAD", "SimdCvtOp",
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("int16_t",), 2, vcvtahp2shCode)
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twoRegMiscInst("vcvta.s16.f16", "NVcvt2shAQ", "SimdCvtOp",
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("int16_t",), 4, vcvtahp2shCode)
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vcvtnhp2shCode = vcvthp2hCode % ("true", "VfpRoundNearest")
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twoRegMiscInst("vcvtn.s16.f16", "NVcvt2shND", "SimdCvtOp",
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("int16_t",), 2, vcvtnhp2shCode)
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twoRegMiscInst("vcvtn.s16.f16", "NVcvt2shNQ", "SimdCvtOp",
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("int16_t",), 4, vcvtnhp2shCode)
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vcvtphp2shCode = vcvthp2hCode % ("true", "VfpRoundUpward")
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twoRegMiscInst("vcvtp.s16.f16", "NVcvt2shPD", "SimdCvtOp",
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("int16_t",), 2, vcvtphp2shCode)
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twoRegMiscInst("vcvtp.s16.f16", "NVcvt2shPQ", "SimdCvtOp",
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("int16_t",), 4, vcvtphp2shCode)
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vcvtmhp2shCode = vcvthp2hCode % ("true", "VfpRoundDown")
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twoRegMiscInst("vcvtm.s16.f16", "NVcvt2shMD", "SimdCvtOp",
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("int16_t",), 2, vcvtmhp2shCode)
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twoRegMiscInst("vcvtm.s16.f16", "NVcvt2shMQ", "SimdCvtOp",
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("int16_t",), 4, vcvtmhp2shCode)
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vcvtsp2sCode = '''
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FPSCR fpscr = (FPSCR) FpscrExc;
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VfpSavedState state = prepFpState(fpscr.rMode);
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__asm__ __volatile__("" : "=m" (srcElem1) : "m" (srcElem1));
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float mid = bitsToFp(srcElem1, (float)0.0);
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if (flushToZero(mid))
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fpscr.idc = 1;
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destElem = vfpFpToFixed<float>(mid, %s, 32, 0, true, %s);
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__asm__ __volatile__("" :: "m" (destElem));
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finishVfp(fpscr, state, true);
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FpscrExc = fpscr;
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'''
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vcvtasp2usCode = vcvtsp2sCode % ("false", "VfpRoundAway")
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twoRegMiscInst("vcvta.u32.f32", "NVcvt2usAD", "SimdCvtOp",
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("uint32_t",), 2, vcvtasp2usCode)
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twoRegMiscInst("vcvta.u32.f32", "NVcvt2usAQ", "SimdCvtOp",
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("uint32_t",), 4, vcvtasp2usCode)
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vcvtnsp2usCode = vcvtsp2sCode % ("false", "VfpRoundNearest")
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twoRegMiscInst("vcvtn.u32.f32", "NVcvt2usND", "SimdCvtOp",
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("uint32_t",), 2, vcvtnsp2usCode)
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twoRegMiscInst("vcvtn.u32.f32", "NVcvt2usNQ", "SimdCvtOp",
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("uint32_t",), 4, vcvtnsp2usCode)
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vcvtpsp2usCode = vcvtsp2sCode % ("false", "VfpRoundUpward")
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twoRegMiscInst("vcvtp.u32.f32", "NVcvt2usPD", "SimdCvtOp",
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("uint32_t",), 2, vcvtpsp2usCode)
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twoRegMiscInst("vcvtp.u32.f32", "NVcvt2usPQ", "SimdCvtOp",
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("uint32_t",), 4, vcvtpsp2usCode)
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vcvtmsp2usCode = vcvtsp2sCode % ("false", "VfpRoundDown")
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twoRegMiscInst("vcvtm.u32.f32", "NVcvt2usMD", "SimdCvtOp",
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("uint32_t",), 2, vcvtmsp2usCode)
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twoRegMiscInst("vcvtm.u32.f32", "NVcvt2usMQ", "SimdCvtOp",
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("uint32_t",), 4, vcvtmsp2usCode)
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vcvtasp2ssCode = vcvtsp2sCode % ("true", "VfpRoundAway")
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twoRegMiscInst("vcvta.s32.f32", "NVcvt2ssAD", "SimdCvtOp",
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("int32_t",), 2, vcvtasp2ssCode)
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twoRegMiscInst("vcvta.s32.f32", "NVcvt2ssAQ", "SimdCvtOp",
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("int32_t",), 4, vcvtasp2ssCode)
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vcvtnsp2ssCode = vcvtsp2sCode % ("true", "VfpRoundNearest")
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twoRegMiscInst("vcvtn.s32.f32", "NVcvt2ssND", "SimdCvtOp",
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("int32_t",), 2, vcvtnsp2ssCode)
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twoRegMiscInst("vcvtn.s32.f32", "NVcvt2ssNQ", "SimdCvtOp",
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("int32_t",), 4, vcvtnsp2ssCode)
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vcvtpsp2ssCode = vcvtsp2sCode % ("true", "VfpRoundUpward")
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twoRegMiscInst("vcvtp.s32.f32", "NVcvt2ssPD", "SimdCvtOp",
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("int32_t",), 2, vcvtpsp2ssCode)
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twoRegMiscInst("vcvtp.s32.f32", "NVcvt2ssPQ", "SimdCvtOp",
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("int32_t",), 4, vcvtpsp2ssCode)
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vcvtmsp2ssCode = vcvtsp2sCode % ("true", "VfpRoundDown")
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twoRegMiscInst("vcvtm.s32.f32", "NVcvt2ssMD", "SimdCvtOp",
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("int32_t",), 2, vcvtmsp2ssCode)
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twoRegMiscInst("vcvtm.s32.f32", "NVcvt2ssMQ", "SimdCvtOp",
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("int32_t",), 4, vcvtmsp2ssCode)
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vrsqrteCode = '''
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destElem = unsignedRSqrtEstimate(srcElem1);
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'''
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