[pre-commit.ci] auto fixes from pre-commit.com hooks

for more information, see https://pre-commit.ci

configs/common/HMC.py

@@ -568,9 +568,9 @@ def config_hmc_dev(opt, system, hmc_host):
     # Attach 4 serial link to 4 crossbar/s
     for i in range(opt.num_serial_links):
         if opt.enable_link_monitor:
-            system.hmc_host.seriallink[
-                i
-            ].mem_side_port = system.hmc_dev.lmonitor[i].cpu_side_port
+            system.hmc_host.seriallink[i].mem_side_port = (
+                system.hmc_dev.lmonitor[i].cpu_side_port
+            )
             system.hmc_dev.lmonitor[i].mem_side_port = system.hmc_dev.xbar[
                 i
             ].cpu_side_ports
@@ -613,14 +613,12 @@ def config_hmc_dev(opt, system, hmc_host):
                     ]
 
                     # Connect the bridge between corssbars
-                    system.hmc_dev.xbar[
-                        i
-                    ].mem_side_ports = system.hmc_dev.buffers[
-                        index
-                    ].cpu_side_port
-                    system.hmc_dev.buffers[
-                        index
-                    ].mem_side_port = system.hmc_dev.xbar[j].cpu_side_ports
+                    system.hmc_dev.xbar[i].mem_side_ports = (
+                        system.hmc_dev.buffers[index].cpu_side_port
+                    )
+                    system.hmc_dev.buffers[index].mem_side_port = (
+                        system.hmc_dev.xbar[j].cpu_side_ports
+                    )
                 else:
                     # Don't connect the xbar to itself
                     pass
@@ -629,49 +627,49 @@ def config_hmc_dev(opt, system, hmc_host):
     # can only direct traffic to it local vaults
     if opt.arch == "mixed":
         system.hmc_dev.buffer30 = Bridge(ranges=system.mem_ranges[0:4])
-        system.hmc_dev.xbar[
-            3
-        ].mem_side_ports = system.hmc_dev.buffer30.cpu_side_port
+        system.hmc_dev.xbar[3].mem_side_ports = (
+            system.hmc_dev.buffer30.cpu_side_port
+        )
         system.hmc_dev.buffer30.mem_side_port = system.hmc_dev.xbar[
             0
         ].cpu_side_ports
 
         system.hmc_dev.buffer31 = Bridge(ranges=system.mem_ranges[4:8])
-        system.hmc_dev.xbar[
-            3
-        ].mem_side_ports = system.hmc_dev.buffer31.cpu_side_port
+        system.hmc_dev.xbar[3].mem_side_ports = (
+            system.hmc_dev.buffer31.cpu_side_port
+        )
         system.hmc_dev.buffer31.mem_side_port = system.hmc_dev.xbar[
             1
         ].cpu_side_ports
 
         system.hmc_dev.buffer32 = Bridge(ranges=system.mem_ranges[8:12])
-        system.hmc_dev.xbar[
-            3
-        ].mem_side_ports = system.hmc_dev.buffer32.cpu_side_port
+        system.hmc_dev.xbar[3].mem_side_ports = (
+            system.hmc_dev.buffer32.cpu_side_port
+        )
         system.hmc_dev.buffer32.mem_side_port = system.hmc_dev.xbar[
             2
         ].cpu_side_ports
 
         system.hmc_dev.buffer20 = Bridge(ranges=system.mem_ranges[0:4])
-        system.hmc_dev.xbar[
-            2
-        ].mem_side_ports = system.hmc_dev.buffer20.cpu_side_port
+        system.hmc_dev.xbar[2].mem_side_ports = (
+            system.hmc_dev.buffer20.cpu_side_port
+        )
         system.hmc_dev.buffer20.mem_side_port = system.hmc_dev.xbar[
             0
         ].cpu_side_ports
 
         system.hmc_dev.buffer21 = Bridge(ranges=system.mem_ranges[4:8])
-        system.hmc_dev.xbar[
-            2
-        ].mem_side_ports = system.hmc_dev.buffer21.cpu_side_port
+        system.hmc_dev.xbar[2].mem_side_ports = (
+            system.hmc_dev.buffer21.cpu_side_port
+        )
         system.hmc_dev.buffer21.mem_side_port = system.hmc_dev.xbar[
             1
         ].cpu_side_ports
 
         system.hmc_dev.buffer23 = Bridge(ranges=system.mem_ranges[12:16])
-        system.hmc_dev.xbar[
-            2
-        ].mem_side_ports = system.hmc_dev.buffer23.cpu_side_port
+        system.hmc_dev.xbar[2].mem_side_ports = (
+            system.hmc_dev.buffer23.cpu_side_port
+        )
         system.hmc_dev.buffer23.mem_side_port = system.hmc_dev.xbar[
             3
         ].cpu_side_ports

configs/common/Simulation.py

@@ -541,9 +541,9 @@ def run(options, root, testsys, cpu_class):
                 IndirectBPClass = ObjectList.indirect_bp_list.get(
                     options.indirect_bp_type
                 )
-                switch_cpus[
-                    i
-                ].branchPred.indirectBranchPred = IndirectBPClass()
+                switch_cpus[i].branchPred.indirectBranchPred = (
+                    IndirectBPClass()
+                )
             switch_cpus[i].createThreads()
 
         # If elastic tracing is enabled attach the elastic trace probe

configs/deprecated/example/fs.py

@@ -213,9 +213,9 @@ def build_test_system(np, isa: ISA):
                     IndirectBPClass = ObjectList.indirect_bp_list.get(
                         args.indirect_bp_type
                     )
-                    test_sys.cpu[
-                        i
-                    ].branchPred.indirectBranchPred = IndirectBPClass()
+                    test_sys.cpu[i].branchPred.indirectBranchPred = (
+                        IndirectBPClass()
+                    )
             test_sys.cpu[i].createThreads()
 
         # If elastic tracing is enabled when not restoring from checkpoint and

configs/example/apu_se.py

@@ -935,9 +935,9 @@ gpu_port_idx = gpu_port_idx - args.num_cp * 2
 token_port_idx = 0
 for i in range(len(system.ruby._cpu_ports)):
     if isinstance(system.ruby._cpu_ports[i], VIPERCoalescer):
-        system.cpu[shader_idx].CUs[
-            token_port_idx
-        ].gmTokenPort = system.ruby._cpu_ports[i].gmTokenPort
+        system.cpu[shader_idx].CUs[token_port_idx].gmTokenPort = (
+            system.ruby._cpu_ports[i].gmTokenPort
+        )
         token_port_idx += 1
 
 wavefront_size = args.wf_size

configs/example/gpufs/system/system.py

@@ -336,9 +336,9 @@ def makeGpuFSSystem(args):
     token_port_idx = 0
     for i in range(len(system.ruby._cpu_ports)):
         if isinstance(system.ruby._cpu_ports[i], VIPERCoalescer):
-            system.cpu[shader_idx].CUs[
-                token_port_idx
-            ].gmTokenPort = system.ruby._cpu_ports[i].gmTokenPort
+            system.cpu[shader_idx].CUs[token_port_idx].gmTokenPort = (
+                system.ruby._cpu_ports[i].gmTokenPort
+            )
             token_port_idx += 1
 
     wavefront_size = args.wf_size
@@ -346,9 +346,9 @@ def makeGpuFSSystem(args):
         # The pipeline issues wavefront_size number of uncoalesced requests
         # in one GPU issue cycle. Hence wavefront_size mem ports.
         for j in range(wavefront_size):
-            system.cpu[shader_idx].CUs[i].memory_port[
-                j
-            ] = system.ruby._cpu_ports[gpu_port_idx].in_ports[j]
+            system.cpu[shader_idx].CUs[i].memory_port[j] = (
+                system.ruby._cpu_ports[gpu_port_idx].in_ports[j]
+            )
         gpu_port_idx += 1
 
     for i in range(args.num_compute_units):

configs/example/read_config.py

@@ -250,9 +250,11 @@ class ConfigManager:
                         obj,
                         param_name,
                         [
-                            self.objects_by_name[name]
-                            if name != "Null"
-                            else m5.params.NULL
+                            (
+                                self.objects_by_name[name]
+                                if name != "Null"
+                                else m5.params.NULL
+                            )
                             for name in param_values
                         ],
                     )

src/arch/isa_parser/isa_parser.py

@@ -111,11 +111,12 @@ class Template:
 
             operands = SubOperandList(self.parser, compositeCode, d.operands)
 
-            myDict[
-                "reg_idx_arr_decl"
-            ] = "RegId srcRegIdxArr[%d]; RegId destRegIdxArr[%d]" % (
-                d.operands.numSrcRegs + d.srcRegIdxPadding,
-                d.operands.numDestRegs + d.destRegIdxPadding,
+            myDict["reg_idx_arr_decl"] = (
+                "RegId srcRegIdxArr[%d]; RegId destRegIdxArr[%d]"
+                % (
+                    d.operands.numSrcRegs + d.srcRegIdxPadding,
+                    d.operands.numDestRegs + d.destRegIdxPadding,
+                )
             )
 
             # The reinterpret casts are largely because an array with a known
@@ -821,7 +822,7 @@ class ISAParser(Grammar):
         "DBLCOLON",
         "ASTERISK",
         # C preprocessor directives
-        "CPPDIRECTIVE"
+        "CPPDIRECTIVE",
         # The following are matched but never returned. commented out to
         # suppress PLY warning
         # newfile directive

src/arch/micro_asm.py

@@ -140,9 +140,9 @@ def handle_statement(parser, container, statement):
     if statement.is_microop:
         if statement.mnemonic not in parser.microops.keys():
             raise Exception(f"Unrecognized mnemonic: {statement.mnemonic}")
-        parser.symbols[
-            "__microopClassFromInsideTheAssembler"
-        ] = parser.microops[statement.mnemonic]
+        parser.symbols["__microopClassFromInsideTheAssembler"] = (
+            parser.microops[statement.mnemonic]
+        )
         try:
             microop = eval(
                 f"__microopClassFromInsideTheAssembler({statement.params})",
@@ -166,9 +166,9 @@ def handle_statement(parser, container, statement):
     elif statement.is_directive:
         if statement.name not in container.directives.keys():
             raise Exception(f"Unrecognized directive: {statement.name}")
-        parser.symbols[
-            "__directiveFunctionFromInsideTheAssembler"
-        ] = container.directives[statement.name]
+        parser.symbols["__directiveFunctionFromInsideTheAssembler"] = (
+            container.directives[statement.name]
+        )
         try:
             eval(
                 f"__directiveFunctionFromInsideTheAssembler({statement.params})",

src/python/gem5/components/boards/abstract_system_board.py

@@ -36,7 +36,6 @@ from .abstract_board import AbstractBoard
 
 
 class AbstractSystemBoard(System, AbstractBoard):
-
     """
     An abstract board for cases where boards should inherit from System.
     """

src/python/gem5/components/boards/test_board.py

@@ -44,7 +44,6 @@ from .abstract_system_board import AbstractSystemBoard
 
 
 class TestBoard(AbstractSystemBoard):
-
     """This is a Testing Board used to run traffic generators on a simple
     architecture.
 

tests/gem5/stats/configs/pystat_vector2d_check.py

@@ -138,9 +138,11 @@ for x in range(args.num_vectors):
 
     vectors[x_index] = {
         "type": "Vector",
-        "description": stat_tester.subdescs[x]
-        if x in stat_tester.subdescs
-        else stat_tester.description,
+        "description": (
+            stat_tester.subdescs[x]
+            if x in stat_tester.subdescs
+            else stat_tester.description
+        ),
         "value": vector,
     }
 

util/minorview/model.py

@@ -374,9 +374,9 @@ class TwoDColours(ColourPattern):
 
                 for index, value in parsed:
                     try:
-                        array[index % strips][
-                            index / strips
-                        ] = special_view_decoder(elemClass)(value)
+                        array[index % strips][index / strips] = (
+                            special_view_decoder(elemClass)(value)
+                        )
                     except:
                         print(
                             "Element out of range strips: %d,"
@@ -912,9 +912,9 @@ class BlobModel:
                         blobs = self.unitNameToBlobs.get(unit, [])
                         for blob in blobs:
                             if blob.visualDecoder is not None:
-                                event.visuals[
-                                    blob.picChar
-                                ] = blob.visualDecoder(pairs)
+                                event.visuals[blob.picChar] = (
+                                    blob.visualDecoder(pairs)
+                                )
 
                         self.add_unit_event(event)
                         last_time_lines[unit] = rest