misc: Run pre-commit run --all-files

This ensures `isort` is applied to all files in the repo.

Change-Id: Ib7ced1c924ef1639542bf0d1a01c5737f6ba43e9

build_tools/cxx_config_cc.py

@@ -43,7 +43,6 @@ import os.path
 import sys
 
 import importer
-
 from code_formatter import code_formatter
 
 parser = argparse.ArgumentParser()
@@ -59,8 +58,8 @@ importer.install()
 module = importlib.import_module(args.modpath)
 sim_object = getattr(module, sim_object_name)
 
-from m5.params import isSimObjectClass
 import m5.params
+from m5.params import isSimObjectClass
 
 code = code_formatter()
 

build_tools/cxx_config_hh.py

@@ -42,7 +42,6 @@ import os.path
 import sys
 
 import importer
-
 from code_formatter import code_formatter
 
 parser = argparse.ArgumentParser()

build_tools/enum_cc.py

@@ -42,7 +42,6 @@ import os.path
 import sys
 
 import importer
-
 from code_formatter import code_formatter
 
 parser = argparse.ArgumentParser()

build_tools/enum_hh.py

@@ -42,7 +42,6 @@ import os.path
 import sys
 
 import importer
-
 from code_formatter import code_formatter
 
 parser = argparse.ArgumentParser()

build_tools/sim_object_param_struct_cc.py

@@ -42,7 +42,6 @@ import os.path
 import sys
 
 import importer
-
 from code_formatter import code_formatter
 
 parser = argparse.ArgumentParser()

build_tools/sim_object_param_struct_hh.py

@@ -42,7 +42,6 @@ import os.path
 import sys
 
 import importer
-
 from code_formatter import code_formatter
 
 parser = argparse.ArgumentParser()

configs/common/Benchmarks.py

@@ -24,8 +24,14 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
-from common.SysPaths import script, disk, binary
 from os import environ as env
+
+from common.SysPaths import (
+    binary,
+    disk,
+    script,
+)
+
 from m5.defines import buildEnv
 
 

configs/common/CacheConfig.py

@@ -40,14 +40,15 @@
 # Configure the M5 cache hierarchy config in one place
 #
 
+from common import ObjectList
+from common.Caches import *
+
 import m5
 from m5.objects import *
+
 from gem5.isas import ISA
 from gem5.runtime import get_runtime_isa
 
-from common.Caches import *
-from common import ObjectList
-
 
 def _get_hwp(hwp_option):
     if hwp_option == None:

configs/common/Caches.py

@@ -39,6 +39,7 @@
 
 from m5.defines import buildEnv
 from m5.objects import *
+
 from gem5.isas import ISA
 from gem5.runtime import get_runtime_isa
 

configs/common/CpuConfig.py

@@ -33,8 +33,8 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
-from m5 import fatal
 import m5.objects
+from m5 import fatal
 
 
 def config_etrace(cpu_cls, cpu_list, options):

configs/common/FSConfig.py

@@ -38,12 +38,13 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
+from common import ObjectList
+from common.Benchmarks import *
+
 import m5
 import m5.defines
 from m5.objects import *
 from m5.util import *
-from common.Benchmarks import *
-from common import ObjectList
 
 # Populate to reflect supported os types per target ISA
 os_types = set()

configs/common/FileSystemConfig.py

@@ -36,18 +36,31 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
+import getpass
+import operator
+import os
+import platform
+from functools import reduce
+from os import (
+    access,
+    getpid,
+    listdir,
+    makedirs,
+    mkdir,
+    stat,
+)
+from os.path import isdir
+from os.path import join as joinpath
+from pwd import getpwuid
+from shutil import (
+    copyfile,
+    rmtree,
+)
+
 import m5
 from m5.objects import *
 from m5.util.convert import *
 
-from functools import reduce
-import operator, os, platform, getpass
-from os import mkdir, makedirs, getpid, listdir, stat, access
-from pwd import getpwuid
-from os.path import join as joinpath
-from os.path import isdir
-from shutil import rmtree, copyfile
-
 
 def hex_mask(terms):
     dec_mask = reduce(operator.or_, [2**i for i in terms], 0)

configs/common/MemConfig.py

@@ -33,9 +33,12 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
+from common import (
+    HMC,
+    ObjectList,
+)
+
 import m5.objects
-from common import ObjectList
-from common import HMC
 
 
 def create_mem_intf(intf, r, i, intlv_bits, intlv_size, xor_low_bit):
@@ -174,6 +177,7 @@ def config_mem(options, system):
     nbr_mem_ctrls = opt_mem_channels
 
     import math
+
     from m5.util import fatal
 
     intlv_bits = int(math.log(nbr_mem_ctrls, 2))

configs/common/ObjectList.py

@@ -34,13 +34,15 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
-from gem5.runtime import get_supported_isas
-import m5.objects
-import m5.internal.params
 import inspect
 import sys
 from textwrap import TextWrapper
 
+import m5.internal.params
+import m5.objects
+
+from gem5.runtime import get_supported_isas
+
 
 class ObjectList:
     """Creates a list of objects that are sub-classes of a given class."""

configs/common/Options.py

@@ -38,13 +38,13 @@
 
 import argparse
 
+from common import ObjectList
+from common.Benchmarks import *
+
 import m5
 from m5.defines import buildEnv
 from m5.objects import *
 
-from common.Benchmarks import *
-from common import ObjectList
-
 vio_9p_help = """\
 Enable the Virtio 9P device and set the path to share. The default 9p path is
 m5ou5/9p/share, and it can be changed by setting VirtIO9p.root with --param. A

configs/common/SimpleOpts.py

@@ -34,12 +34,12 @@ from each class instead of only from the configuration script.
 # Module-level variable to track if we've called the parse_args function yet
 called_parse_args = False
 
-# For fatal
-import m5
-
 # import the argument parser
 from argparse import ArgumentParser
 
+# For fatal
+import m5
+
 # add the args we want to be able to control from the command line
 parser = ArgumentParser()
 

configs/common/Simulation.py

@@ -41,8 +41,10 @@ import sys
 from os import getcwd
 from os.path import join as joinpath
 
-from common import CpuConfig
+from common import (
-from common import ObjectList
+    CpuConfig,
+    ObjectList,
+)
 
 import m5
 from m5.defines import buildEnv
@@ -128,9 +130,12 @@ def findCptDir(options, cptdir, testsys):
     the appropriate directory.
     """
 
-    from os.path import isdir, exists
-    from os import listdir
     import re
+    from os import listdir
+    from os.path import (
+        exists,
+        isdir,
+    )
 
     if not isdir(cptdir):
         fatal("checkpoint dir %s does not exist!", cptdir)

configs/common/SysPaths.py

@@ -24,7 +24,8 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
-import os, sys
+import os
+import sys
 
 config_path = os.path.dirname(os.path.abspath(__file__))
 config_root = os.path.dirname(config_path)

configs/common/cores/arm/O3_ARM_Etrace.py

@@ -34,6 +34,7 @@
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
 from m5.objects import *
+
 from .O3_ARM_v7a import O3_ARM_v7a_3
 
 

configs/common/cores/arm/__init__.py

@@ -33,8 +33,8 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
-from pkgutil import iter_modules
 from importlib import import_module
+from pkgutil import iter_modules
 
 _cpu_modules = [name for _, name, ispkg in iter_modules(__path__) if not ispkg]
 

configs/common/cpu2000.py

@@ -26,8 +26,15 @@
 
 import os
 import sys
-from os.path import basename, exists, join as joinpath, normpath
+from os.path import (
-from os.path import isdir, isfile, islink
+    basename,
+    exists,
+    isdir,
+    isfile,
+    islink,
+)
+from os.path import join as joinpath
+from os.path import normpath
 
 spec_dist = os.environ.get("M5_CPU2000", "/dist/m5/cpu2000")
 

configs/deprecated/example/fs.py

@@ -45,25 +45,31 @@ import sys
 import m5
 from m5.defines import buildEnv
 from m5.objects import *
-from m5.util import addToPath, fatal, warn
+from m5.util import (
+    addToPath,
+    fatal,
+    warn,
+)
 from m5.util.fdthelper import *
+
 from gem5.isas import ISA
 from gem5.runtime import get_runtime_isa
 
 addToPath("../../")
 
-from ruby import Ruby
+from common import (
-
+    CacheConfig,
+    CpuConfig,
+    MemConfig,
+    ObjectList,
+    Options,
+    Simulation,
+)
+from common.Benchmarks import *
+from common.Caches import *
 from common.FSConfig import *
 from common.SysPaths import *
-from common.Benchmarks import *
+from ruby import Ruby
-from common import Simulation
-from common import CacheConfig
-from common import CpuConfig
-from common import MemConfig
-from common import ObjectList
-from common.Caches import *
-from common import Options
 
 
 def cmd_line_template():

configs/deprecated/example/se.py

@@ -41,30 +41,36 @@
 # "m5 test.py"
 
 import argparse
-import sys
 import os
+import sys
 
 import m5
 from m5.defines import buildEnv
 from m5.objects import *
 from m5.params import NULL
-from m5.util import addToPath, fatal, warn
+from m5.util import (
+    addToPath,
+    fatal,
+    warn,
+)
+
 from gem5.isas import ISA
 from gem5.runtime import get_runtime_isa
 
 addToPath("../../")
 
-from ruby import Ruby
+from common import (
-
+    CacheConfig,
-from common import Options
+    CpuConfig,
-from common import Simulation
+    MemConfig,
-from common import CacheConfig
+    ObjectList,
-from common import CpuConfig
+    Options,
-from common import ObjectList
+    Simulation,
-from common import MemConfig
+)
-from common.FileSystemConfig import config_filesystem
 from common.Caches import *
 from common.cpu2000 import *
+from common.FileSystemConfig import config_filesystem
+from ruby import Ruby
 
 
 def get_processes(args):

configs/dram/lat_mem_rd.py

@@ -33,18 +33,20 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
-import gzip
 import argparse
+import gzip
 import os
 
 import m5
 from m5.objects import *
-from m5.util import addToPath
 from m5.stats import periodicStatDump
+from m5.util import addToPath
 
 addToPath("../")
-from common import ObjectList
+from common import (
-from common import MemConfig
+    MemConfig,
+    ObjectList,
+)
 
 addToPath("../../util")
 import protolib

configs/dram/low_power_sweep.py

@@ -37,13 +37,15 @@ import argparse
 
 import m5
 from m5.objects import *
-from m5.util import addToPath
 from m5.stats import periodicStatDump
+from m5.util import addToPath
 
 addToPath("../")
 
-from common import ObjectList
+from common import (
-from common import MemConfig
+    MemConfig,
+    ObjectList,
+)
 
 # This script aims at triggering low power state transitions in the DRAM
 # controller. The traffic generator is used in DRAM mode and traffic

configs/dram/sweep.py

@@ -33,18 +33,20 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
-import math
 import argparse
+import math
 
 import m5
 from m5.objects import *
-from m5.util import addToPath
 from m5.stats import periodicStatDump
+from m5.util import addToPath
 
 addToPath("../")
 
-from common import ObjectList
+from common import (
-from common import MemConfig
+    MemConfig,
+    ObjectList,
+)
 
 # this script is helpful to sweep the efficiency of a specific memory
 # controller configuration, by varying the number of banks accessed,

configs/example/apu_se.py

@@ -27,28 +27,32 @@
 # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
 # POSSIBILITY OF SUCH DAMAGE.
 
-import argparse, os, re, getpass
+import argparse
-import math
+import getpass
 import glob
 import inspect
+import math
+import os
+import re
 
 import m5
 from m5.objects import *
 from m5.util import addToPath
+
 from gem5.isas import ISA
 from gem5.runtime import get_runtime_isa
 
 addToPath("../")
 
-from ruby import Ruby
-
-from common import Options
-from common import Simulation
-from common import GPUTLBOptions, GPUTLBConfig
-
 import hsaTopology
-from common import FileSystemConfig
+from common import (
-
+    FileSystemConfig,
+    GPUTLBConfig,
+    GPUTLBOptions,
+    Options,
+    Simulation,
+)
+from ruby import Ruby
 
 # Adding script options
 parser = argparse.ArgumentParser()

configs/example/arm/baremetal.py

@@ -39,24 +39,29 @@ Research Starter Kit on System Modeling. More information can be found
 at: http://www.arm.com/ResearchEnablement/SystemModeling
 """
 
+import argparse
 import os
+
 import m5
-from m5.util import addToPath
 from m5.objects import *
 from m5.options import *
+from m5.util import addToPath
+
 from gem5.simulate.exit_event import ExitEvent
-import argparse
 
 m5.util.addToPath("../..")
 
-from common import SysPaths
-from common import MemConfig
-from common import ObjectList
-from common.cores.arm import HPI
-from common.cores.arm import O3_ARM_v7a
-
 import devices
 import workloads
+from common import (
+    MemConfig,
+    ObjectList,
+    SysPaths,
+)
+from common.cores.arm import (
+    HPI,
+    O3_ARM_v7a,
+)
 
 # Pre-defined CPU configurations. Each tuple must be ordered as : (cpu_class,
 # l1_icache_class, l1_dcache_class, walk_cache_class, l2_Cache_class). Any of

configs/example/arm/devices.py

@@ -39,8 +39,8 @@ import m5
 from m5.objects import *
 
 m5.util.addToPath("../../")
-from common.Caches import *
 from common import ObjectList
+from common.Caches import *
 
 have_kvm = "ArmV8KvmCPU" in ObjectList.cpu_list.get_names()
 have_fastmodel = "FastModelCortexA76" in ObjectList.cpu_list.get_names()

configs/example/arm/dist_bigLITTLE.py

@@ -39,11 +39,11 @@
 import argparse
 import os
 
+import fs_bigLITTLE as bL
+
 import m5
 from m5.objects import *
 
-import fs_bigLITTLE as bL
-
 m5.util.addToPath("../../dist")
 import sw
 

configs/example/arm/etrace_se.py

@@ -34,18 +34,18 @@
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
 
-import os
-import m5
-from m5.util import addToPath
-from m5.objects import *
 import argparse
+import os
 import shlex
 
+import m5
+from m5.objects import *
+from m5.util import addToPath
+
 m5.util.addToPath("../..")
 
-from common import ObjectList
-
 import devices
+from common import ObjectList
 
 
 def get_processes(cmd):

configs/example/arm/fs_bigLITTLE.py

@@ -39,21 +39,29 @@
 import argparse
 import os
 import sys
+
 import m5
 import m5.util
 from m5.objects import *
 
 m5.util.addToPath("../../")
 
-from common import FSConfig
-from common import SysPaths
-from common import ObjectList
-from common import Options
-from common.cores.arm import ex5_big, ex5_LITTLE
-
 import devices
-from devices import AtomicCluster, KvmCluster, FastmodelCluster
+from common import (
-
+    FSConfig,
+    ObjectList,
+    Options,
+    SysPaths,
+)
+from common.cores.arm import (
+    ex5_big,
+    ex5_LITTLE,
+)
+from devices import (
+    AtomicCluster,
+    FastmodelCluster,
+    KvmCluster,
+)
 
 default_disk = "aarch64-ubuntu-trusty-headless.img"
 
@@ -410,7 +418,8 @@ def build(options):
         system.generateDtb(system.workload.dtb_filename)
 
     if devices.have_fastmodel and issubclass(big_model, FastmodelCluster):
-        from m5 import arm_fast_model as fm, systemc as sc
+        from m5 import arm_fast_model as fm
+        from m5 import systemc as sc
 
         # setup FastModels for simulation
         fm.setup_simulation("cortexa76")

configs/example/arm/fs_power.py

@@ -39,11 +39,14 @@
 import argparse
 import os
 
-import m5
-from m5.objects import MathExprPowerModel, PowerModel
-
 import fs_bigLITTLE as bL
 
+import m5
+from m5.objects import (
+    MathExprPowerModel,
+    PowerModel,
+)
+
 
 class CpuPowerOn(MathExprPowerModel):
     def __init__(self, cpu_path, **kwargs):

configs/example/arm/ruby_fs.py

@@ -33,24 +33,28 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
+import argparse
 import os
+
 import m5
-from m5.util import addToPath
 from m5.objects import *
 from m5.options import *
-import argparse
+from m5.util import addToPath
 
 m5.util.addToPath("../..")
 
-from common import MemConfig
-from common import ObjectList
-from common import Options
-from common import SysPaths
-from common.cores.arm import O3_ARM_v7a, HPI
-from ruby import Ruby
-
 import devices
-
+from common import (
+    MemConfig,
+    ObjectList,
+    Options,
+    SysPaths,
+)
+from common.cores.arm import (
+    HPI,
+    O3_ARM_v7a,
+)
+from ruby import Ruby
 
 default_kernel = "vmlinux.arm64"
 default_disk = "linaro-minimal-aarch64.img"

configs/example/arm/starter_fs.py

@@ -38,22 +38,26 @@ Research Starter Kit on System Modeling. More information can be found
 at: http://www.arm.com/ResearchEnablement/SystemModeling
 """
 
+import argparse
 import os
+
 import m5
-from m5.util import addToPath
 from m5.objects import *
 from m5.options import *
-import argparse
+from m5.util import addToPath
 
 m5.util.addToPath("../..")
 
-from common import SysPaths
-from common import ObjectList
-from common import MemConfig
-from common.cores.arm import O3_ARM_v7a, HPI
-
 import devices
-
+from common import (
+    MemConfig,
+    ObjectList,
+    SysPaths,
+)
+from common.cores.arm import (
+    HPI,
+    O3_ARM_v7a,
+)
 
 default_kernel = "vmlinux.arm64"
 default_disk = "linaro-minimal-aarch64.img"

configs/example/arm/starter_se.py

@@ -38,21 +38,22 @@ Research Starter Kit on System Modeling. More information can be found
 at: http://www.arm.com/ResearchEnablement/SystemModeling
 """
 
-import os
-import m5
-from m5.util import addToPath
-from m5.objects import *
 import argparse
+import os
 import shlex
 
+import m5
+from m5.objects import *
+from m5.util import addToPath
+
 m5.util.addToPath("../..")
 
-from common import ObjectList
-from common import MemConfig
-from common.cores.arm import HPI
-
 import devices
-
+from common import (
+    MemConfig,
+    ObjectList,
+)
+from common.cores.arm import HPI
 
 # Pre-defined CPU configurations. Each tuple must be ordered as : (cpu_class,
 # l1_icache_class, l1_dcache_class, walk_cache_class, l2_Cache_class). Any of

configs/example/arm/workloads.py

@@ -35,13 +35,17 @@
 #
 
 import inspect
+
+from common.ObjectList import ObjectList
+from common.SysPaths import (
+    binary,
+    disk,
+)
+
 import m5
 from m5.objects import *
 from m5.options import *
 
-from common.ObjectList import ObjectList
-from common.SysPaths import binary, disk
-
 
 class ArmBaremetal(ArmFsWorkload):
     """Baremetal workload"""

configs/example/dramsys.py

@@ -25,7 +25,6 @@
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
 import m5
-
 from m5.objects import *
 
 traffic_gen = PyTrafficGen()

configs/example/etrace_replay.py

@@ -37,13 +37,18 @@
 
 import argparse
 
-from m5.util import addToPath, fatal
+from m5.util import (
+    addToPath,
+    fatal,
+)
 
 addToPath("../")
 
-from common import Options
+from common import (
-from common import Simulation
+    MemConfig,
-from common import MemConfig
+    Options,
+    Simulation,
+)
 from common.Caches import *
 
 

configs/example/garnet_synth_traffic.py

@@ -26,11 +26,14 @@
 #
 # Author: Tushar Krishna
 
+import argparse
+import os
+import sys
+
 import m5
-from m5.objects import *
 from m5.defines import buildEnv
+from m5.objects import *
 from m5.util import addToPath
-import os, argparse, sys
 
 addToPath("../")
 

configs/example/gem5_library/arm-hello.py

@@ -41,15 +41,15 @@ scons build/ARM/gem5.opt
 ```
 """
 
-from gem5.isas import ISA
-from gem5.utils.requires import requires
-from gem5.resources.resource import obtain_resource
-from gem5.components.memory import SingleChannelDDR3_1600
-from gem5.components.processors.cpu_types import CPUTypes
 from gem5.components.boards.simple_board import SimpleBoard
 from gem5.components.cachehierarchies.classic.no_cache import NoCache
+from gem5.components.memory import SingleChannelDDR3_1600
+from gem5.components.processors.cpu_types import CPUTypes
 from gem5.components.processors.simple_processor import SimpleProcessor
+from gem5.isas import ISA
+from gem5.resources.resource import obtain_resource
 from gem5.simulate.simulator import Simulator
+from gem5.utils.requires import requires
 
 # This check ensures the gem5 binary is compiled to the ARM ISA target. If not,
 # an exception will be thrown.

configs/example/gem5_library/arm-ubuntu-run.py

@@ -40,18 +40,20 @@ scons build/ARM/gem5.opt -j<NUM_CPUS>
 
 """
 
-from gem5.isas import ISA
+from m5.objects import (
-from m5.objects import ArmDefaultRelease
+    ArmDefaultRelease,
-from gem5.utils.requires import requires
+    VExpress_GEM5_Foundation,
-from gem5.resources.resource import obtain_resource
+)
-from gem5.simulate.simulator import Simulator
+
-from m5.objects import VExpress_GEM5_Foundation
 from gem5.coherence_protocol import CoherenceProtocol
 from gem5.components.boards.arm_board import ArmBoard
 from gem5.components.memory import DualChannelDDR4_2400
 from gem5.components.processors.cpu_types import CPUTypes
 from gem5.components.processors.simple_processor import SimpleProcessor
-
+from gem5.isas import ISA
+from gem5.resources.resource import obtain_resource
+from gem5.simulate.simulator import Simulator
+from gem5.utils.requires import requires
 
 # This runs a check to ensure the gem5 binary is compiled for ARM and the
 # protocol is CHI.

configs/example/gem5_library/caches/octopi-cache-example.py

@@ -38,20 +38,23 @@ scons build/ARM_MESI_Three_Level/gem5.opt -j `nproc`
 """
 
 
-from m5.objects import ArmDefaultRelease, VExpress_GEM5_Foundation
+from m5.objects import (
+    ArmDefaultRelease,
+    VExpress_GEM5_Foundation,
+)
 
-from gem5.utils.requires import requires
+from gem5.coherence_protocol import CoherenceProtocol
 from gem5.components.boards.arm_board import ArmBoard
-from gem5.components.memory import DualChannelDDR4_2400
-from gem5.components.processors.simple_processor import SimpleProcessor
-from gem5.components.processors.cpu_types import CPUTypes
 from gem5.components.cachehierarchies.ruby.caches.mesi_three_level.octopi import (
     OctopiCache,
 )
+from gem5.components.memory import DualChannelDDR4_2400
+from gem5.components.processors.cpu_types import CPUTypes
+from gem5.components.processors.simple_processor import SimpleProcessor
 from gem5.isas import ISA
-from gem5.coherence_protocol import CoherenceProtocol
-from gem5.simulate.simulator import Simulator
 from gem5.resources.resource import obtain_resource
+from gem5.simulate.simulator import Simulator
+from gem5.utils.requires import requires
 
 num_ccds = 1  # CCDs
 num_cores_per_ccd = 8  # 8 cores/CCD

configs/example/gem5_library/checkpoints/riscv-hello-restore-checkpoint.py

@@ -46,15 +46,15 @@ scons build/RISCV/gem5.opt
 ```
 """
 
-from gem5.isas import ISA
-from gem5.utils.requires import requires
-from gem5.resources.resource import obtain_resource
-from gem5.components.memory import SingleChannelDDR3_1600
-from gem5.components.processors.cpu_types import CPUTypes
 from gem5.components.boards.simple_board import SimpleBoard
 from gem5.components.cachehierarchies.classic.no_cache import NoCache
+from gem5.components.memory import SingleChannelDDR3_1600
+from gem5.components.processors.cpu_types import CPUTypes
 from gem5.components.processors.simple_processor import SimpleProcessor
+from gem5.isas import ISA
+from gem5.resources.resource import obtain_resource
 from gem5.simulate.simulator import Simulator
+from gem5.utils.requires import requires
 
 # This check ensures the gem5 binary is compiled to the RISCV ISA target.
 # If not, an exception will be thrown.

configs/example/gem5_library/checkpoints/riscv-hello-save-checkpoint.py

@@ -44,15 +44,16 @@ scons build/RISCV/gem5.opt
 """
 
 import argparse
-from gem5.isas import ISA
+
-from gem5.utils.requires import requires
-from gem5.resources.resource import obtain_resource
-from gem5.components.memory import SingleChannelDDR3_1600
-from gem5.components.processors.cpu_types import CPUTypes
 from gem5.components.boards.simple_board import SimpleBoard
 from gem5.components.cachehierarchies.classic.no_cache import NoCache
+from gem5.components.memory import SingleChannelDDR3_1600
+from gem5.components.processors.cpu_types import CPUTypes
 from gem5.components.processors.simple_processor import SimpleProcessor
+from gem5.isas import ISA
+from gem5.resources.resource import obtain_resource
 from gem5.simulate.simulator import Simulator
+from gem5.utils.requires import requires
 
 parser = argparse.ArgumentParser()
 

configs/example/gem5_library/checkpoints/simpoints-se-checkpoint.py

@@ -48,22 +48,23 @@ scons build/X86/gem5.opt
 """
 
 import argparse
+from pathlib import Path
 
+from gem5.components.boards.simple_board import SimpleBoard
+from gem5.components.cachehierarchies.classic.no_cache import NoCache
+from gem5.components.memory.single_channel import SingleChannelDDR3_1600
+from gem5.components.processors.cpu_types import CPUTypes
+from gem5.components.processors.simple_processor import SimpleProcessor
+from gem5.isas import ISA
+from gem5.resources.resource import (
+    SimpointResource,
+    obtain_resource,
+)
+from gem5.resources.workload import Workload
 from gem5.simulate.exit_event import ExitEvent
+from gem5.simulate.exit_event_generators import save_checkpoint_generator
 from gem5.simulate.simulator import Simulator
 from gem5.utils.requires import requires
-from gem5.components.boards.simple_board import SimpleBoard
-from gem5.components.memory.single_channel import SingleChannelDDR3_1600
-from gem5.components.processors.simple_processor import SimpleProcessor
-from gem5.components.processors.cpu_types import CPUTypes
-from gem5.isas import ISA
-from gem5.resources.workload import Workload
-from gem5.resources.resource import obtain_resource, SimpointResource
-from pathlib import Path
-from gem5.components.cachehierarchies.classic.no_cache import NoCache
-from gem5.simulate.exit_event_generators import (
-    save_checkpoint_generator,
-)
 
 requires(isa_required=ISA.X86)
 

configs/example/gem5_library/checkpoints/simpoints-se-restore.py

@@ -52,23 +52,29 @@ scons build/X86/gem5.opt
 
 """
 
-from gem5.simulate.exit_event import ExitEvent
+from pathlib import Path
-from gem5.simulate.simulator import Simulator
+
-from gem5.utils.requires import requires
+from m5.stats import (
+    dump,
+    reset,
+)
+
+from gem5.components.boards.simple_board import SimpleBoard
 from gem5.components.cachehierarchies.classic.private_l1_private_l2_cache_hierarchy import (
     PrivateL1PrivateL2CacheHierarchy,
 )
-from gem5.components.boards.simple_board import SimpleBoard
 from gem5.components.memory import DualChannelDDR4_2400
-from gem5.components.processors.simple_processor import SimpleProcessor
 from gem5.components.processors.cpu_types import CPUTypes
+from gem5.components.processors.simple_processor import SimpleProcessor
 from gem5.isas import ISA
-from gem5.resources.resource import SimpointResource, obtain_resource
+from gem5.resources.resource import (
+    SimpointResource,
+    obtain_resource,
+)
 from gem5.resources.workload import Workload
-from gem5.resources.resource import SimpointResource
+from gem5.simulate.exit_event import ExitEvent
-
+from gem5.simulate.simulator import Simulator
-from pathlib import Path
+from gem5.utils.requires import requires
-from m5.stats import reset, dump
 
 requires(isa_required=ISA.X86)
 

configs/example/gem5_library/dramsys/arm-hello-dramsys.py

@@ -33,17 +33,17 @@ DRRAMSys simulator. Please consult 'ext/dramsys/README' on how to compile
 correctly. If this is not done correctly this script will run with error.
 """
 
-from gem5.isas import ISA
-from gem5.utils.requires import requires
-from gem5.resources.resource import obtain_resource
-from gem5.components.memory import DRAMSysDDR3_1600
-from gem5.components.processors.cpu_types import CPUTypes
 from gem5.components.boards.simple_board import SimpleBoard
 from gem5.components.cachehierarchies.classic.private_l1_cache_hierarchy import (
     PrivateL1CacheHierarchy,
 )
+from gem5.components.memory import DRAMSysDDR3_1600
+from gem5.components.processors.cpu_types import CPUTypes
 from gem5.components.processors.simple_processor import SimpleProcessor
+from gem5.isas import ISA
+from gem5.resources.resource import obtain_resource
 from gem5.simulate.simulator import Simulator
+from gem5.utils.requires import requires
 
 # This check ensures the gem5 binary is compiled to the ARM ISA target. If not,
 # an exception will be thrown.

configs/example/gem5_library/dramsys/dramsys-traffic.py

@@ -32,8 +32,8 @@ DRRAMSys simulator. Please consult 'ext/dramsys/README' on how to compile
 correctly. If this is not done correctly this script will run with error.
 """
 
-from gem5.components.memory.dramsys import DRAMSysMem
 from gem5.components.boards.test_board import TestBoard
+from gem5.components.memory.dramsys import DRAMSysMem
 from gem5.components.processors.linear_generator import LinearGenerator
 from gem5.simulate.simulator import Simulator
 

configs/example/gem5_library/looppoints/create-looppoint-checkpoints.py

@@ -47,22 +47,22 @@ scons build/X86/gem5.opt
 ```
 """
 
-from gem5.simulate.exit_event import ExitEvent
+import argparse
-from gem5.simulate.simulator import Simulator
+from pathlib import Path
-from gem5.utils.requires import requires
+
-from gem5.components.cachehierarchies.classic.no_cache import NoCache
 from gem5.components.boards.simple_board import SimpleBoard
+from gem5.components.cachehierarchies.classic.no_cache import NoCache
 from gem5.components.memory.single_channel import SingleChannelDDR3_1600
-from gem5.components.processors.simple_processor import SimpleProcessor
 from gem5.components.processors.cpu_types import CPUTypes
+from gem5.components.processors.simple_processor import SimpleProcessor
 from gem5.isas import ISA
 from gem5.resources.resource import obtain_resource
-from pathlib import Path
+from gem5.simulate.exit_event import ExitEvent
 from gem5.simulate.exit_event_generators import (
     looppoint_save_checkpoint_generator,
 )
-
+from gem5.simulate.simulator import Simulator
-import argparse
+from gem5.utils.requires import requires
 
 requires(isa_required=ISA.X86)
 

configs/example/gem5_library/looppoints/restore-looppoint-checkpoint.py

@@ -42,19 +42,23 @@ Usage
 """
 import argparse
 
-from gem5.simulate.exit_event import ExitEvent
+from m5.stats import (
-from gem5.simulate.simulator import Simulator
+    dump,
-from gem5.utils.requires import requires
+    reset,
+)
+
+from gem5.components.boards.simple_board import SimpleBoard
 from gem5.components.cachehierarchies.classic.private_l1_private_l2_cache_hierarchy import (
     PrivateL1PrivateL2CacheHierarchy,
 )
-from gem5.components.boards.simple_board import SimpleBoard
 from gem5.components.memory import DualChannelDDR4_2400
-from gem5.components.processors.simple_processor import SimpleProcessor
 from gem5.components.processors.cpu_types import CPUTypes
+from gem5.components.processors.simple_processor import SimpleProcessor
 from gem5.isas import ISA
 from gem5.resources.resource import obtain_resource
-from m5.stats import reset, dump
+from gem5.simulate.exit_event import ExitEvent
+from gem5.simulate.simulator import Simulator
+from gem5.utils.requires import requires
 
 requires(isa_required=ISA.X86)
 

configs/example/gem5_library/memory_traffic.py

@@ -36,14 +36,12 @@ and this channel is driven with 32GiB/s of traffic for 1ms.
 import argparse
 
 from m5.objects import MemorySize
-from gem5.components.boards.test_board import TestBoard
 
+from gem5.components.boards.test_board import TestBoard
+from gem5.components.memory.dram_interfaces.hbm import HBM_2000_4H_1x64
+from gem5.components.memory.hbm import HighBandwidthMemory
 from gem5.components.processors.linear_generator import LinearGenerator
 from gem5.components.processors.random_generator import RandomGenerator
-
-from gem5.components.memory.hbm import HighBandwidthMemory
-from gem5.components.memory.dram_interfaces.hbm import HBM_2000_4H_1x64
-
 from gem5.simulate.simulator import Simulator
 
 

configs/example/gem5_library/power-hello.py

@@ -41,15 +41,15 @@ scons build/POWER/gem5.opt
 ```
 """
 
-from gem5.isas import ISA
-from gem5.utils.requires import requires
-from gem5.resources.resource import obtain_resource
-from gem5.components.memory import SingleChannelDDR4_2400
-from gem5.components.processors.cpu_types import CPUTypes
 from gem5.components.boards.simple_board import SimpleBoard
 from gem5.components.cachehierarchies.classic.no_cache import NoCache
+from gem5.components.memory import SingleChannelDDR4_2400
+from gem5.components.processors.cpu_types import CPUTypes
 from gem5.components.processors.simple_processor import SimpleProcessor
+from gem5.isas import ISA
+from gem5.resources.resource import obtain_resource
 from gem5.simulate.simulator import Simulator
+from gem5.utils.requires import requires
 
 # This check ensures the gem5 binary is compiled to the POWER ISA target.
 # If not, an exception will be thrown.

configs/example/gem5_library/riscv-fs.py

@@ -40,16 +40,16 @@ Characteristics
 """
 
 from gem5.components.boards.riscv_board import RiscvBoard
-from gem5.components.memory import SingleChannelDDR3_1600
-from gem5.components.processors.simple_processor import SimpleProcessor
 from gem5.components.cachehierarchies.classic.private_l1_private_l2_cache_hierarchy import (
     PrivateL1PrivateL2CacheHierarchy,
 )
+from gem5.components.memory import SingleChannelDDR3_1600
 from gem5.components.processors.cpu_types import CPUTypes
+from gem5.components.processors.simple_processor import SimpleProcessor
 from gem5.isas import ISA
-from gem5.utils.requires import requires
 from gem5.resources.resource import obtain_resource
 from gem5.simulate.simulator import Simulator
+from gem5.utils.requires import requires
 
 # Run a check to ensure the right version of gem5 is being used.
 requires(isa_required=ISA.RISCV)

configs/example/gem5_library/riscv-ubuntu-run.py

@@ -43,14 +43,14 @@ scons build/RISCV/gem5.opt
 import m5
 from m5.objects import Root
 
-from gem5.utils.requires import requires
 from gem5.components.boards.riscv_board import RiscvBoard
 from gem5.components.memory import DualChannelDDR4_2400
-from gem5.components.processors.simple_processor import SimpleProcessor
 from gem5.components.processors.cpu_types import CPUTypes
+from gem5.components.processors.simple_processor import SimpleProcessor
 from gem5.isas import ISA
-from gem5.simulate.simulator import Simulator
 from gem5.resources.resource import obtain_resource
+from gem5.simulate.simulator import Simulator
+from gem5.utils.requires import requires
 
 # This runs a check to ensure the gem5 binary is compiled for RISCV.
 

configs/example/gem5_library/riscvmatched-fs.py

@@ -38,14 +38,14 @@ scons build/RISCV/gem5.opt
 ```
 """
 
-from gem5.prebuilt.riscvmatched.riscvmatched_board import RISCVMatchedBoard
-from gem5.utils.requires import requires
-from gem5.isas import ISA
-from gem5.simulate.simulator import Simulator
-from gem5.resources.resource import obtain_resource
-
 import argparse
 
+from gem5.isas import ISA
+from gem5.prebuilt.riscvmatched.riscvmatched_board import RISCVMatchedBoard
+from gem5.resources.resource import obtain_resource
+from gem5.simulate.simulator import Simulator
+from gem5.utils.requires import requires
+
 requires(isa_required=ISA.RISCV)
 
 parser = argparse.ArgumentParser(

configs/example/gem5_library/riscvmatched-hello.py

@@ -37,10 +37,10 @@ scons build/RISCV/gem5.opt
 ```
 """
 
+from gem5.isas import ISA
+from gem5.prebuilt.riscvmatched.riscvmatched_board import RISCVMatchedBoard
 from gem5.resources.resource import obtain_resource
 from gem5.simulate.simulator import Simulator
-from gem5.prebuilt.riscvmatched.riscvmatched_board import RISCVMatchedBoard
-from gem5.isas import ISA
 from gem5.utils.requires import requires
 
 requires(isa_required=ISA.RISCV)

configs/example/gem5_library/riscvmatched-microbenchmark-suite.py

@@ -33,10 +33,10 @@ The print statements in the script are for illustrative purposes only,
 and are not required to run the script.
 """
 
+from gem5.isas import ISA
+from gem5.prebuilt.riscvmatched.riscvmatched_board import RISCVMatchedBoard
 from gem5.resources.resource import obtain_resource
 from gem5.simulate.simulator import Simulator
-from gem5.prebuilt.riscvmatched.riscvmatched_board import RISCVMatchedBoard
-from gem5.isas import ISA
 from gem5.utils.requires import requires
 
 requires(isa_required=ISA.RISCV)

configs/example/gem5_library/x86-gapbs-benchmarks.py

@@ -48,24 +48,24 @@ scons build/X86/gem5.opt
 """
 
 import argparse
-import time
 import sys
+import time
 
 import m5
 from m5.objects import Root
 
-from gem5.utils.requires import requires
+from gem5.coherence_protocol import CoherenceProtocol
 from gem5.components.boards.x86_board import X86Board
 from gem5.components.memory import DualChannelDDR4_2400
+from gem5.components.processors.cpu_types import CPUTypes
 from gem5.components.processors.simple_switchable_processor import (
     SimpleSwitchableProcessor,
 )
-from gem5.components.processors.cpu_types import CPUTypes
 from gem5.isas import ISA
-from gem5.coherence_protocol import CoherenceProtocol
 from gem5.resources.resource import obtain_resource
-from gem5.simulate.simulator import Simulator
 from gem5.simulate.exit_event import ExitEvent
+from gem5.simulate.simulator import Simulator
+from gem5.utils.requires import requires
 
 requires(
     isa_required=ISA.X86,

configs/example/gem5_library/x86-npb-benchmarks.py

@@ -50,22 +50,23 @@ import time
 
 import m5
 from m5.objects import Root
+from m5.stats.gem5stats import get_simstat
+from m5.util import warn
 
-from gem5.utils.requires import requires
+from gem5.coherence_protocol import CoherenceProtocol
 from gem5.components.boards.x86_board import X86Board
 from gem5.components.memory import DualChannelDDR4_2400
+from gem5.components.processors.cpu_types import CPUTypes
 from gem5.components.processors.simple_switchable_processor import (
     SimpleSwitchableProcessor,
 )
-from gem5.components.processors.cpu_types import CPUTypes
 from gem5.isas import ISA
-from gem5.coherence_protocol import CoherenceProtocol
 from gem5.resources.resource import obtain_resource
-from gem5.simulate.simulator import Simulator
+from gem5.simulate.simulator import (
-from gem5.simulate.simulator import ExitEvent
+    ExitEvent,
-
+    Simulator,
-from m5.stats.gem5stats import get_simstat
+)
-from m5.util import warn
+from gem5.utils.requires import requires
 
 requires(
     isa_required=ISA.X86,

configs/example/gem5_library/x86-parsec-benchmarks.py

@@ -50,18 +50,18 @@ import time
 import m5
 from m5.objects import Root
 
-from gem5.utils.requires import requires
+from gem5.coherence_protocol import CoherenceProtocol
 from gem5.components.boards.x86_board import X86Board
 from gem5.components.memory import DualChannelDDR4_2400
+from gem5.components.processors.cpu_types import CPUTypes
 from gem5.components.processors.simple_switchable_processor import (
     SimpleSwitchableProcessor,
 )
-from gem5.components.processors.cpu_types import CPUTypes
 from gem5.isas import ISA
-from gem5.coherence_protocol import CoherenceProtocol
 from gem5.resources.resource import obtain_resource
-from gem5.simulate.simulator import Simulator
 from gem5.simulate.exit_event import ExitEvent
+from gem5.simulate.simulator import Simulator
+from gem5.utils.requires import requires
 
 # We check for the required gem5 build.
 

configs/example/gem5_library/x86-spec-cpu2006-benchmarks.py

@@ -49,29 +49,33 @@ scons build/X86/gem5.opt
 """
 
 import argparse
-import time
-import os
 import json
+import os
+import time
 
 import m5
 from m5.objects import Root
+from m5.stats.gem5stats import get_simstat
+from m5.util import (
+    fatal,
+    warn,
+)
 
-from gem5.utils.requires import requires
+from gem5.coherence_protocol import CoherenceProtocol
 from gem5.components.boards.x86_board import X86Board
 from gem5.components.memory import DualChannelDDR4_2400
+from gem5.components.processors.cpu_types import CPUTypes
 from gem5.components.processors.simple_switchable_processor import (
     SimpleSwitchableProcessor,
 )
-from gem5.components.processors.cpu_types import CPUTypes
 from gem5.isas import ISA
-from gem5.coherence_protocol import CoherenceProtocol
+from gem5.resources.resource import (
-from gem5.resources.resource import Resource, DiskImageResource
+    DiskImageResource,
-from gem5.simulate.simulator import Simulator
+    Resource,
+)
 from gem5.simulate.exit_event import ExitEvent
-
+from gem5.simulate.simulator import Simulator
-from m5.stats.gem5stats import get_simstat
+from gem5.utils.requires import requires
-from m5.util import warn
-from m5.util import fatal
 
 # We check for the required gem5 build.
 

configs/example/gem5_library/x86-spec-cpu2017-benchmarks.py

@@ -47,29 +47,33 @@ scons build/X86/gem5.opt
 """
 
 import argparse
-import time
-import os
 import json
+import os
+import time
 
 import m5
 from m5.objects import Root
+from m5.stats.gem5stats import get_simstat
+from m5.util import (
+    fatal,
+    warn,
+)
 
-from gem5.utils.requires import requires
+from gem5.coherence_protocol import CoherenceProtocol
 from gem5.components.boards.x86_board import X86Board
 from gem5.components.memory import DualChannelDDR4_2400
+from gem5.components.processors.cpu_types import CPUTypes
 from gem5.components.processors.simple_switchable_processor import (
     SimpleSwitchableProcessor,
 )
-from gem5.components.processors.cpu_types import CPUTypes
 from gem5.isas import ISA
-from gem5.coherence_protocol import CoherenceProtocol
+from gem5.resources.resource import (
-from gem5.resources.resource import obtain_resource, DiskImageResource
+    DiskImageResource,
-from gem5.simulate.simulator import Simulator
+    obtain_resource,
+)
 from gem5.simulate.exit_event import ExitEvent
-
+from gem5.simulate.simulator import Simulator
-from m5.stats.gem5stats import get_simstat
+from gem5.utils.requires import requires
-from m5.util import warn
-from m5.util import fatal
 
 # We check for the required gem5 build.
 

configs/example/gem5_library/x86-ubuntu-run-with-kvm-no-perf.py

@@ -38,21 +38,21 @@ scons build/X86/gem5.opt -j`nproc`
 ```
 """
 
-from gem5.utils.requires import requires
+from gem5.coherence_protocol import CoherenceProtocol
 from gem5.components.boards.x86_board import X86Board
 from gem5.components.cachehierarchies.ruby.mesi_two_level_cache_hierarchy import (
     MESITwoLevelCacheHierarchy,
 )
 from gem5.components.memory.single_channel import SingleChannelDDR4_2400
+from gem5.components.processors.cpu_types import CPUTypes
 from gem5.components.processors.simple_switchable_processor import (
     SimpleSwitchableProcessor,
 )
-from gem5.components.processors.cpu_types import CPUTypes
 from gem5.isas import ISA
-from gem5.coherence_protocol import CoherenceProtocol
-from gem5.simulate.simulator import Simulator
-from gem5.simulate.exit_event import ExitEvent
 from gem5.resources.resource import obtain_resource
+from gem5.simulate.exit_event import ExitEvent
+from gem5.simulate.simulator import Simulator
+from gem5.utils.requires import requires
 
 # This simulation requires using KVM with gem5 compiled for X86 simulation
 # and with MESI_Two_Level cache coherence protocol.

configs/example/gem5_library/x86-ubuntu-run-with-kvm.py

@@ -40,18 +40,18 @@ scons build/X86/gem5.opt
 ```
 """
 
-from gem5.utils.requires import requires
+from gem5.coherence_protocol import CoherenceProtocol
 from gem5.components.boards.x86_board import X86Board
 from gem5.components.memory.single_channel import SingleChannelDDR3_1600
+from gem5.components.processors.cpu_types import CPUTypes
 from gem5.components.processors.simple_switchable_processor import (
     SimpleSwitchableProcessor,
 )
-from gem5.components.processors.cpu_types import CPUTypes
 from gem5.isas import ISA
-from gem5.coherence_protocol import CoherenceProtocol
-from gem5.simulate.simulator import Simulator
-from gem5.simulate.exit_event import ExitEvent
 from gem5.resources.resource import obtain_resource
+from gem5.simulate.exit_event import ExitEvent
+from gem5.simulate.simulator import Simulator
+from gem5.utils.requires import requires
 
 # This runs a check to ensure the gem5 binary is compiled to X86 and to the
 # MESI Two Level coherence protocol.

configs/example/gem5_library/x86-ubuntu-run.py

@@ -48,7 +48,6 @@ from gem5.prebuilt.demo.x86_demo_board import X86DemoBoard
 from gem5.resources.resource import obtain_resource
 from gem5.simulate.simulator import Simulator
 
-
 # Here we setup the board. The prebuilt X86DemoBoard allows for Full-System X86
 # simulation.
 board = X86DemoBoard()

configs/example/gpufs/DisjointNetwork.py

@@ -27,13 +27,13 @@
 # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
 # POSSIBILITY OF SUCH DAMAGE.
 
-from m5.objects import *
-from m5.util import fatal
-
 from importlib import *
 
 from network import Network
 
+from m5.objects import *
+from m5.util import fatal
+
 
 class DisjointSimple(SimpleNetwork):
     def __init__(self, ruby_system):

configs/example/gpufs/Disjoint_VIPER.py

@@ -27,14 +27,14 @@
 # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
 # POSSIBILITY OF SUCH DAMAGE.
 
+from example.gpufs.DisjointNetwork import *
+from ruby import Ruby
+from ruby.GPU_VIPER import *
+
 from m5.defines import buildEnv
 from m5.objects import *
 from m5.util import fatal
 
-from example.gpufs.DisjointNetwork import *
-from ruby.GPU_VIPER import *
-from ruby import Ruby
-
 
 class DummySystem:
     def __init__(self, mem_ranges):

configs/example/gpufs/hip_cookbook.py

@@ -27,18 +27,21 @@
 # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
 # POSSIBILITY OF SUCH DAMAGE.
 
-import m5
-import runfs
-import tempfile
 import argparse
-import sys
 import os
+import sys
+import tempfile
 
+import runfs
 from amd import AmdGPUOptions
-from common import Options
+from common import (
-from common import GPUTLBOptions
+    GPUTLBOptions,
+    Options,
+)
 from ruby import Ruby
 
+import m5
+
 cookbook_runscript = """\
 export LD_LIBRARY_PATH=/opt/rocm/lib:$LD_LIBRARY_PATH
 export HSA_ENABLE_INTERRUPT=0

configs/example/gpufs/hip_rodinia.py

@@ -27,19 +27,22 @@
 # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
 # POSSIBILITY OF SUCH DAMAGE.
 
-import m5
-import runfs
-import base64
-import tempfile
 import argparse
-import sys
+import base64
 import os
+import sys
+import tempfile
 
+import runfs
 from amd import AmdGPUOptions
-from common import Options
+from common import (
-from common import GPUTLBOptions
+    GPUTLBOptions,
+    Options,
+)
 from ruby import Ruby
 
+import m5
+
 rodinia_runscript = """\
 export LD_LIBRARY_PATH=/opt/rocm/lib:$LD_LIBRARY_PATH
 export HSA_ENABLE_INTERRUPT=0

configs/example/gpufs/hip_samples.py

@@ -27,18 +27,21 @@
 # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
 # POSSIBILITY OF SUCH DAMAGE.
 
-import m5
-import runfs
-import tempfile
 import argparse
-import sys
 import os
+import sys
+import tempfile
 
+import runfs
 from amd import AmdGPUOptions
-from common import Options
+from common import (
-from common import GPUTLBOptions
+    GPUTLBOptions,
+    Options,
+)
 from ruby import Ruby
 
+import m5
+
 samples_runscript = """\
 export LD_LIBRARY_PATH=/opt/rocm/lib:$LD_LIBRARY_PATH
 export HSA_ENABLE_INTERRUPT=0

configs/example/gpufs/runfs.py

@@ -29,8 +29,8 @@
 
 # System includes
 import argparse
-import math
 import hashlib
+import math
 
 # gem5 related
 import m5
@@ -39,13 +39,15 @@ from m5.util import addToPath
 
 # gem5 options and objects
 addToPath("../../")
-from ruby import Ruby
-from common import Simulation
-from common import ObjectList
-from common import Options
-from common import GPUTLBOptions
-from common import GPUTLBConfig
 from amd import AmdGPUOptions
+from common import (
+    GPUTLBConfig,
+    GPUTLBOptions,
+    ObjectList,
+    Options,
+    Simulation,
+)
+from ruby import Ruby
 
 # GPU FS related
 from system.system import makeGpuFSSystem

configs/example/gpufs/system/system.py

@@ -27,18 +27,18 @@
 # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
 # POSSIBILITY OF SUCH DAMAGE.
 
+from common import (
+    GPUTLBConfig,
+    Simulation,
+)
+from common.Benchmarks import *
+from common.FSConfig import *
+from example.gpufs.Disjoint_VIPER import *
+from ruby import Ruby
 from system.amdgpu import *
 
 from m5.util import panic
 
-from common.Benchmarks import *
-from common.FSConfig import *
-from common import GPUTLBConfig
-from common import Simulation
-from ruby import Ruby
-
-from example.gpufs.Disjoint_VIPER import *
-
 
 def makeGpuFSSystem(args):
     # Boot options are standard gem5 options plus:

configs/example/gpufs/vega10.py

@@ -27,19 +27,21 @@
 # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
 # POSSIBILITY OF SUCH DAMAGE.
 
-import m5
-import runfs
-import base64
-import tempfile
 import argparse
-import sys
+import base64
 import os
+import sys
+import tempfile
 
+import runfs
 from amd import AmdGPUOptions
-from common import Options
+from common import (
-from common import GPUTLBOptions
+    GPUTLBOptions,
+    Options,
+)
 from ruby import Ruby
 
+import m5
 
 demo_runscript_without_checkpoint = """\
 export LD_LIBRARY_PATH=/opt/rocm/lib:$LD_LIBRARY_PATH

configs/example/hmc_hello.py

@@ -30,19 +30,21 @@
 #
 # Author: Éder F. Zulian
 
-import sys
 import argparse
+import sys
 
 import m5
 from m5.objects import *
 from m5.util import *
+
 from gem5.runtime import get_runtime_isa
 
 addToPath("../")
 
-from common import MemConfig
+from common import (
-from common import HMC
+    HMC,
-
+    MemConfig,
+)
 
 pd = "Simple 'hello world' example using HMC as main memory"
 parser = argparse.ArgumentParser(description=pd)

configs/example/hmctest.py

@@ -1,6 +1,6 @@
-import sys
 import argparse
 import subprocess
+import sys
 from pprint import pprint
 
 import m5
@@ -9,8 +9,10 @@ from m5.util import *
 
 addToPath("../")
 
-from common import MemConfig
+from common import (
-from common import HMC
+    HMC,
+    MemConfig,
+)
 
 
 def add_options(parser):

configs/example/hsaTopology.py

@@ -27,14 +27,26 @@
 # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
 # POSSIBILITY OF SUCH DAMAGE.
 
-import m5
-
 import operator
-from os import mkdir, makedirs, getpid, listdir, fsync
+from os import (
-from os.path import join as joinpath
+    fsync,
+    getpid,
+    listdir,
+    makedirs,
+    mkdir,
+)
 from os.path import isdir
-from shutil import rmtree, copyfile
+from os.path import join as joinpath
-from m5.util.convert import toFrequency, toMemorySize
+from shutil import (
+    copyfile,
+    rmtree,
+)
+
+import m5
+from m5.util.convert import (
+    toFrequency,
+    toMemorySize,
+)
 
 
 def file_append(path, contents):

configs/example/lupv/run_lupv.py

@@ -33,18 +33,18 @@ Characteristics
 * Automatically generates the DTB file
 """
 
+import argparse
+
 import m5
 from m5.objects import Root
 
 from gem5.components.boards.experimental.lupv_board import LupvBoard
 from gem5.components.memory.single_channel import SingleChannelDDR3_1600
-from gem5.components.processors.simple_processor import SimpleProcessor
 from gem5.components.processors.cpu_types import CPUTypes
+from gem5.components.processors.simple_processor import SimpleProcessor
 from gem5.isas import ISA
-from gem5.utils.requires import requires
 from gem5.resources.resource import obtain_resource
-
+from gem5.utils.requires import requires
-import argparse
 
 # Run a check to ensure the right version of gem5 is being used.
 requires(isa_required=ISA.RISCV)

configs/example/riscv/fs_linux.py

@@ -45,23 +45,28 @@ from os import path
 import m5
 from m5.defines import buildEnv
 from m5.objects import *
-from m5.util import addToPath, fatal, warn
+from m5.util import (
+    addToPath,
+    fatal,
+    warn,
+)
 from m5.util.fdthelper import *
 
 addToPath("../../")
 
-from ruby import Ruby
+from common import (
-
+    CacheConfig,
+    CpuConfig,
+    MemConfig,
+    ObjectList,
+    Options,
+    Simulation,
+)
+from common.Benchmarks import *
+from common.Caches import *
 from common.FSConfig import *
 from common.SysPaths import *
-from common.Benchmarks import *
+from ruby import Ruby
-from common import Simulation
-from common import CacheConfig
-from common import CpuConfig
-from common import MemConfig
-from common import ObjectList
-from common.Caches import *
-from common import Options
 
 # ------------------------- Usage Instructions ------------------------- #
 # Common system confirguration options (cpu types, num cpus, checkpointing

configs/example/ruby_direct_test.py

@@ -25,11 +25,14 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
+import argparse
+import os
+import sys
+
 import m5
-from m5.objects import *
 from m5.defines import buildEnv
+from m5.objects import *
 from m5.util import addToPath
-import os, argparse, sys
 
 addToPath("../")
 

configs/example/ruby_gpu_random_test.py

@@ -27,11 +27,14 @@
 # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
 # POSSIBILITY OF SUCH DAMAGE.
 
+import argparse
+import os
+import sys
+
 import m5
-from m5.objects import *
 from m5.defines import buildEnv
+from m5.objects import *
 from m5.util import addToPath
-import os, argparse, sys
 
 addToPath("../")
 

configs/example/ruby_mem_test.py

@@ -25,11 +25,14 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
+import argparse
+import os
+import sys
+
 import m5
-from m5.objects import *
 from m5.defines import buildEnv
+from m5.objects import *
 from m5.util import addToPath
-import os, argparse, sys
 
 addToPath("../")
 

configs/example/ruby_random_test.py

@@ -25,11 +25,14 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
+import argparse
+import os
+import sys
+
 import m5
-from m5.objects import *
 from m5.defines import buildEnv
+from m5.objects import *
 from m5.util import addToPath
-import os, argparse, sys
 
 addToPath("../")
 

configs/example/sc_main.py

@@ -26,7 +26,10 @@
 import sys
 
 import m5
-from m5.objects import SystemC_Kernel, Root
+from m5.objects import (
+    Root,
+    SystemC_Kernel,
+)
 
 # pylint:disable=unused-variable
 

configs/example/sst/riscv_fs.py

@@ -24,15 +24,15 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
+import argparse
+from os import path
+
 import m5
 from m5.objects import *
-from os import path
 
 # For downloading the disk image
 from gem5.resources.resource import obtain_resource
 
-import argparse
-
 
 def generateMemNode(state, mem_range):
     node = FdtNode(f"memory@{int(mem_range.start):x}")

configs/learning_gem5/part1/two_level.py

@@ -42,6 +42,7 @@ import m5
 
 # import all of the SimObjects
 from m5.objects import *
+
 from gem5.runtime import get_runtime_isa
 
 # Add the common scripts to our path

configs/learning_gem5/part3/msi_caches.py

@@ -37,9 +37,11 @@ IMPORTANT: If you modify this file, it's likely that the Learning gem5 book
 import math
 
 from m5.defines import buildEnv
-from m5.util import fatal, panic
-
 from m5.objects import *
+from m5.util import (
+    fatal,
+    panic,
+)
 
 
 class MyCacheSystem(RubySystem):

configs/learning_gem5/part3/ruby_caches_MI_example.py

@@ -39,9 +39,11 @@ IMPORTANT: If you modify this file, it's likely that the Learning gem5 book
 import math
 
 from m5.defines import buildEnv
-from m5.util import fatal, panic
-
 from m5.objects import *
+from m5.util import (
+    fatal,
+    panic,
+)
 
 
 class MyCacheSystem(RubySystem):

configs/learning_gem5/part3/ruby_test.py

@@ -33,14 +33,14 @@ IMPORTANT: If you modify this file, it's likely that the Learning gem5 book
 
 """
 
+from test_caches import TestCacheSystem
+
 # import the m5 (gem5) library created when gem5 is built
 import m5
 
 # import all of the SimObjects
 from m5.objects import *
 
-from test_caches import TestCacheSystem
-
 # create the system we are going to simulate
 system = System()
 

configs/learning_gem5/part3/test_caches.py

@@ -34,12 +34,15 @@ IMPORTANT: If you modify this file, it's likely that the Learning gem5 book
 
 """
 
+from msi_caches import (
+    DirController,
+    L1Cache,
+    MyNetwork,
+)
+
 from m5.defines import buildEnv
-from m5.util import fatal
-
 from m5.objects import *
-
+from m5.util import fatal
-from msi_caches import L1Cache, DirController, MyNetwork
 
 
 class TestCacheSystem(RubySystem):

configs/network/Network.py

@@ -25,10 +25,15 @@
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
 import math
+
 import m5
-from m5.objects import *
 from m5.defines import buildEnv
-from m5.util import addToPath, fatal, warn
+from m5.objects import *
+from m5.util import (
+    addToPath,
+    fatal,
+    warn,
+)
 
 
 def define_options(parser):

configs/nvm/sweep.py

@@ -33,18 +33,20 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
-import math
 import argparse
+import math
 
 import m5
 from m5.objects import *
-from m5.util import addToPath
 from m5.stats import periodicStatDump
+from m5.util import addToPath
 
 addToPath("../")
 
-from common import ObjectList
+from common import (
-from common import MemConfig
+    MemConfig,
+    ObjectList,
+)
 
 # this script is helpful to sweep the efficiency of a specific memory
 # controller configuration, by varying the number of banks accessed,

configs/nvm/sweep_hybrid.py

@@ -33,18 +33,20 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
-import math
 import argparse
+import math
 
 import m5
 from m5.objects import *
-from m5.util import addToPath
 from m5.stats import periodicStatDump
+from m5.util import addToPath
 
 addToPath("../")
 
-from common import ObjectList
+from common import (
-from common import MemConfig
+    MemConfig,
+    ObjectList,
+)
 
 # this script is helpful to sweep the efficiency of a specific memory
 # controller configuration, by varying the number of banks accessed,

configs/ruby/AMD_Base_Constructor.py

@@ -28,10 +28,15 @@
 # POSSIBILITY OF SUCH DAMAGE.
 
 import math
+
 import m5
-from m5.objects import *
 from m5.defines import buildEnv
-from m5.util import addToPath, convert
+from m5.objects import *
+from m5.util import (
+    addToPath,
+    convert,
+)
+
 from .CntrlBase import *
 
 addToPath("../")

configs/ruby/CHI.py

@@ -34,8 +34,9 @@
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
 import m5
-from m5.objects import *
 from m5.defines import buildEnv
+from m5.objects import *
+
 from .Ruby import create_topology
 
 
@@ -53,8 +54,8 @@ def define_options(parser):
 
 def read_config_file(file):
     """Read file as a module and return it"""
-    import types
     import importlib.machinery
+    import types
 
     loader = importlib.machinery.SourceFileLoader("chi_configs", file)
     chi_configs = types.ModuleType(loader.name)

configs/ruby/CHI_config.py

@@ -46,6 +46,7 @@ node to router binding. See configs/example/noc_config/2x4.py for an example.
 """
 
 import math
+
 import m5
 from m5.objects import *
 

configs/ruby/GPU_VIPER.py

@@ -28,15 +28,22 @@
 # POSSIBILITY OF SUCH DAMAGE.
 
 import math
+
+from common import (
+    FileSystemConfig,
+    MemConfig,
+    ObjectList,
+)
+
 import m5
-from m5.objects import *
 from m5.defines import buildEnv
+from m5.objects import *
 from m5.util import addToPath
-from .Ruby import create_topology
+
-from .Ruby import send_evicts
+from .Ruby import (
-from common import ObjectList
+    create_topology,
-from common import MemConfig
+    send_evicts,
-from common import FileSystemConfig
+)
 
 addToPath("../")
 

configs/ruby/Garnet_standalone.py

@@ -26,10 +26,14 @@
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
 import m5
-from m5.objects import *
 from m5.defines import buildEnv
+from m5.objects import *
 from m5.util import addToPath
-from .Ruby import create_topology, create_directories
+
+from .Ruby import (
+    create_directories,
+    create_topology,
+)
 
 
 #

configs/ruby/MESI_Three_Level.py

@@ -28,13 +28,19 @@
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
 import math
-import m5
+
-from m5.objects import *
-from m5.defines import buildEnv
-from .Ruby import create_topology, create_directories
-from .Ruby import send_evicts
 from common import FileSystemConfig
 
+import m5
+from m5.defines import buildEnv
+from m5.objects import *
+
+from .Ruby import (
+    create_directories,
+    create_topology,
+    send_evicts,
+)
+
 
 #
 # Declare caches used by the protocol

configs/ruby/MESI_Three_Level_HTM.py

@@ -28,13 +28,19 @@
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
 import math
-import m5
+
-from m5.objects import *
-from m5.defines import buildEnv
-from .Ruby import create_topology, create_directories
-from .Ruby import send_evicts
 from common import FileSystemConfig
 
+import m5
+from m5.defines import buildEnv
+from m5.objects import *
+
+from .Ruby import (
+    create_directories,
+    create_topology,
+    send_evicts,
+)
+
 
 #
 # Declare caches used by the protocol