From d11c40dcac927b9501b61fed66b7144de648a4d8 Mon Sep 17 00:00:00 2001 From: "Bobby R. Bruce" Date: Wed, 29 Nov 2023 22:06:41 -0800 Subject: [PATCH] misc: Run `pre-commit run --all-files` This ensures `isort` is applied to all files in the repo. Change-Id: Ib7ced1c924ef1639542bf0d1a01c5737f6ba43e9 --- build_tools/cxx_config_cc.py | 3 +- build_tools/cxx_config_hh.py | 1 - build_tools/enum_cc.py | 1 - build_tools/enum_hh.py | 1 - build_tools/sim_object_param_struct_cc.py | 1 - build_tools/sim_object_param_struct_hh.py | 1 - configs/common/Benchmarks.py | 8 +- configs/common/CacheConfig.py | 7 +- configs/common/Caches.py | 1 + configs/common/CpuConfig.py | 2 +- configs/common/FSConfig.py | 5 +- configs/common/FileSystemConfig.py | 29 +++++-- configs/common/MemConfig.py | 8 +- configs/common/ObjectList.py | 8 +- configs/common/Options.py | 6 +- configs/common/SimpleOpts.py | 6 +- configs/common/Simulation.py | 13 ++- configs/common/SysPaths.py | 3 +- configs/common/cores/arm/O3_ARM_Etrace.py | 1 + configs/common/cores/arm/__init__.py | 2 +- configs/common/cpu2000.py | 11 ++- configs/deprecated/example/fs.py | 28 +++--- configs/deprecated/example/se.py | 28 +++--- configs/dram/lat_mem_rd.py | 10 ++- configs/dram/low_power_sweep.py | 8 +- configs/dram/sweep.py | 10 ++- configs/example/apu_se.py | 24 +++--- configs/example/arm/baremetal.py | 21 +++-- configs/example/arm/devices.py | 2 +- configs/example/arm/dist_bigLITTLE.py | 4 +- configs/example/arm/etrace_se.py | 12 +-- configs/example/arm/fs_bigLITTLE.py | 27 ++++-- configs/example/arm/fs_power.py | 9 +- configs/example/arm/ruby_fs.py | 24 +++--- configs/example/arm/starter_fs.py | 20 +++-- configs/example/arm/starter_se.py | 19 ++-- configs/example/arm/workloads.py | 10 ++- configs/example/dramsys.py | 1 - configs/example/etrace_replay.py | 13 ++- configs/example/garnet_synth_traffic.py | 7 +- configs/example/gem5_library/arm-hello.py | 10 +-- .../example/gem5_library/arm-ubuntu-run.py | 16 ++-- .../caches/octopi-cache-example.py | 17 ++-- .../riscv-hello-restore-checkpoint.py | 10 +-- .../riscv-hello-save-checkpoint.py | 11 +-- .../checkpoints/simpoints-se-checkpoint.py | 25 +++--- .../checkpoints/simpoints-se-restore.py | 26 +++--- .../gem5_library/dramsys/arm-hello-dramsys.py | 10 +-- .../gem5_library/dramsys/dramsys-traffic.py | 2 +- .../create-looppoint-checkpoints.py | 16 ++-- .../restore-looppoint-checkpoint.py | 16 ++-- .../example/gem5_library/memory_traffic.py | 8 +- configs/example/gem5_library/power-hello.py | 10 +-- configs/example/gem5_library/riscv-fs.py | 6 +- .../example/gem5_library/riscv-ubuntu-run.py | 6 +- .../example/gem5_library/riscvmatched-fs.py | 12 +-- .../gem5_library/riscvmatched-hello.py | 4 +- .../riscvmatched-microbenchmark-suite.py | 4 +- .../gem5_library/x86-gapbs-benchmarks.py | 10 +-- .../gem5_library/x86-npb-benchmarks.py | 17 ++-- .../gem5_library/x86-parsec-benchmarks.py | 8 +- .../x86-spec-cpu2006-benchmarks.py | 26 +++--- .../x86-spec-cpu2017-benchmarks.py | 26 +++--- .../x86-ubuntu-run-with-kvm-no-perf.py | 10 +-- .../gem5_library/x86-ubuntu-run-with-kvm.py | 10 +-- .../example/gem5_library/x86-ubuntu-run.py | 1 - configs/example/gpufs/DisjointNetwork.py | 6 +- configs/example/gpufs/Disjoint_VIPER.py | 8 +- configs/example/gpufs/hip_cookbook.py | 15 ++-- configs/example/gpufs/hip_rodinia.py | 17 ++-- configs/example/gpufs/hip_samples.py | 15 ++-- configs/example/gpufs/runfs.py | 16 ++-- configs/example/gpufs/system/system.py | 16 ++-- configs/example/gpufs/vega10.py | 16 ++-- configs/example/hmc_hello.py | 10 ++- configs/example/hmctest.py | 8 +- configs/example/hsaTopology.py | 24 ++++-- configs/example/lupv/run_lupv.py | 8 +- configs/example/riscv/fs_linux.py | 27 +++--- configs/example/ruby_direct_test.py | 7 +- configs/example/ruby_gpu_random_test.py | 7 +- configs/example/ruby_mem_test.py | 7 +- configs/example/ruby_random_test.py | 7 +- configs/example/sc_main.py | 5 +- configs/example/sst/riscv_fs.py | 6 +- configs/learning_gem5/part1/two_level.py | 1 + configs/learning_gem5/part3/msi_caches.py | 6 +- .../part3/ruby_caches_MI_example.py | 6 +- configs/learning_gem5/part3/ruby_test.py | 4 +- configs/learning_gem5/part3/test_caches.py | 11 ++- configs/network/Network.py | 9 +- configs/nvm/sweep.py | 10 ++- configs/nvm/sweep_hybrid.py | 10 ++- configs/ruby/AMD_Base_Constructor.py | 9 +- configs/ruby/CHI.py | 5 +- configs/ruby/CHI_config.py | 1 + configs/ruby/GPU_VIPER.py | 19 ++-- configs/ruby/Garnet_standalone.py | 8 +- configs/ruby/MESI_Three_Level.py | 16 ++-- configs/ruby/MESI_Three_Level_HTM.py | 16 ++-- configs/ruby/MESI_Two_Level.py | 11 ++- configs/ruby/MI_example.py | 11 ++- configs/ruby/MOESI_AMD_Base.py | 17 ++-- configs/ruby/MOESI_CMP_directory.py | 11 ++- configs/ruby/MOESI_CMP_token.py | 11 ++- configs/ruby/MOESI_hammer.py | 16 ++-- configs/ruby/Ruby.py | 20 +++-- configs/splash2/cluster.py | 2 +- configs/splash2/run.py | 2 +- configs/topologies/Crossbar.py | 6 +- configs/topologies/CrossbarGarnet.py | 6 +- configs/topologies/CustomMesh.py | 7 +- configs/topologies/MeshDirCorners_XY.py | 7 +- configs/topologies/Mesh_XY.py | 7 +- configs/topologies/Mesh_westfirst.py | 6 +- configs/topologies/Pt2Pt.py | 6 +- ext/testlib/__init__.py | 20 ++--- ext/testlib/configuration.py | 7 +- ext/testlib/fixture.py | 4 +- ext/testlib/handlers.py | 6 +- ext/testlib/helper.py | 5 +- ext/testlib/loader.py | 4 +- ext/testlib/main.py | 2 +- ext/testlib/query.py | 2 +- ext/testlib/result.py | 2 +- ext/testlib/runner.py | 6 +- ext/testlib/terminal.py | 4 +- ext/testlib/uid.py | 2 +- ext/testlib/wrappers.py | 5 +- site_scons/gem5_scons/__init__.py | 6 +- site_scons/gem5_scons/builders/blob.py | 11 +-- site_scons/gem5_scons/builders/config_file.py | 5 +- .../gem5_scons/builders/switching_headers.py | 5 +- site_scons/gem5_scons/kconfig.py | 3 +- site_scons/gem5_scons/util.py | 6 +- site_scons/site_tools/git.py | 4 +- src/arch/amdgpu/common/X86GPUTLB.py | 3 +- src/arch/amdgpu/vega/VegaGPUTLB.py | 5 +- src/arch/arm/ArmCPU.py | 17 ++-- src/arch/arm/ArmDecoder.py | 2 +- src/arch/arm/ArmFsWorkload.py | 6 +- src/arch/arm/ArmISA.py | 11 ++- src/arch/arm/ArmMMU.py | 5 +- src/arch/arm/ArmNativeTrace.py | 4 +- src/arch/arm/ArmPMU.py | 7 +- src/arch/arm/ArmSeWorkload.py | 3 +- src/arch/arm/ArmSemihosting.py | 5 +- src/arch/arm/ArmSystem.py | 11 ++- src/arch/arm/ArmTLB.py | 4 +- .../fastmodel/CortexA76/FastModelCortexA76.py | 27 +++--- .../fastmodel/CortexR52/FastModelCortexR52.py | 22 +++-- src/arch/arm/fastmodel/FastModel.py | 8 +- src/arch/arm/fastmodel/GIC/FastModelGIC.py | 12 +-- .../fastmodel/PL330_DMAC/FastModelPL330.py | 7 +- src/arch/arm/fastmodel/arm_fast_model.py | 1 + src/arch/arm/fastmodel/iris/Iris.py | 7 +- .../FastModelResetControllerExample.py | 5 +- src/arch/arm/kvm/ArmKvmCPU.py | 2 +- src/arch/arm/kvm/ArmV8KvmCPU.py | 2 +- src/arch/arm/kvm/BaseArmKvmCPU.py | 2 +- src/arch/arm/kvm/KvmGic.py | 6 +- src/arch/arm/tracers/ArmCapstone.py | 4 +- src/arch/arm/tracers/TarmacTrace.py | 4 +- src/arch/isa_parser/isa_parser.py | 1 + src/arch/isa_parser/operand_list.py | 8 +- src/arch/micro_asm.py | 8 +- src/arch/micro_asm_test.py | 7 +- src/arch/mips/MipsCPU.py | 8 +- src/arch/mips/MipsISA.py | 3 +- src/arch/mips/MipsSeWorkload.py | 3 +- src/arch/mips/MipsTLB.py | 5 +- src/arch/power/PowerCPU.py | 8 +- src/arch/power/PowerSeWorkload.py | 3 +- src/arch/power/PowerTLB.py | 5 +- src/arch/riscv/PMAChecker.py | 2 +- src/arch/riscv/PMP.py | 2 +- src/arch/riscv/RiscvCPU.py | 8 +- src/arch/riscv/RiscvFsWorkload.py | 8 +- src/arch/riscv/RiscvISA.py | 7 +- src/arch/riscv/RiscvMMU.py | 5 +- src/arch/riscv/RiscvSeWorkload.py | 3 +- src/arch/riscv/RiscvTLB.py | 5 +- src/arch/sparc/SparcCPU.py | 8 +- src/arch/sparc/SparcFsWorkload.py | 3 +- src/arch/sparc/SparcMMU.py | 4 +- src/arch/sparc/SparcNativeTrace.py | 5 +- src/arch/sparc/SparcSeWorkload.py | 3 +- src/arch/sparc/SparcTLB.py | 5 +- src/arch/x86/X86CPU.py | 13 ++- src/arch/x86/X86FsWorkload.py | 20 +++-- src/arch/x86/X86LocalApic.py | 5 +- src/arch/x86/X86NativeTrace.py | 5 +- src/arch/x86/X86SeWorkload.py | 3 +- src/arch/x86/X86TLB.py | 5 +- src/arch/x86/kvm/X86KvmCPU.py | 5 +- src/base/Graphics.py | 2 +- src/base/vnc/Vnc.py | 4 +- src/cpu/BaseCPU.py | 19 ++-- src/cpu/CPUTracers.py | 4 +- src/cpu/Capstone.py | 4 +- src/cpu/CheckerCPU.py | 3 +- src/cpu/CpuCluster.py | 2 +- src/cpu/DummyChecker.py | 2 +- src/cpu/FuncUnit.py | 2 +- src/cpu/InstPBTrace.py | 5 +- src/cpu/kvm/BaseKvmCPU.py | 7 +- src/cpu/kvm/KvmVM.py | 1 - src/cpu/minor/BaseMinorCPU.py | 11 ++- src/cpu/o3/BaseO3CPU.py | 7 +- src/cpu/o3/BaseO3Checker.py | 2 +- src/cpu/o3/FUPool.py | 4 +- src/cpu/o3/FuncUnitConfig.py | 5 +- src/cpu/pred/BranchPredictor.py | 5 +- src/cpu/probes/PcCountTracker.py | 4 +- src/cpu/simple/BaseAtomicSimpleCPU.py | 2 +- src/cpu/simple/BaseNonCachingSimpleCPU.py | 2 +- src/cpu/simple/BaseSimpleCPU.py | 5 +- src/cpu/simple/BaseTimingSimpleCPU.py | 3 +- src/cpu/simple/probes/SimPoint.py | 2 +- .../directedtest/RubyDirectedTester.py | 5 +- src/cpu/testers/gpu_ruby_test/CpuThread.py | 3 +- src/cpu/testers/gpu_ruby_test/DmaThread.py | 3 +- src/cpu/testers/gpu_ruby_test/GpuWavefront.py | 3 +- src/cpu/testers/memtest/MemTest.py | 3 +- src/cpu/testers/rubytest/RubyTester.py | 3 +- src/cpu/testers/traffic_gen/BaseTrafficGen.py | 2 +- src/cpu/testers/traffic_gen/GUPSGen.py | 2 +- src/cpu/testers/traffic_gen/PyTrafficGen.py | 3 +- src/cpu/testers/traffic_gen/TrafficGen.py | 2 +- src/cpu/trace/TraceCPU.py | 2 +- src/dev/BadDevice.py | 2 +- src/dev/Device.py | 3 +- src/dev/IntPin.py | 5 +- src/dev/Platform.py | 2 +- src/dev/ResetPort.py | 5 +- src/dev/amdgpu/AMDGPU.py | 15 +++- src/dev/arm/Doorbell.py | 2 +- src/dev/arm/EnergyCtrl.py | 4 +- src/dev/arm/FlashDevice.py | 3 +- src/dev/arm/GenericTimer.py | 16 +++- src/dev/arm/Gic.py | 12 +-- src/dev/arm/NoMali.py | 3 +- src/dev/arm/RealView.py | 86 +++++++++++-------- src/dev/arm/SMMUv3.py | 4 +- src/dev/arm/UFSHostDevice.py | 5 +- src/dev/arm/VExpressFastmodel.py | 10 ++- src/dev/arm/VirtIOMMIO.py | 12 +-- src/dev/arm/css/Scmi.py | 6 +- src/dev/hsa/HSADevice.py | 6 +- src/dev/hsa/HSADriver.py | 4 +- src/dev/i2c/I2C.py | 4 +- src/dev/lupio/LupioBLK.py | 1 - src/dev/lupio/LupioTTY.py | 3 +- src/dev/mips/Malta.py | 5 +- src/dev/net/Ethernet.py | 8 +- src/dev/pci/CopyEngine.py | 8 +- src/dev/pci/PciDevice.py | 6 +- src/dev/pci/PciHost.py | 6 +- src/dev/ps2/PS2.py | 2 +- src/dev/qemu/QemuFwCfg.py | 4 +- src/dev/riscv/HiFive.py | 9 +- src/dev/riscv/RTC.py | 2 +- src/dev/riscv/RiscvVirtIOMMIO.py | 9 +- src/dev/serial/Terminal.py | 5 +- src/dev/serial/Uart.py | 7 +- src/dev/sparc/T1000.py | 12 ++- src/dev/storage/DiskImage.py | 2 +- src/dev/storage/Ide.py | 7 +- src/dev/storage/SimpleDisk.py | 2 +- src/dev/virtio/VirtIO.py | 9 +- src/dev/virtio/VirtIO9P.py | 2 +- src/dev/virtio/VirtIOBlock.py | 2 +- src/dev/virtio/VirtIOConsole.py | 4 +- src/dev/virtio/VirtIORng 2.py | 2 +- src/dev/virtio/VirtIORng.py | 2 +- src/dev/x86/Cmos.py | 4 +- src/dev/x86/I8042.py | 4 +- src/dev/x86/I82094AA.py | 4 +- src/dev/x86/I8237.py | 2 +- src/dev/x86/I8254.py | 4 +- src/dev/x86/I8259.py | 7 +- src/dev/x86/Pc.py | 12 +-- src/dev/x86/PcSpeaker.py | 2 +- src/dev/x86/SouthBridge.py | 11 ++- src/dev/x86/X86Ide.py | 4 +- src/dev/x86/X86QemuFwCfg.py | 7 +- src/gpu-compute/GPU.py | 7 +- src/gpu-compute/LdsState.py | 3 +- src/learning_gem5/part2/SimpleCache.py | 2 +- src/mem/AbstractMemory.py | 2 +- src/mem/Bridge.py | 2 +- src/mem/CfiMemory.py | 7 +- src/mem/CommMonitor.py | 2 +- src/mem/DRAMSim2.py | 2 +- src/mem/DRAMSys.py | 8 +- src/mem/DRAMsim3.py | 3 +- src/mem/HBMCtrl.py | 2 +- src/mem/HMCController.py | 2 +- src/mem/HeteroMemCtrl.py | 2 +- src/mem/MemChecker.py | 2 +- src/mem/MemCtrl.py | 4 +- src/mem/MemDelay.py | 2 +- src/mem/MemInterface.py | 3 +- src/mem/NVMInterface.py | 6 +- src/mem/SerialLink.py | 2 +- src/mem/SharedMemoryServer.py | 2 +- src/mem/SimpleMemory.py | 2 +- src/mem/ThreadBridge.py | 2 +- src/mem/XBar.py | 3 +- src/mem/cache/Cache.py | 7 +- src/mem/cache/compressors/Compressors.py | 5 +- src/mem/cache/prefetch/Prefetcher.py | 7 +- src/mem/cache/tags/Tags.py | 4 +- src/mem/probes/MemFootprintProbe.py | 3 +- src/mem/probes/MemTraceProbe.py | 2 +- src/mem/probes/StackDistProbe.py | 2 +- src/mem/qos/QoSMemCtrl.py | 4 +- src/mem/qos/QoSMemSinkCtrl.py | 2 +- src/mem/qos/QoSPolicy.py | 2 +- src/mem/ruby/network/BasicRouter.py | 3 +- src/mem/ruby/network/Network.py | 4 +- src/mem/ruby/network/garnet/GarnetLink.py | 7 +- src/mem/ruby/network/garnet/GarnetNetwork.py | 6 +- src/mem/ruby/network/simple/SimpleLink.py | 9 +- src/mem/ruby/network/simple/SimpleNetwork.py | 11 ++- src/mem/ruby/slicc_interface/Controller.py | 2 +- src/mem/ruby/structures/RubyCache.py | 2 +- src/mem/ruby/structures/RubyPrefetcher.py | 5 +- src/mem/ruby/system/GPUCoalescer.py | 3 +- src/mem/ruby/system/RubySystem.py | 4 +- src/mem/ruby/system/Sequencer.py | 2 +- src/mem/ruby/system/VIPERCoalescer.py | 2 +- src/mem/slicc/ast/AST.py | 5 +- src/mem/slicc/ast/ActionDeclAST.py | 6 +- src/mem/slicc/ast/EnumDeclAST.py | 5 +- src/mem/slicc/ast/ExprStatementAST.py | 2 +- src/mem/slicc/ast/FuncCallExprAST.py | 5 +- src/mem/slicc/ast/FuncDeclAST.py | 5 +- src/mem/slicc/ast/InPortDeclAST.py | 6 +- src/mem/slicc/ast/MachineAST.py | 5 +- src/mem/slicc/ast/OutPortDeclAST.py | 6 +- src/mem/slicc/ast/StateDeclAST.py | 5 +- src/mem/slicc/ast/TypeAST.py | 1 - src/mem/slicc/ast/TypeFieldEnumAST.py | 6 +- src/mem/slicc/ast/TypeFieldStateAST.py | 5 +- src/mem/slicc/ast/VarExprAST.py | 5 +- src/mem/slicc/ast/__init__.py | 9 +- src/mem/slicc/parser.py | 5 +- src/mem/slicc/symbols/StateMachine.py | 4 +- src/mem/slicc/symbols/Symbol.py | 2 +- src/mem/slicc/symbols/Transition.py | 2 +- src/mem/slicc/symbols/Type.py | 2 +- src/mem/slicc/symbols/__init__.py | 2 +- .../gem5/components/boards/abstract_board.py | 26 ++++-- .../boards/abstract_system_board.py | 9 +- .../gem5/components/boards/arm_board.py | 67 ++++++++------- .../boards/experimental/lupv_board.py | 42 +++++---- .../components/boards/kernel_disk_workload.py | 25 +++--- .../gem5/components/boards/riscv_board.py | 42 ++++----- .../components/boards/se_binary_workload.py | 35 ++++---- .../gem5/components/boards/simple_board.py | 18 ++-- .../gem5/components/boards/test_board.py | 20 +++-- .../gem5/components/boards/x86_board.py | 59 ++++++------- .../abstract_cache_hierarchy.py | 9 +- .../chi/nodes/abstract_node.py | 18 ++-- .../cachehierarchies/chi/nodes/directory.py | 9 +- .../chi/nodes/dma_requestor.py | 7 +- .../chi/nodes/private_l1_moesi_cache.py | 8 +- .../chi/private_l1_cache_hierarchy.py | 32 ++++--- .../abstract_classic_cache_hierarchy.py | 5 +- .../classic/caches/l1dcache.py | 12 ++- .../classic/caches/l1icache.py | 6 +- .../classic/caches/l2cache.py | 13 ++- .../classic/caches/mmu_cache.py | 8 +- .../cachehierarchies/classic/no_cache.py | 17 ++-- .../classic/private_l1_cache_hierarchy.py | 17 ++-- .../private_l1_private_l2_cache_hierarchy.py | 19 ++-- .../private_l1_shared_l2_cache_hierarchy.py | 19 ++-- .../ruby/caches/abstract_l1_cache.py | 8 +- .../ruby/caches/mesi_three_level/directory.py | 7 +- .../caches/mesi_three_level/dma_controller.py | 7 +- .../ruby/caches/mesi_three_level/l1_cache.py | 16 ++-- .../ruby/caches/mesi_three_level/l2_cache.py | 14 +-- .../ruby/caches/mesi_three_level/l3_cache.py | 8 +- .../ruby/caches/mesi_two_level/directory.py | 7 +- .../caches/mesi_two_level/dma_controller.py | 4 +- .../ruby/caches/mesi_two_level/l1_cache.py | 19 ++-- .../ruby/caches/mesi_two_level/l2_cache.py | 13 +-- .../ruby/caches/mi_example/directory.py | 10 ++- .../ruby/caches/mi_example/dma_controller.py | 6 +- .../ruby/caches/mi_example/l1_cache.py | 10 ++- .../prebuilt/octopi_cache/core_complex.py | 18 ++-- .../caches/prebuilt/octopi_cache/octopi.py | 24 ++++-- .../prebuilt/octopi_cache/octopi_network.py | 2 +- .../octopi_cache/ruby_network_components.py | 6 +- .../ruby/mesi_three_level_cache_hierarchy.py | 26 +++--- .../ruby/mesi_two_level_cache_hierarchy.py | 22 +++-- .../ruby/mi_example_cache_hierarchy.py | 24 +++--- .../ruby/topologies/simple_pt2pt.py | 7 +- src/python/gem5/components/memory/__init__.py | 40 +++++---- .../memory/abstract_memory_system.py | 19 +++- .../gem5/components/memory/dramsim_3.py | 20 +++-- src/python/gem5/components/memory/dramsys.py | 14 +-- src/python/gem5/components/memory/hbm.py | 25 ++++-- src/python/gem5/components/memory/memory.py | 20 ++++- .../gem5/components/memory/multi_channel.py | 13 +-- src/python/gem5/components/memory/simple.py | 17 +++- .../gem5/components/memory/single_channel.py | 16 ++-- .../components/processors/abstract_core.py | 21 +++-- .../processors/abstract_generator.py | 7 +- .../processors/abstract_generator_core.py | 15 ++-- .../processors/abstract_processor.py | 18 ++-- .../components/processors/base_cpu_core.py | 28 +++--- .../processors/base_cpu_processor.py | 19 ++-- .../processors/complex_generator.py | 16 ++-- .../processors/complex_generator_core.py | 24 ++++-- .../gem5/components/processors/cpu_types.py | 6 +- .../components/processors/gups_generator.py | 2 +- .../processors/gups_generator_core.py | 10 ++- .../processors/gups_generator_ep.py | 4 +- .../processors/gups_generator_par.py | 7 +- .../components/processors/linear_generator.py | 12 +-- .../processors/linear_generator_core.py | 20 +++-- .../components/processors/random_generator.py | 13 ++- .../processors/random_generator_core.py | 20 +++-- .../gem5/components/processors/simple_core.py | 10 +-- .../components/processors/simple_processor.py | 14 +-- .../processors/simple_switchable_processor.py | 19 ++-- .../processors/switchable_processor.py | 16 ++-- .../processors/traffic_generator.py | 9 +- .../processors/traffic_generator_core.py | 7 +- .../gem5/prebuilt/demo/x86_demo_board.py | 8 +- .../riscvmatched/riscvmatched_board.py | 68 +++++++-------- .../riscvmatched/riscvmatched_cache.py | 22 +++-- .../riscvmatched/riscvmatched_core.py | 21 ++--- .../riscvmatched/riscvmatched_processor.py | 8 +- src/python/gem5/resources/client.py | 21 +++-- .../resources/client_api/abstract_client.py | 12 ++- .../gem5/resources/client_api/atlasclient.py | 21 ++++- .../resources/client_api/client_wrapper.py | 18 ++-- .../gem5/resources/client_api/jsonclient.py | 14 ++- src/python/gem5/resources/downloader.py | 38 ++++---- src/python/gem5/resources/elfie.py | 6 +- src/python/gem5/resources/looppoint.py | 17 ++-- src/python/gem5/resources/md5_utils.py | 2 +- src/python/gem5/resources/resource.py | 40 +++++---- src/python/gem5/resources/workload.py | 17 +++- src/python/gem5/runtime.py | 9 +- .../gem5/simulate/exit_event_generators.py | 14 ++- src/python/gem5/simulate/simulator.py | 42 +++++---- src/python/gem5/utils/filelock.py | 2 +- .../gem5/utils/multiprocessing/__init__.py | 7 +- .../utils/multiprocessing/_command_line.py | 5 +- .../gem5/utils/multiprocessing/context.py | 5 +- .../utils/multiprocessing/popen_spawn_gem5.py | 14 +-- src/python/gem5/utils/requires.py | 14 +-- src/python/gem5/utils/simpoint.py | 12 ++- src/python/m5/SimObject.py | 25 +++--- src/python/m5/__init__.py | 15 ++-- src/python/m5/debug.py | 10 ++- src/python/m5/event.py | 7 +- src/python/m5/ext/pystats/__init__.py | 4 +- src/python/m5/ext/pystats/abstract_stat.py | 4 +- src/python/m5/ext/pystats/group.py | 5 +- src/python/m5/ext/pystats/jsonloader.py | 22 +++-- .../m5/ext/pystats/serializable_stat.py | 10 ++- src/python/m5/ext/pystats/simstat.py | 7 +- src/python/m5/ext/pystats/statistic.py | 8 +- src/python/m5/main.py | 26 +++--- src/python/m5/objects/SimObject.py | 3 +- src/python/m5/options.py | 1 - src/python/m5/params.py | 33 ++++--- src/python/m5/simulate.py | 46 ++++++---- src/python/m5/stats/__init__.py | 14 +-- src/python/m5/stats/gem5stats.py | 11 ++- src/python/m5/ticks.py | 3 +- src/python/m5/trace.py | 8 +- src/python/m5/util/__init__.py | 8 +- src/python/m5/util/dot_writer.py | 15 +++- src/python/m5/util/dot_writer_ruby.py | 1 + src/python/m5/util/fdthelper.py | 5 +- src/python/m5/util/terminal_formatter.py | 4 +- src/sim/ClockDomain.py | 2 +- src/sim/ClockedObject.py | 2 +- src/sim/DVFSHandler.py | 2 +- src/sim/InstTracer.py | 2 +- src/sim/PowerDomain.py | 2 +- src/sim/PowerState.py | 2 +- src/sim/Process.py | 5 +- src/sim/RedirectPath.py | 2 +- src/sim/Root.py | 2 +- src/sim/SignalPort.py | 5 +- src/sim/SubSystem.py | 2 +- src/sim/System.py | 7 +- src/sim/VoltageDomain.py | 2 +- src/sim/Workload.py | 8 +- src/sim/power/MathExprPowerModel.py | 4 +- src/sim/power/PowerModel.py | 2 +- src/sim/power/PowerModelState.py | 2 +- src/sim/power/ThermalDomain.py | 2 +- src/sim/power/ThermalModel.py | 7 +- src/sim/probe/Probe.py | 2 +- src/systemc/Tlm.py | 5 +- src/systemc/core/SystemC.py | 5 +- src/systemc/python/systemc.py | 10 ++- src/systemc/python/tlm.py | 1 - src/systemc/tests/config.py | 7 +- src/systemc/tlm_bridge/TlmBridge.py | 6 +- tests/gem5/__init__.py | 4 +- .../configs/arm_boot_exit_run.py | 33 +++---- tests/gem5/arm_boot_tests/test_linux_boot.py | 1 - tests/gem5/asmtest/configs/riscv_asmtest.py | 18 ++-- .../configs/arm-hello-restore-checkpoint.py | 17 ++-- .../configs/arm-hello-save-checkpoint.py | 13 +-- .../configs/power-hello-restore-checkpoint.py | 16 ++-- .../configs/power-hello-save-checkpoint.py | 13 +-- .../configs/sparc-hello-restore-checkpoint.py | 16 ++-- .../configs/sparc-hello-save-checkpoint.py | 13 +-- .../configs/x86-fs-restore-checkpoint.py | 11 ++- .../configs/x86-fs-save-checkpoint.py | 7 +- .../configs/x86-hello-restore-checkpoint.py | 16 ++-- .../configs/x86-hello-save-checkpoint.py | 13 +-- .../gem5/checkpoint_tests/test-checkpoints.py | 5 +- tests/gem5/cpu_tests/run.py | 2 +- tests/gem5/fixture.py | 37 +++++--- .../gem5/fs/linux/arm/configs/arm_generic.py | 15 ++-- .../gem5/fs/linux/arm/configs/base_config.py | 17 ++-- tests/gem5/fs/linux/arm/configs/checkpoint.py | 4 +- .../linux/arm/configs/realview-minor-dual.py | 3 +- .../fs/linux/arm/configs/realview-minor.py | 3 +- .../linux/arm/configs/realview-o3-checker.py | 3 +- .../fs/linux/arm/configs/realview-o3-dual.py | 3 +- .../gem5/fs/linux/arm/configs/realview-o3.py | 3 +- .../realview-simple-atomic-checkpoint.py | 5 +- .../configs/realview-simple-atomic-dual.py | 3 +- .../arm/configs/realview-simple-atomic.py | 3 +- .../realview-simple-timing-dual-ruby.py | 3 +- .../configs/realview-simple-timing-dual.py | 3 +- .../configs/realview-simple-timing-ruby.py | 3 +- .../arm/configs/realview-simple-timing.py | 3 +- .../arm/configs/realview-switcheroo-atomic.py | 5 +- .../arm/configs/realview-switcheroo-full.py | 5 +- .../realview-switcheroo-noncaching-timing.py | 5 +- .../arm/configs/realview-switcheroo-o3.py | 5 +- .../arm/configs/realview-switcheroo-timing.py | 5 +- .../linux/arm/configs/realview64-kvm-dual.py | 8 +- .../fs/linux/arm/configs/realview64-kvm.py | 3 +- .../arm/configs/realview64-minor-dual.py | 3 +- .../fs/linux/arm/configs/realview64-minor.py | 3 +- .../arm/configs/realview64-o3-checker.py | 3 +- .../arm/configs/realview64-o3-dual-ruby.py | 3 +- .../linux/arm/configs/realview64-o3-dual.py | 3 +- .../fs/linux/arm/configs/realview64-o3.py | 3 +- .../realview64-simple-atomic-checkpoint.py | 5 +- .../configs/realview64-simple-atomic-dual.py | 3 +- .../arm/configs/realview64-simple-atomic.py | 3 +- .../realview64-simple-timing-dual-ruby.py | 3 +- .../configs/realview64-simple-timing-dual.py | 3 +- .../configs/realview64-simple-timing-ruby.py | 3 +- .../arm/configs/realview64-simple-timing.py | 3 +- .../configs/realview64-switcheroo-atomic.py | 5 +- .../arm/configs/realview64-switcheroo-full.py | 5 +- .../arm/configs/realview64-switcheroo-o3.py | 5 +- .../configs/realview64-switcheroo-timing.py | 5 +- tests/gem5/fs/linux/arm/configs/switcheroo.py | 3 +- tests/gem5/fs/linux/arm/run.py | 2 +- tests/gem5/fs/linux/arm/test.py | 3 +- .../test_gem5_library_examples.py | 5 +- .../gem5_resources/configs/download_check.py | 18 ++-- .../insttest_se/configs/simple_binary_run.py | 40 +++++---- .../configs/boot_kvm_fork_run.py | 6 +- .../configs/boot_kvm_switch_exit.py | 8 +- .../gem5/m5_util/configs/simple_binary_run.py | 41 +++++---- tests/gem5/m5_util/test_exit.py | 1 + .../m5threads_test_atomic/atomic_system.py | 8 +- tests/gem5/m5threads_test_atomic/caches.py | 13 ++- tests/gem5/memory/simple-run.py | 4 +- .../multi_isa/configs/runtime_isa_check.py | 10 ++- .../multi_isa/configs/supported_isa_check.py | 11 ++- .../configs/parsec_disk_run.py | 23 ++--- .../configs/cache_hierarchies.py | 7 +- .../configs/run_replacement_policy.py | 2 +- .../run_replacement_policy.py | 2 +- .../configs/riscv_boot_exit_run.py | 20 +++-- .../gem5/riscv_boot_tests/test_linux_boot.py | 1 - .../hello_se/configs/simple_binary_run.py | 40 +++++---- tests/gem5/se_mode/hello_se/test_hello_se.py | 4 +- tests/gem5/stats/configs/simple_binary_run.py | 40 +++++---- tests/gem5/stats/test_hdf5.py | 3 +- tests/gem5/stdlib/configs/requires_check.py | 11 ++- .../gem5/stdlib/configs/simple_binary_run.py | 40 +++++---- .../configs/simulator_exit_event_run.py | 13 ++- tests/gem5/suite.py | 17 ++-- tests/gem5/to_tick/configs/tick-exit.py | 20 ++--- tests/gem5/to_tick/configs/tick-to-max.py | 18 ++-- .../traffic_gen/configs/simple_traffic_run.py | 9 +- tests/gem5/verifier.py | 9 +- .../configs/x86_boot_exit_run.py | 29 +++---- tests/gem5/x86_boot_tests/test_linux_boot.py | 2 +- tests/main.py | 4 +- tests/pyunit/pyunit_jsonserializable_check.py | 1 + tests/pyunit/stdlib/pyunit_looppoint.py | 9 +- .../resources/pyunit_client_wrapper_checks.py | 14 +-- .../resources/pyunit_json_client_checks.py | 8 +- .../resources/pyunit_local_file_path_check.py | 5 +- .../resources/pyunit_md5_utils_check.py | 9 +- .../pyunit_obtain_resources_check.py | 17 ++-- .../pyunit_resource_specialization.py | 11 +-- .../stdlib/resources/pyunit_suite_checks.py | 11 +-- .../resources/pyunit_workload_checks.py | 19 ++-- tests/pyunit/test_run.py | 1 + tests/run.py | 6 +- util/checkpoint-tester.py | 6 +- util/checkpoint_aggregator.py | 7 +- util/cpt_upgrader.py | 10 ++- util/decode_inst_dep_trace.py | 3 +- util/decode_inst_trace.py | 3 +- util/decode_packet_trace.py | 3 +- util/encode_inst_dep_trace.py | 3 +- util/encode_packet_trace.py | 3 +- util/find_copyrights.py | 5 +- util/gem5-resources-manager/api/client.py | 10 ++- .../api/create_resources_json.py | 5 +- .../gem5-resources-manager/api/json_client.py | 8 +- .../api/mongo_client.py | 17 ++-- .../gem5_resource_cli.py | 11 +-- util/gem5-resources-manager/server.py | 38 ++++---- util/gem5-resources-manager/test/api_test.py | 13 +-- .../test/comprehensive_test.py | 11 +-- .../test/json_client_test.py | 10 +-- .../test/mongo_client_test.py | 12 ++- util/gem5-stubgen.py | 5 +- .../artifact/gem5art/artifact/__init__.py | 4 +- .../artifact/gem5art/artifact/_artifactdb.py | 18 +++- .../artifact/gem5art/artifact/artifact.py | 18 ++-- util/gem5art/artifact/setup.py | 5 +- util/gem5art/artifact/tests/test_artifact.py | 16 ++-- util/gem5art/artifact/tests/test_filedb.py | 2 +- util/gem5art/run/bin/gem5art-getruns | 5 +- util/gem5art/run/gem5art/run.py | 18 +++- util/gem5art/run/setup.py | 5 +- util/gem5art/run/tests/test_run.py | 2 +- util/gem5art/tasks/gem5art/tasks/tasks.py | 3 +- util/gem5art/tasks/setup.py | 5 +- util/gem5img.py | 18 ++-- util/gen_arm_fs_files.py | 14 +-- util/gerrit-bot/bot.py | 13 +-- util/gerrit-bot/gerrit.py | 3 +- util/git-commit-msg.py | 2 +- util/git-pre-commit.py | 15 ++-- util/maint/list_changes.py | 2 +- util/maint/show_changes_by_file.py | 5 +- util/md5.py | 6 +- util/minorview.py | 11 ++- util/minorview/blobs.py | 22 +++-- util/minorview/model.py | 15 ++-- util/minorview/view.py | 24 ++++-- util/o3-pipeview.py | 2 +- util/obtain-resource.py | 3 +- util/on-chip-network-power-area.py | 5 +- util/oprofile-top.py | 5 +- util/plot_dram/PlotPowerStates.py | 7 +- util/plot_dram/dram_lat_mem_rd_plot.py | 4 +- util/plot_dram/dram_sweep_plot.py | 6 +- util/plot_dram/lowp_dram_sweep_plot.py | 3 +- util/slicc | 5 +- util/streamline/m5stats2streamline.py | 17 ++-- util/style.py | 7 +- util/style/repo.py | 2 +- util/style/style.py | 5 +- util/style/verifiers.py | 15 ++-- .../systemc_gem5_tlm/SystemC_Example.py | 8 +- .../systemc_gem5_tlm/config.py | 2 +- .../systemc_sc_main/config.py | 7 +- .../systemc_simple_object/SystemC_Example.py | 3 +- .../systemc_simple_object/config.py | 9 +- .../systemc_within_gem5/systemc_tlm/config.py | 7 +- util/tlm/conf/tlm_elastic_slave.py | 6 +- util/tlm/conf/tlm_master.py | 4 +- .../tlm/examples/tlm_elastic_slave_with_l2.py | 6 +- util/update-copyright.py | 1 - 681 files changed, 3729 insertions(+), 2487 deletions(-) diff --git a/build_tools/cxx_config_cc.py b/build_tools/cxx_config_cc.py index f2b126b463..1a4de0339d 100644 --- a/build_tools/cxx_config_cc.py +++ b/build_tools/cxx_config_cc.py @@ -43,7 +43,6 @@ import os.path import sys import importer - from code_formatter import code_formatter parser = argparse.ArgumentParser() @@ -59,8 +58,8 @@ importer.install() module = importlib.import_module(args.modpath) sim_object = getattr(module, sim_object_name) -from m5.params import isSimObjectClass import m5.params +from m5.params import isSimObjectClass code = code_formatter() diff --git a/build_tools/cxx_config_hh.py b/build_tools/cxx_config_hh.py index 55828e37b7..dfcb02c190 100644 --- a/build_tools/cxx_config_hh.py +++ b/build_tools/cxx_config_hh.py @@ -42,7 +42,6 @@ import os.path import sys import importer - from code_formatter import code_formatter parser = argparse.ArgumentParser() diff --git a/build_tools/enum_cc.py b/build_tools/enum_cc.py index 504a1b9883..7cfd3990b9 100644 --- a/build_tools/enum_cc.py +++ b/build_tools/enum_cc.py @@ -42,7 +42,6 @@ import os.path import sys import importer - from code_formatter import code_formatter parser = argparse.ArgumentParser() diff --git a/build_tools/enum_hh.py b/build_tools/enum_hh.py index f91ffef437..dab47bfa19 100644 --- a/build_tools/enum_hh.py +++ b/build_tools/enum_hh.py @@ -42,7 +42,6 @@ import os.path import sys import importer - from code_formatter import code_formatter parser = argparse.ArgumentParser() diff --git a/build_tools/sim_object_param_struct_cc.py b/build_tools/sim_object_param_struct_cc.py index 2ef90c7420..5aca1b8711 100644 --- a/build_tools/sim_object_param_struct_cc.py +++ b/build_tools/sim_object_param_struct_cc.py @@ -42,7 +42,6 @@ import os.path import sys import importer - from code_formatter import code_formatter parser = argparse.ArgumentParser() diff --git a/build_tools/sim_object_param_struct_hh.py b/build_tools/sim_object_param_struct_hh.py index 45971669f8..c82c25921c 100644 --- a/build_tools/sim_object_param_struct_hh.py +++ b/build_tools/sim_object_param_struct_hh.py @@ -42,7 +42,6 @@ import os.path import sys import importer - from code_formatter import code_formatter parser = argparse.ArgumentParser() diff --git a/configs/common/Benchmarks.py b/configs/common/Benchmarks.py index c90e78ed61..9983a8ea84 100644 --- a/configs/common/Benchmarks.py +++ b/configs/common/Benchmarks.py @@ -24,8 +24,14 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from common.SysPaths import script, disk, binary from os import environ as env + +from common.SysPaths import ( + binary, + disk, + script, +) + from m5.defines import buildEnv diff --git a/configs/common/CacheConfig.py b/configs/common/CacheConfig.py index 7a191570e3..723978f05c 100644 --- a/configs/common/CacheConfig.py +++ b/configs/common/CacheConfig.py @@ -40,14 +40,15 @@ # Configure the M5 cache hierarchy config in one place # +from common import ObjectList +from common.Caches import * + import m5 from m5.objects import * + from gem5.isas import ISA from gem5.runtime import get_runtime_isa -from common.Caches import * -from common import ObjectList - def _get_hwp(hwp_option): if hwp_option == None: diff --git a/configs/common/Caches.py b/configs/common/Caches.py index e25d16ca1e..ac8dc17f7d 100644 --- a/configs/common/Caches.py +++ b/configs/common/Caches.py @@ -39,6 +39,7 @@ from m5.defines import buildEnv from m5.objects import * + from gem5.isas import ISA from gem5.runtime import get_runtime_isa diff --git a/configs/common/CpuConfig.py b/configs/common/CpuConfig.py index 1672d43343..0d132b83b9 100644 --- a/configs/common/CpuConfig.py +++ b/configs/common/CpuConfig.py @@ -33,8 +33,8 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from m5 import fatal import m5.objects +from m5 import fatal def config_etrace(cpu_cls, cpu_list, options): diff --git a/configs/common/FSConfig.py b/configs/common/FSConfig.py index 5da951c93b..469101a82e 100644 --- a/configs/common/FSConfig.py +++ b/configs/common/FSConfig.py @@ -38,12 +38,13 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +from common import ObjectList +from common.Benchmarks import * + import m5 import m5.defines from m5.objects import * from m5.util import * -from common.Benchmarks import * -from common import ObjectList # Populate to reflect supported os types per target ISA os_types = set() diff --git a/configs/common/FileSystemConfig.py b/configs/common/FileSystemConfig.py index 9c6647c861..91d427a259 100644 --- a/configs/common/FileSystemConfig.py +++ b/configs/common/FileSystemConfig.py @@ -36,18 +36,31 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +import getpass +import operator +import os +import platform +from functools import reduce +from os import ( + access, + getpid, + listdir, + makedirs, + mkdir, + stat, +) +from os.path import isdir +from os.path import join as joinpath +from pwd import getpwuid +from shutil import ( + copyfile, + rmtree, +) + import m5 from m5.objects import * from m5.util.convert import * -from functools import reduce -import operator, os, platform, getpass -from os import mkdir, makedirs, getpid, listdir, stat, access -from pwd import getpwuid -from os.path import join as joinpath -from os.path import isdir -from shutil import rmtree, copyfile - def hex_mask(terms): dec_mask = reduce(operator.or_, [2**i for i in terms], 0) diff --git a/configs/common/MemConfig.py b/configs/common/MemConfig.py index 02af2b8449..717ffa5fae 100644 --- a/configs/common/MemConfig.py +++ b/configs/common/MemConfig.py @@ -33,9 +33,12 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +from common import ( + HMC, + ObjectList, +) + import m5.objects -from common import ObjectList -from common import HMC def create_mem_intf(intf, r, i, intlv_bits, intlv_size, xor_low_bit): @@ -174,6 +177,7 @@ def config_mem(options, system): nbr_mem_ctrls = opt_mem_channels import math + from m5.util import fatal intlv_bits = int(math.log(nbr_mem_ctrls, 2)) diff --git a/configs/common/ObjectList.py b/configs/common/ObjectList.py index 7b926efaf5..4a893e4d14 100644 --- a/configs/common/ObjectList.py +++ b/configs/common/ObjectList.py @@ -34,13 +34,15 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from gem5.runtime import get_supported_isas -import m5.objects -import m5.internal.params import inspect import sys from textwrap import TextWrapper +import m5.internal.params +import m5.objects + +from gem5.runtime import get_supported_isas + class ObjectList: """Creates a list of objects that are sub-classes of a given class.""" diff --git a/configs/common/Options.py b/configs/common/Options.py index 8344d9fd44..cd658e33c1 100644 --- a/configs/common/Options.py +++ b/configs/common/Options.py @@ -38,13 +38,13 @@ import argparse +from common import ObjectList +from common.Benchmarks import * + import m5 from m5.defines import buildEnv from m5.objects import * -from common.Benchmarks import * -from common import ObjectList - vio_9p_help = """\ Enable the Virtio 9P device and set the path to share. The default 9p path is m5ou5/9p/share, and it can be changed by setting VirtIO9p.root with --param. A diff --git a/configs/common/SimpleOpts.py b/configs/common/SimpleOpts.py index da78ec977d..7faf092bcd 100644 --- a/configs/common/SimpleOpts.py +++ b/configs/common/SimpleOpts.py @@ -34,12 +34,12 @@ from each class instead of only from the configuration script. # Module-level variable to track if we've called the parse_args function yet called_parse_args = False -# For fatal -import m5 - # import the argument parser from argparse import ArgumentParser +# For fatal +import m5 + # add the args we want to be able to control from the command line parser = ArgumentParser() diff --git a/configs/common/Simulation.py b/configs/common/Simulation.py index a2a04c3610..34825fb415 100644 --- a/configs/common/Simulation.py +++ b/configs/common/Simulation.py @@ -41,8 +41,10 @@ import sys from os import getcwd from os.path import join as joinpath -from common import CpuConfig -from common import ObjectList +from common import ( + CpuConfig, + ObjectList, +) import m5 from m5.defines import buildEnv @@ -128,9 +130,12 @@ def findCptDir(options, cptdir, testsys): the appropriate directory. """ - from os.path import isdir, exists - from os import listdir import re + from os import listdir + from os.path import ( + exists, + isdir, + ) if not isdir(cptdir): fatal("checkpoint dir %s does not exist!", cptdir) diff --git a/configs/common/SysPaths.py b/configs/common/SysPaths.py index 382740e110..f8bd6883fb 100644 --- a/configs/common/SysPaths.py +++ b/configs/common/SysPaths.py @@ -24,7 +24,8 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -import os, sys +import os +import sys config_path = os.path.dirname(os.path.abspath(__file__)) config_root = os.path.dirname(config_path) diff --git a/configs/common/cores/arm/O3_ARM_Etrace.py b/configs/common/cores/arm/O3_ARM_Etrace.py index 3315664cec..b925a86e9d 100644 --- a/configs/common/cores/arm/O3_ARM_Etrace.py +++ b/configs/common/cores/arm/O3_ARM_Etrace.py @@ -34,6 +34,7 @@ # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. from m5.objects import * + from .O3_ARM_v7a import O3_ARM_v7a_3 diff --git a/configs/common/cores/arm/__init__.py b/configs/common/cores/arm/__init__.py index 135b75f802..6c1c7e869f 100644 --- a/configs/common/cores/arm/__init__.py +++ b/configs/common/cores/arm/__init__.py @@ -33,8 +33,8 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from pkgutil import iter_modules from importlib import import_module +from pkgutil import iter_modules _cpu_modules = [name for _, name, ispkg in iter_modules(__path__) if not ispkg] diff --git a/configs/common/cpu2000.py b/configs/common/cpu2000.py index b928152939..40dab5c820 100644 --- a/configs/common/cpu2000.py +++ b/configs/common/cpu2000.py @@ -26,8 +26,15 @@ import os import sys -from os.path import basename, exists, join as joinpath, normpath -from os.path import isdir, isfile, islink +from os.path import ( + basename, + exists, + isdir, + isfile, + islink, +) +from os.path import join as joinpath +from os.path import normpath spec_dist = os.environ.get("M5_CPU2000", "/dist/m5/cpu2000") diff --git a/configs/deprecated/example/fs.py b/configs/deprecated/example/fs.py index ce6eea7623..52354dc3a2 100644 --- a/configs/deprecated/example/fs.py +++ b/configs/deprecated/example/fs.py @@ -45,25 +45,31 @@ import sys import m5 from m5.defines import buildEnv from m5.objects import * -from m5.util import addToPath, fatal, warn +from m5.util import ( + addToPath, + fatal, + warn, +) from m5.util.fdthelper import * + from gem5.isas import ISA from gem5.runtime import get_runtime_isa addToPath("../../") -from ruby import Ruby - +from common import ( + CacheConfig, + CpuConfig, + MemConfig, + ObjectList, + Options, + Simulation, +) +from common.Benchmarks import * +from common.Caches import * from common.FSConfig import * from common.SysPaths import * -from common.Benchmarks import * -from common import Simulation -from common import CacheConfig -from common import CpuConfig -from common import MemConfig -from common import ObjectList -from common.Caches import * -from common import Options +from ruby import Ruby def cmd_line_template(): diff --git a/configs/deprecated/example/se.py b/configs/deprecated/example/se.py index 6e0aa5b919..ad610b05d3 100644 --- a/configs/deprecated/example/se.py +++ b/configs/deprecated/example/se.py @@ -41,30 +41,36 @@ # "m5 test.py" import argparse -import sys import os +import sys import m5 from m5.defines import buildEnv from m5.objects import * from m5.params import NULL -from m5.util import addToPath, fatal, warn +from m5.util import ( + addToPath, + fatal, + warn, +) + from gem5.isas import ISA from gem5.runtime import get_runtime_isa addToPath("../../") -from ruby import Ruby - -from common import Options -from common import Simulation -from common import CacheConfig -from common import CpuConfig -from common import ObjectList -from common import MemConfig -from common.FileSystemConfig import config_filesystem +from common import ( + CacheConfig, + CpuConfig, + MemConfig, + ObjectList, + Options, + Simulation, +) from common.Caches import * from common.cpu2000 import * +from common.FileSystemConfig import config_filesystem +from ruby import Ruby def get_processes(args): diff --git a/configs/dram/lat_mem_rd.py b/configs/dram/lat_mem_rd.py index 639a93dbf6..b632e72b76 100644 --- a/configs/dram/lat_mem_rd.py +++ b/configs/dram/lat_mem_rd.py @@ -33,18 +33,20 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -import gzip import argparse +import gzip import os import m5 from m5.objects import * -from m5.util import addToPath from m5.stats import periodicStatDump +from m5.util import addToPath addToPath("../") -from common import ObjectList -from common import MemConfig +from common import ( + MemConfig, + ObjectList, +) addToPath("../../util") import protolib diff --git a/configs/dram/low_power_sweep.py b/configs/dram/low_power_sweep.py index 7f8591b692..5ef91d0618 100644 --- a/configs/dram/low_power_sweep.py +++ b/configs/dram/low_power_sweep.py @@ -37,13 +37,15 @@ import argparse import m5 from m5.objects import * -from m5.util import addToPath from m5.stats import periodicStatDump +from m5.util import addToPath addToPath("../") -from common import ObjectList -from common import MemConfig +from common import ( + MemConfig, + ObjectList, +) # This script aims at triggering low power state transitions in the DRAM # controller. The traffic generator is used in DRAM mode and traffic diff --git a/configs/dram/sweep.py b/configs/dram/sweep.py index ca7b70d4ed..95190a8ab8 100644 --- a/configs/dram/sweep.py +++ b/configs/dram/sweep.py @@ -33,18 +33,20 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -import math import argparse +import math import m5 from m5.objects import * -from m5.util import addToPath from m5.stats import periodicStatDump +from m5.util import addToPath addToPath("../") -from common import ObjectList -from common import MemConfig +from common import ( + MemConfig, + ObjectList, +) # this script is helpful to sweep the efficiency of a specific memory # controller configuration, by varying the number of banks accessed, diff --git a/configs/example/apu_se.py b/configs/example/apu_se.py index b20779fcdb..219f8f9f29 100644 --- a/configs/example/apu_se.py +++ b/configs/example/apu_se.py @@ -27,28 +27,32 @@ # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE # POSSIBILITY OF SUCH DAMAGE. -import argparse, os, re, getpass -import math +import argparse +import getpass import glob import inspect +import math +import os +import re import m5 from m5.objects import * from m5.util import addToPath + from gem5.isas import ISA from gem5.runtime import get_runtime_isa addToPath("../") -from ruby import Ruby - -from common import Options -from common import Simulation -from common import GPUTLBOptions, GPUTLBConfig - import hsaTopology -from common import FileSystemConfig - +from common import ( + FileSystemConfig, + GPUTLBConfig, + GPUTLBOptions, + Options, + Simulation, +) +from ruby import Ruby # Adding script options parser = argparse.ArgumentParser() diff --git a/configs/example/arm/baremetal.py b/configs/example/arm/baremetal.py index fae85fa04b..a986a2c44d 100644 --- a/configs/example/arm/baremetal.py +++ b/configs/example/arm/baremetal.py @@ -39,24 +39,29 @@ Research Starter Kit on System Modeling. More information can be found at: http://www.arm.com/ResearchEnablement/SystemModeling """ +import argparse import os + import m5 -from m5.util import addToPath from m5.objects import * from m5.options import * +from m5.util import addToPath + from gem5.simulate.exit_event import ExitEvent -import argparse m5.util.addToPath("../..") -from common import SysPaths -from common import MemConfig -from common import ObjectList -from common.cores.arm import HPI -from common.cores.arm import O3_ARM_v7a - import devices import workloads +from common import ( + MemConfig, + ObjectList, + SysPaths, +) +from common.cores.arm import ( + HPI, + O3_ARM_v7a, +) # Pre-defined CPU configurations. Each tuple must be ordered as : (cpu_class, # l1_icache_class, l1_dcache_class, walk_cache_class, l2_Cache_class). Any of diff --git a/configs/example/arm/devices.py b/configs/example/arm/devices.py index 7d92f4ee36..dc62525204 100644 --- a/configs/example/arm/devices.py +++ b/configs/example/arm/devices.py @@ -39,8 +39,8 @@ import m5 from m5.objects import * m5.util.addToPath("../../") -from common.Caches import * from common import ObjectList +from common.Caches import * have_kvm = "ArmV8KvmCPU" in ObjectList.cpu_list.get_names() have_fastmodel = "FastModelCortexA76" in ObjectList.cpu_list.get_names() diff --git a/configs/example/arm/dist_bigLITTLE.py b/configs/example/arm/dist_bigLITTLE.py index 2884a5efd5..f5a816c12a 100644 --- a/configs/example/arm/dist_bigLITTLE.py +++ b/configs/example/arm/dist_bigLITTLE.py @@ -39,11 +39,11 @@ import argparse import os +import fs_bigLITTLE as bL + import m5 from m5.objects import * -import fs_bigLITTLE as bL - m5.util.addToPath("../../dist") import sw diff --git a/configs/example/arm/etrace_se.py b/configs/example/arm/etrace_se.py index 8fa971ff84..1b06ba3fdf 100644 --- a/configs/example/arm/etrace_se.py +++ b/configs/example/arm/etrace_se.py @@ -34,18 +34,18 @@ # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -import os -import m5 -from m5.util import addToPath -from m5.objects import * import argparse +import os import shlex +import m5 +from m5.objects import * +from m5.util import addToPath + m5.util.addToPath("../..") -from common import ObjectList - import devices +from common import ObjectList def get_processes(cmd): diff --git a/configs/example/arm/fs_bigLITTLE.py b/configs/example/arm/fs_bigLITTLE.py index 401eb0c9e7..17e9e6dd28 100644 --- a/configs/example/arm/fs_bigLITTLE.py +++ b/configs/example/arm/fs_bigLITTLE.py @@ -39,21 +39,29 @@ import argparse import os import sys + import m5 import m5.util from m5.objects import * m5.util.addToPath("../../") -from common import FSConfig -from common import SysPaths -from common import ObjectList -from common import Options -from common.cores.arm import ex5_big, ex5_LITTLE - import devices -from devices import AtomicCluster, KvmCluster, FastmodelCluster - +from common import ( + FSConfig, + ObjectList, + Options, + SysPaths, +) +from common.cores.arm import ( + ex5_big, + ex5_LITTLE, +) +from devices import ( + AtomicCluster, + FastmodelCluster, + KvmCluster, +) default_disk = "aarch64-ubuntu-trusty-headless.img" @@ -410,7 +418,8 @@ def build(options): system.generateDtb(system.workload.dtb_filename) if devices.have_fastmodel and issubclass(big_model, FastmodelCluster): - from m5 import arm_fast_model as fm, systemc as sc + from m5 import arm_fast_model as fm + from m5 import systemc as sc # setup FastModels for simulation fm.setup_simulation("cortexa76") diff --git a/configs/example/arm/fs_power.py b/configs/example/arm/fs_power.py index 0442682411..83e43eef66 100644 --- a/configs/example/arm/fs_power.py +++ b/configs/example/arm/fs_power.py @@ -39,11 +39,14 @@ import argparse import os -import m5 -from m5.objects import MathExprPowerModel, PowerModel - import fs_bigLITTLE as bL +import m5 +from m5.objects import ( + MathExprPowerModel, + PowerModel, +) + class CpuPowerOn(MathExprPowerModel): def __init__(self, cpu_path, **kwargs): diff --git a/configs/example/arm/ruby_fs.py b/configs/example/arm/ruby_fs.py index 67a8a6e0b3..a0979c1ced 100644 --- a/configs/example/arm/ruby_fs.py +++ b/configs/example/arm/ruby_fs.py @@ -33,24 +33,28 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +import argparse import os + import m5 -from m5.util import addToPath from m5.objects import * from m5.options import * -import argparse +from m5.util import addToPath m5.util.addToPath("../..") -from common import MemConfig -from common import ObjectList -from common import Options -from common import SysPaths -from common.cores.arm import O3_ARM_v7a, HPI -from ruby import Ruby - import devices - +from common import ( + MemConfig, + ObjectList, + Options, + SysPaths, +) +from common.cores.arm import ( + HPI, + O3_ARM_v7a, +) +from ruby import Ruby default_kernel = "vmlinux.arm64" default_disk = "linaro-minimal-aarch64.img" diff --git a/configs/example/arm/starter_fs.py b/configs/example/arm/starter_fs.py index 07280bd204..44f72a6291 100644 --- a/configs/example/arm/starter_fs.py +++ b/configs/example/arm/starter_fs.py @@ -38,22 +38,26 @@ Research Starter Kit on System Modeling. More information can be found at: http://www.arm.com/ResearchEnablement/SystemModeling """ +import argparse import os + import m5 -from m5.util import addToPath from m5.objects import * from m5.options import * -import argparse +from m5.util import addToPath m5.util.addToPath("../..") -from common import SysPaths -from common import ObjectList -from common import MemConfig -from common.cores.arm import O3_ARM_v7a, HPI - import devices - +from common import ( + MemConfig, + ObjectList, + SysPaths, +) +from common.cores.arm import ( + HPI, + O3_ARM_v7a, +) default_kernel = "vmlinux.arm64" default_disk = "linaro-minimal-aarch64.img" diff --git a/configs/example/arm/starter_se.py b/configs/example/arm/starter_se.py index 9834487155..33cf7b2f40 100644 --- a/configs/example/arm/starter_se.py +++ b/configs/example/arm/starter_se.py @@ -38,21 +38,22 @@ Research Starter Kit on System Modeling. More information can be found at: http://www.arm.com/ResearchEnablement/SystemModeling """ -import os -import m5 -from m5.util import addToPath -from m5.objects import * import argparse +import os import shlex +import m5 +from m5.objects import * +from m5.util import addToPath + m5.util.addToPath("../..") -from common import ObjectList -from common import MemConfig -from common.cores.arm import HPI - import devices - +from common import ( + MemConfig, + ObjectList, +) +from common.cores.arm import HPI # Pre-defined CPU configurations. Each tuple must be ordered as : (cpu_class, # l1_icache_class, l1_dcache_class, walk_cache_class, l2_Cache_class). Any of diff --git a/configs/example/arm/workloads.py b/configs/example/arm/workloads.py index d7aea2ca0a..d84657712e 100644 --- a/configs/example/arm/workloads.py +++ b/configs/example/arm/workloads.py @@ -35,13 +35,17 @@ # import inspect + +from common.ObjectList import ObjectList +from common.SysPaths import ( + binary, + disk, +) + import m5 from m5.objects import * from m5.options import * -from common.ObjectList import ObjectList -from common.SysPaths import binary, disk - class ArmBaremetal(ArmFsWorkload): """Baremetal workload""" diff --git a/configs/example/dramsys.py b/configs/example/dramsys.py index 0e8bebfb75..191e1937f7 100755 --- a/configs/example/dramsys.py +++ b/configs/example/dramsys.py @@ -25,7 +25,6 @@ # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. import m5 - from m5.objects import * traffic_gen = PyTrafficGen() diff --git a/configs/example/etrace_replay.py b/configs/example/etrace_replay.py index 184934fab9..7df1333f2b 100644 --- a/configs/example/etrace_replay.py +++ b/configs/example/etrace_replay.py @@ -37,13 +37,18 @@ import argparse -from m5.util import addToPath, fatal +from m5.util import ( + addToPath, + fatal, +) addToPath("../") -from common import Options -from common import Simulation -from common import MemConfig +from common import ( + MemConfig, + Options, + Simulation, +) from common.Caches import * diff --git a/configs/example/garnet_synth_traffic.py b/configs/example/garnet_synth_traffic.py index 1da82e11b8..8bbacd7a8e 100644 --- a/configs/example/garnet_synth_traffic.py +++ b/configs/example/garnet_synth_traffic.py @@ -26,11 +26,14 @@ # # Author: Tushar Krishna +import argparse +import os +import sys + import m5 -from m5.objects import * from m5.defines import buildEnv +from m5.objects import * from m5.util import addToPath -import os, argparse, sys addToPath("../") diff --git a/configs/example/gem5_library/arm-hello.py b/configs/example/gem5_library/arm-hello.py index 721d71c2cb..39583463e7 100644 --- a/configs/example/gem5_library/arm-hello.py +++ b/configs/example/gem5_library/arm-hello.py @@ -41,15 +41,15 @@ scons build/ARM/gem5.opt ``` """ -from gem5.isas import ISA -from gem5.utils.requires import requires -from gem5.resources.resource import obtain_resource -from gem5.components.memory import SingleChannelDDR3_1600 -from gem5.components.processors.cpu_types import CPUTypes from gem5.components.boards.simple_board import SimpleBoard from gem5.components.cachehierarchies.classic.no_cache import NoCache +from gem5.components.memory import SingleChannelDDR3_1600 +from gem5.components.processors.cpu_types import CPUTypes from gem5.components.processors.simple_processor import SimpleProcessor +from gem5.isas import ISA +from gem5.resources.resource import obtain_resource from gem5.simulate.simulator import Simulator +from gem5.utils.requires import requires # This check ensures the gem5 binary is compiled to the ARM ISA target. If not, # an exception will be thrown. diff --git a/configs/example/gem5_library/arm-ubuntu-run.py b/configs/example/gem5_library/arm-ubuntu-run.py index 78160c9976..734fb9ee1b 100644 --- a/configs/example/gem5_library/arm-ubuntu-run.py +++ b/configs/example/gem5_library/arm-ubuntu-run.py @@ -40,18 +40,20 @@ scons build/ARM/gem5.opt -j """ -from gem5.isas import ISA -from m5.objects import ArmDefaultRelease -from gem5.utils.requires import requires -from gem5.resources.resource import obtain_resource -from gem5.simulate.simulator import Simulator -from m5.objects import VExpress_GEM5_Foundation +from m5.objects import ( + ArmDefaultRelease, + VExpress_GEM5_Foundation, +) + from gem5.coherence_protocol import CoherenceProtocol from gem5.components.boards.arm_board import ArmBoard from gem5.components.memory import DualChannelDDR4_2400 from gem5.components.processors.cpu_types import CPUTypes from gem5.components.processors.simple_processor import SimpleProcessor - +from gem5.isas import ISA +from gem5.resources.resource import obtain_resource +from gem5.simulate.simulator import Simulator +from gem5.utils.requires import requires # This runs a check to ensure the gem5 binary is compiled for ARM and the # protocol is CHI. diff --git a/configs/example/gem5_library/caches/octopi-cache-example.py b/configs/example/gem5_library/caches/octopi-cache-example.py index 4a4926a174..fa19773167 100644 --- a/configs/example/gem5_library/caches/octopi-cache-example.py +++ b/configs/example/gem5_library/caches/octopi-cache-example.py @@ -38,20 +38,23 @@ scons build/ARM_MESI_Three_Level/gem5.opt -j `nproc` """ -from m5.objects import ArmDefaultRelease, VExpress_GEM5_Foundation +from m5.objects import ( + ArmDefaultRelease, + VExpress_GEM5_Foundation, +) -from gem5.utils.requires import requires +from gem5.coherence_protocol import CoherenceProtocol from gem5.components.boards.arm_board import ArmBoard -from gem5.components.memory import DualChannelDDR4_2400 -from gem5.components.processors.simple_processor import SimpleProcessor -from gem5.components.processors.cpu_types import CPUTypes from gem5.components.cachehierarchies.ruby.caches.mesi_three_level.octopi import ( OctopiCache, ) +from gem5.components.memory import DualChannelDDR4_2400 +from gem5.components.processors.cpu_types import CPUTypes +from gem5.components.processors.simple_processor import SimpleProcessor from gem5.isas import ISA -from gem5.coherence_protocol import CoherenceProtocol -from gem5.simulate.simulator import Simulator from gem5.resources.resource import obtain_resource +from gem5.simulate.simulator import Simulator +from gem5.utils.requires import requires num_ccds = 1 # CCDs num_cores_per_ccd = 8 # 8 cores/CCD diff --git a/configs/example/gem5_library/checkpoints/riscv-hello-restore-checkpoint.py b/configs/example/gem5_library/checkpoints/riscv-hello-restore-checkpoint.py index eed76e2448..aa78de5647 100644 --- a/configs/example/gem5_library/checkpoints/riscv-hello-restore-checkpoint.py +++ b/configs/example/gem5_library/checkpoints/riscv-hello-restore-checkpoint.py @@ -46,15 +46,15 @@ scons build/RISCV/gem5.opt ``` """ -from gem5.isas import ISA -from gem5.utils.requires import requires -from gem5.resources.resource import obtain_resource -from gem5.components.memory import SingleChannelDDR3_1600 -from gem5.components.processors.cpu_types import CPUTypes from gem5.components.boards.simple_board import SimpleBoard from gem5.components.cachehierarchies.classic.no_cache import NoCache +from gem5.components.memory import SingleChannelDDR3_1600 +from gem5.components.processors.cpu_types import CPUTypes from gem5.components.processors.simple_processor import SimpleProcessor +from gem5.isas import ISA +from gem5.resources.resource import obtain_resource from gem5.simulate.simulator import Simulator +from gem5.utils.requires import requires # This check ensures the gem5 binary is compiled to the RISCV ISA target. # If not, an exception will be thrown. diff --git a/configs/example/gem5_library/checkpoints/riscv-hello-save-checkpoint.py b/configs/example/gem5_library/checkpoints/riscv-hello-save-checkpoint.py index 234153a57f..b024a3a44a 100644 --- a/configs/example/gem5_library/checkpoints/riscv-hello-save-checkpoint.py +++ b/configs/example/gem5_library/checkpoints/riscv-hello-save-checkpoint.py @@ -44,15 +44,16 @@ scons build/RISCV/gem5.opt """ import argparse -from gem5.isas import ISA -from gem5.utils.requires import requires -from gem5.resources.resource import obtain_resource -from gem5.components.memory import SingleChannelDDR3_1600 -from gem5.components.processors.cpu_types import CPUTypes + from gem5.components.boards.simple_board import SimpleBoard from gem5.components.cachehierarchies.classic.no_cache import NoCache +from gem5.components.memory import SingleChannelDDR3_1600 +from gem5.components.processors.cpu_types import CPUTypes from gem5.components.processors.simple_processor import SimpleProcessor +from gem5.isas import ISA +from gem5.resources.resource import obtain_resource from gem5.simulate.simulator import Simulator +from gem5.utils.requires import requires parser = argparse.ArgumentParser() diff --git a/configs/example/gem5_library/checkpoints/simpoints-se-checkpoint.py b/configs/example/gem5_library/checkpoints/simpoints-se-checkpoint.py index 5787bf4bfc..4649f4a07e 100644 --- a/configs/example/gem5_library/checkpoints/simpoints-se-checkpoint.py +++ b/configs/example/gem5_library/checkpoints/simpoints-se-checkpoint.py @@ -48,22 +48,23 @@ scons build/X86/gem5.opt """ import argparse +from pathlib import Path +from gem5.components.boards.simple_board import SimpleBoard +from gem5.components.cachehierarchies.classic.no_cache import NoCache +from gem5.components.memory.single_channel import SingleChannelDDR3_1600 +from gem5.components.processors.cpu_types import CPUTypes +from gem5.components.processors.simple_processor import SimpleProcessor +from gem5.isas import ISA +from gem5.resources.resource import ( + SimpointResource, + obtain_resource, +) +from gem5.resources.workload import Workload from gem5.simulate.exit_event import ExitEvent +from gem5.simulate.exit_event_generators import save_checkpoint_generator from gem5.simulate.simulator import Simulator from gem5.utils.requires import requires -from gem5.components.boards.simple_board import SimpleBoard -from gem5.components.memory.single_channel import SingleChannelDDR3_1600 -from gem5.components.processors.simple_processor import SimpleProcessor -from gem5.components.processors.cpu_types import CPUTypes -from gem5.isas import ISA -from gem5.resources.workload import Workload -from gem5.resources.resource import obtain_resource, SimpointResource -from pathlib import Path -from gem5.components.cachehierarchies.classic.no_cache import NoCache -from gem5.simulate.exit_event_generators import ( - save_checkpoint_generator, -) requires(isa_required=ISA.X86) diff --git a/configs/example/gem5_library/checkpoints/simpoints-se-restore.py b/configs/example/gem5_library/checkpoints/simpoints-se-restore.py index d063c143a7..284289be6f 100644 --- a/configs/example/gem5_library/checkpoints/simpoints-se-restore.py +++ b/configs/example/gem5_library/checkpoints/simpoints-se-restore.py @@ -52,23 +52,29 @@ scons build/X86/gem5.opt """ -from gem5.simulate.exit_event import ExitEvent -from gem5.simulate.simulator import Simulator -from gem5.utils.requires import requires +from pathlib import Path + +from m5.stats import ( + dump, + reset, +) + +from gem5.components.boards.simple_board import SimpleBoard from gem5.components.cachehierarchies.classic.private_l1_private_l2_cache_hierarchy import ( PrivateL1PrivateL2CacheHierarchy, ) -from gem5.components.boards.simple_board import SimpleBoard from gem5.components.memory import DualChannelDDR4_2400 -from gem5.components.processors.simple_processor import SimpleProcessor from gem5.components.processors.cpu_types import CPUTypes +from gem5.components.processors.simple_processor import SimpleProcessor from gem5.isas import ISA -from gem5.resources.resource import SimpointResource, obtain_resource +from gem5.resources.resource import ( + SimpointResource, + obtain_resource, +) from gem5.resources.workload import Workload -from gem5.resources.resource import SimpointResource - -from pathlib import Path -from m5.stats import reset, dump +from gem5.simulate.exit_event import ExitEvent +from gem5.simulate.simulator import Simulator +from gem5.utils.requires import requires requires(isa_required=ISA.X86) diff --git a/configs/example/gem5_library/dramsys/arm-hello-dramsys.py b/configs/example/gem5_library/dramsys/arm-hello-dramsys.py index ae2b4bb5b6..2561f98fae 100644 --- a/configs/example/gem5_library/dramsys/arm-hello-dramsys.py +++ b/configs/example/gem5_library/dramsys/arm-hello-dramsys.py @@ -33,17 +33,17 @@ DRRAMSys simulator. Please consult 'ext/dramsys/README' on how to compile correctly. If this is not done correctly this script will run with error. """ -from gem5.isas import ISA -from gem5.utils.requires import requires -from gem5.resources.resource import obtain_resource -from gem5.components.memory import DRAMSysDDR3_1600 -from gem5.components.processors.cpu_types import CPUTypes from gem5.components.boards.simple_board import SimpleBoard from gem5.components.cachehierarchies.classic.private_l1_cache_hierarchy import ( PrivateL1CacheHierarchy, ) +from gem5.components.memory import DRAMSysDDR3_1600 +from gem5.components.processors.cpu_types import CPUTypes from gem5.components.processors.simple_processor import SimpleProcessor +from gem5.isas import ISA +from gem5.resources.resource import obtain_resource from gem5.simulate.simulator import Simulator +from gem5.utils.requires import requires # This check ensures the gem5 binary is compiled to the ARM ISA target. If not, # an exception will be thrown. diff --git a/configs/example/gem5_library/dramsys/dramsys-traffic.py b/configs/example/gem5_library/dramsys/dramsys-traffic.py index 2f9b768696..cc10dd0657 100644 --- a/configs/example/gem5_library/dramsys/dramsys-traffic.py +++ b/configs/example/gem5_library/dramsys/dramsys-traffic.py @@ -32,8 +32,8 @@ DRRAMSys simulator. Please consult 'ext/dramsys/README' on how to compile correctly. If this is not done correctly this script will run with error. """ -from gem5.components.memory.dramsys import DRAMSysMem from gem5.components.boards.test_board import TestBoard +from gem5.components.memory.dramsys import DRAMSysMem from gem5.components.processors.linear_generator import LinearGenerator from gem5.simulate.simulator import Simulator diff --git a/configs/example/gem5_library/looppoints/create-looppoint-checkpoints.py b/configs/example/gem5_library/looppoints/create-looppoint-checkpoints.py index 4a15da55ff..b31353c681 100644 --- a/configs/example/gem5_library/looppoints/create-looppoint-checkpoints.py +++ b/configs/example/gem5_library/looppoints/create-looppoint-checkpoints.py @@ -47,22 +47,22 @@ scons build/X86/gem5.opt ``` """ -from gem5.simulate.exit_event import ExitEvent -from gem5.simulate.simulator import Simulator -from gem5.utils.requires import requires -from gem5.components.cachehierarchies.classic.no_cache import NoCache +import argparse +from pathlib import Path + from gem5.components.boards.simple_board import SimpleBoard +from gem5.components.cachehierarchies.classic.no_cache import NoCache from gem5.components.memory.single_channel import SingleChannelDDR3_1600 -from gem5.components.processors.simple_processor import SimpleProcessor from gem5.components.processors.cpu_types import CPUTypes +from gem5.components.processors.simple_processor import SimpleProcessor from gem5.isas import ISA from gem5.resources.resource import obtain_resource -from pathlib import Path +from gem5.simulate.exit_event import ExitEvent from gem5.simulate.exit_event_generators import ( looppoint_save_checkpoint_generator, ) - -import argparse +from gem5.simulate.simulator import Simulator +from gem5.utils.requires import requires requires(isa_required=ISA.X86) diff --git a/configs/example/gem5_library/looppoints/restore-looppoint-checkpoint.py b/configs/example/gem5_library/looppoints/restore-looppoint-checkpoint.py index 4ca6ad495e..781b2f7281 100644 --- a/configs/example/gem5_library/looppoints/restore-looppoint-checkpoint.py +++ b/configs/example/gem5_library/looppoints/restore-looppoint-checkpoint.py @@ -42,19 +42,23 @@ Usage """ import argparse -from gem5.simulate.exit_event import ExitEvent -from gem5.simulate.simulator import Simulator -from gem5.utils.requires import requires +from m5.stats import ( + dump, + reset, +) + +from gem5.components.boards.simple_board import SimpleBoard from gem5.components.cachehierarchies.classic.private_l1_private_l2_cache_hierarchy import ( PrivateL1PrivateL2CacheHierarchy, ) -from gem5.components.boards.simple_board import SimpleBoard from gem5.components.memory import DualChannelDDR4_2400 -from gem5.components.processors.simple_processor import SimpleProcessor from gem5.components.processors.cpu_types import CPUTypes +from gem5.components.processors.simple_processor import SimpleProcessor from gem5.isas import ISA from gem5.resources.resource import obtain_resource -from m5.stats import reset, dump +from gem5.simulate.exit_event import ExitEvent +from gem5.simulate.simulator import Simulator +from gem5.utils.requires import requires requires(isa_required=ISA.X86) diff --git a/configs/example/gem5_library/memory_traffic.py b/configs/example/gem5_library/memory_traffic.py index d6772d1e77..4c653114fb 100644 --- a/configs/example/gem5_library/memory_traffic.py +++ b/configs/example/gem5_library/memory_traffic.py @@ -36,14 +36,12 @@ and this channel is driven with 32GiB/s of traffic for 1ms. import argparse from m5.objects import MemorySize -from gem5.components.boards.test_board import TestBoard +from gem5.components.boards.test_board import TestBoard +from gem5.components.memory.dram_interfaces.hbm import HBM_2000_4H_1x64 +from gem5.components.memory.hbm import HighBandwidthMemory from gem5.components.processors.linear_generator import LinearGenerator from gem5.components.processors.random_generator import RandomGenerator - -from gem5.components.memory.hbm import HighBandwidthMemory -from gem5.components.memory.dram_interfaces.hbm import HBM_2000_4H_1x64 - from gem5.simulate.simulator import Simulator diff --git a/configs/example/gem5_library/power-hello.py b/configs/example/gem5_library/power-hello.py index 59020643e0..8a73b6a201 100644 --- a/configs/example/gem5_library/power-hello.py +++ b/configs/example/gem5_library/power-hello.py @@ -41,15 +41,15 @@ scons build/POWER/gem5.opt ``` """ -from gem5.isas import ISA -from gem5.utils.requires import requires -from gem5.resources.resource import obtain_resource -from gem5.components.memory import SingleChannelDDR4_2400 -from gem5.components.processors.cpu_types import CPUTypes from gem5.components.boards.simple_board import SimpleBoard from gem5.components.cachehierarchies.classic.no_cache import NoCache +from gem5.components.memory import SingleChannelDDR4_2400 +from gem5.components.processors.cpu_types import CPUTypes from gem5.components.processors.simple_processor import SimpleProcessor +from gem5.isas import ISA +from gem5.resources.resource import obtain_resource from gem5.simulate.simulator import Simulator +from gem5.utils.requires import requires # This check ensures the gem5 binary is compiled to the POWER ISA target. # If not, an exception will be thrown. diff --git a/configs/example/gem5_library/riscv-fs.py b/configs/example/gem5_library/riscv-fs.py index 8a0de6c688..914d9a7023 100644 --- a/configs/example/gem5_library/riscv-fs.py +++ b/configs/example/gem5_library/riscv-fs.py @@ -40,16 +40,16 @@ Characteristics """ from gem5.components.boards.riscv_board import RiscvBoard -from gem5.components.memory import SingleChannelDDR3_1600 -from gem5.components.processors.simple_processor import SimpleProcessor from gem5.components.cachehierarchies.classic.private_l1_private_l2_cache_hierarchy import ( PrivateL1PrivateL2CacheHierarchy, ) +from gem5.components.memory import SingleChannelDDR3_1600 from gem5.components.processors.cpu_types import CPUTypes +from gem5.components.processors.simple_processor import SimpleProcessor from gem5.isas import ISA -from gem5.utils.requires import requires from gem5.resources.resource import obtain_resource from gem5.simulate.simulator import Simulator +from gem5.utils.requires import requires # Run a check to ensure the right version of gem5 is being used. requires(isa_required=ISA.RISCV) diff --git a/configs/example/gem5_library/riscv-ubuntu-run.py b/configs/example/gem5_library/riscv-ubuntu-run.py index 9b172fd501..1d31b055de 100644 --- a/configs/example/gem5_library/riscv-ubuntu-run.py +++ b/configs/example/gem5_library/riscv-ubuntu-run.py @@ -43,14 +43,14 @@ scons build/RISCV/gem5.opt import m5 from m5.objects import Root -from gem5.utils.requires import requires from gem5.components.boards.riscv_board import RiscvBoard from gem5.components.memory import DualChannelDDR4_2400 -from gem5.components.processors.simple_processor import SimpleProcessor from gem5.components.processors.cpu_types import CPUTypes +from gem5.components.processors.simple_processor import SimpleProcessor from gem5.isas import ISA -from gem5.simulate.simulator import Simulator from gem5.resources.resource import obtain_resource +from gem5.simulate.simulator import Simulator +from gem5.utils.requires import requires # This runs a check to ensure the gem5 binary is compiled for RISCV. diff --git a/configs/example/gem5_library/riscvmatched-fs.py b/configs/example/gem5_library/riscvmatched-fs.py index 29ec76e16b..ad045cac3d 100644 --- a/configs/example/gem5_library/riscvmatched-fs.py +++ b/configs/example/gem5_library/riscvmatched-fs.py @@ -38,14 +38,14 @@ scons build/RISCV/gem5.opt ``` """ -from gem5.prebuilt.riscvmatched.riscvmatched_board import RISCVMatchedBoard -from gem5.utils.requires import requires -from gem5.isas import ISA -from gem5.simulate.simulator import Simulator -from gem5.resources.resource import obtain_resource - import argparse +from gem5.isas import ISA +from gem5.prebuilt.riscvmatched.riscvmatched_board import RISCVMatchedBoard +from gem5.resources.resource import obtain_resource +from gem5.simulate.simulator import Simulator +from gem5.utils.requires import requires + requires(isa_required=ISA.RISCV) parser = argparse.ArgumentParser( diff --git a/configs/example/gem5_library/riscvmatched-hello.py b/configs/example/gem5_library/riscvmatched-hello.py index a11ec39159..3ea13b4851 100644 --- a/configs/example/gem5_library/riscvmatched-hello.py +++ b/configs/example/gem5_library/riscvmatched-hello.py @@ -37,10 +37,10 @@ scons build/RISCV/gem5.opt ``` """ +from gem5.isas import ISA +from gem5.prebuilt.riscvmatched.riscvmatched_board import RISCVMatchedBoard from gem5.resources.resource import obtain_resource from gem5.simulate.simulator import Simulator -from gem5.prebuilt.riscvmatched.riscvmatched_board import RISCVMatchedBoard -from gem5.isas import ISA from gem5.utils.requires import requires requires(isa_required=ISA.RISCV) diff --git a/configs/example/gem5_library/riscvmatched-microbenchmark-suite.py b/configs/example/gem5_library/riscvmatched-microbenchmark-suite.py index 7e08355e31..2024bdddf0 100644 --- a/configs/example/gem5_library/riscvmatched-microbenchmark-suite.py +++ b/configs/example/gem5_library/riscvmatched-microbenchmark-suite.py @@ -33,10 +33,10 @@ The print statements in the script are for illustrative purposes only, and are not required to run the script. """ +from gem5.isas import ISA +from gem5.prebuilt.riscvmatched.riscvmatched_board import RISCVMatchedBoard from gem5.resources.resource import obtain_resource from gem5.simulate.simulator import Simulator -from gem5.prebuilt.riscvmatched.riscvmatched_board import RISCVMatchedBoard -from gem5.isas import ISA from gem5.utils.requires import requires requires(isa_required=ISA.RISCV) diff --git a/configs/example/gem5_library/x86-gapbs-benchmarks.py b/configs/example/gem5_library/x86-gapbs-benchmarks.py index c20d2ea4cc..d425d797a6 100644 --- a/configs/example/gem5_library/x86-gapbs-benchmarks.py +++ b/configs/example/gem5_library/x86-gapbs-benchmarks.py @@ -48,24 +48,24 @@ scons build/X86/gem5.opt """ import argparse -import time import sys +import time import m5 from m5.objects import Root -from gem5.utils.requires import requires +from gem5.coherence_protocol import CoherenceProtocol from gem5.components.boards.x86_board import X86Board from gem5.components.memory import DualChannelDDR4_2400 +from gem5.components.processors.cpu_types import CPUTypes from gem5.components.processors.simple_switchable_processor import ( SimpleSwitchableProcessor, ) -from gem5.components.processors.cpu_types import CPUTypes from gem5.isas import ISA -from gem5.coherence_protocol import CoherenceProtocol from gem5.resources.resource import obtain_resource -from gem5.simulate.simulator import Simulator from gem5.simulate.exit_event import ExitEvent +from gem5.simulate.simulator import Simulator +from gem5.utils.requires import requires requires( isa_required=ISA.X86, diff --git a/configs/example/gem5_library/x86-npb-benchmarks.py b/configs/example/gem5_library/x86-npb-benchmarks.py index bcc48382ac..c78c6102aa 100644 --- a/configs/example/gem5_library/x86-npb-benchmarks.py +++ b/configs/example/gem5_library/x86-npb-benchmarks.py @@ -50,22 +50,23 @@ import time import m5 from m5.objects import Root +from m5.stats.gem5stats import get_simstat +from m5.util import warn -from gem5.utils.requires import requires +from gem5.coherence_protocol import CoherenceProtocol from gem5.components.boards.x86_board import X86Board from gem5.components.memory import DualChannelDDR4_2400 +from gem5.components.processors.cpu_types import CPUTypes from gem5.components.processors.simple_switchable_processor import ( SimpleSwitchableProcessor, ) -from gem5.components.processors.cpu_types import CPUTypes from gem5.isas import ISA -from gem5.coherence_protocol import CoherenceProtocol from gem5.resources.resource import obtain_resource -from gem5.simulate.simulator import Simulator -from gem5.simulate.simulator import ExitEvent - -from m5.stats.gem5stats import get_simstat -from m5.util import warn +from gem5.simulate.simulator import ( + ExitEvent, + Simulator, +) +from gem5.utils.requires import requires requires( isa_required=ISA.X86, diff --git a/configs/example/gem5_library/x86-parsec-benchmarks.py b/configs/example/gem5_library/x86-parsec-benchmarks.py index 5e855b773f..71cfd4a9ef 100644 --- a/configs/example/gem5_library/x86-parsec-benchmarks.py +++ b/configs/example/gem5_library/x86-parsec-benchmarks.py @@ -50,18 +50,18 @@ import time import m5 from m5.objects import Root -from gem5.utils.requires import requires +from gem5.coherence_protocol import CoherenceProtocol from gem5.components.boards.x86_board import X86Board from gem5.components.memory import DualChannelDDR4_2400 +from gem5.components.processors.cpu_types import CPUTypes from gem5.components.processors.simple_switchable_processor import ( SimpleSwitchableProcessor, ) -from gem5.components.processors.cpu_types import CPUTypes from gem5.isas import ISA -from gem5.coherence_protocol import CoherenceProtocol from gem5.resources.resource import obtain_resource -from gem5.simulate.simulator import Simulator from gem5.simulate.exit_event import ExitEvent +from gem5.simulate.simulator import Simulator +from gem5.utils.requires import requires # We check for the required gem5 build. diff --git a/configs/example/gem5_library/x86-spec-cpu2006-benchmarks.py b/configs/example/gem5_library/x86-spec-cpu2006-benchmarks.py index 63a7b6b236..18bac9671d 100644 --- a/configs/example/gem5_library/x86-spec-cpu2006-benchmarks.py +++ b/configs/example/gem5_library/x86-spec-cpu2006-benchmarks.py @@ -49,29 +49,33 @@ scons build/X86/gem5.opt """ import argparse -import time -import os import json +import os +import time import m5 from m5.objects import Root +from m5.stats.gem5stats import get_simstat +from m5.util import ( + fatal, + warn, +) -from gem5.utils.requires import requires +from gem5.coherence_protocol import CoherenceProtocol from gem5.components.boards.x86_board import X86Board from gem5.components.memory import DualChannelDDR4_2400 +from gem5.components.processors.cpu_types import CPUTypes from gem5.components.processors.simple_switchable_processor import ( SimpleSwitchableProcessor, ) -from gem5.components.processors.cpu_types import CPUTypes from gem5.isas import ISA -from gem5.coherence_protocol import CoherenceProtocol -from gem5.resources.resource import Resource, DiskImageResource -from gem5.simulate.simulator import Simulator +from gem5.resources.resource import ( + DiskImageResource, + Resource, +) from gem5.simulate.exit_event import ExitEvent - -from m5.stats.gem5stats import get_simstat -from m5.util import warn -from m5.util import fatal +from gem5.simulate.simulator import Simulator +from gem5.utils.requires import requires # We check for the required gem5 build. diff --git a/configs/example/gem5_library/x86-spec-cpu2017-benchmarks.py b/configs/example/gem5_library/x86-spec-cpu2017-benchmarks.py index 348c26f1ff..96c4a37c9e 100644 --- a/configs/example/gem5_library/x86-spec-cpu2017-benchmarks.py +++ b/configs/example/gem5_library/x86-spec-cpu2017-benchmarks.py @@ -47,29 +47,33 @@ scons build/X86/gem5.opt """ import argparse -import time -import os import json +import os +import time import m5 from m5.objects import Root +from m5.stats.gem5stats import get_simstat +from m5.util import ( + fatal, + warn, +) -from gem5.utils.requires import requires +from gem5.coherence_protocol import CoherenceProtocol from gem5.components.boards.x86_board import X86Board from gem5.components.memory import DualChannelDDR4_2400 +from gem5.components.processors.cpu_types import CPUTypes from gem5.components.processors.simple_switchable_processor import ( SimpleSwitchableProcessor, ) -from gem5.components.processors.cpu_types import CPUTypes from gem5.isas import ISA -from gem5.coherence_protocol import CoherenceProtocol -from gem5.resources.resource import obtain_resource, DiskImageResource -from gem5.simulate.simulator import Simulator +from gem5.resources.resource import ( + DiskImageResource, + obtain_resource, +) from gem5.simulate.exit_event import ExitEvent - -from m5.stats.gem5stats import get_simstat -from m5.util import warn -from m5.util import fatal +from gem5.simulate.simulator import Simulator +from gem5.utils.requires import requires # We check for the required gem5 build. diff --git a/configs/example/gem5_library/x86-ubuntu-run-with-kvm-no-perf.py b/configs/example/gem5_library/x86-ubuntu-run-with-kvm-no-perf.py index 233efd92b8..632b409b16 100644 --- a/configs/example/gem5_library/x86-ubuntu-run-with-kvm-no-perf.py +++ b/configs/example/gem5_library/x86-ubuntu-run-with-kvm-no-perf.py @@ -38,21 +38,21 @@ scons build/X86/gem5.opt -j`nproc` ``` """ -from gem5.utils.requires import requires +from gem5.coherence_protocol import CoherenceProtocol from gem5.components.boards.x86_board import X86Board from gem5.components.cachehierarchies.ruby.mesi_two_level_cache_hierarchy import ( MESITwoLevelCacheHierarchy, ) from gem5.components.memory.single_channel import SingleChannelDDR4_2400 +from gem5.components.processors.cpu_types import CPUTypes from gem5.components.processors.simple_switchable_processor import ( SimpleSwitchableProcessor, ) -from gem5.components.processors.cpu_types import CPUTypes from gem5.isas import ISA -from gem5.coherence_protocol import CoherenceProtocol -from gem5.simulate.simulator import Simulator -from gem5.simulate.exit_event import ExitEvent from gem5.resources.resource import obtain_resource +from gem5.simulate.exit_event import ExitEvent +from gem5.simulate.simulator import Simulator +from gem5.utils.requires import requires # This simulation requires using KVM with gem5 compiled for X86 simulation # and with MESI_Two_Level cache coherence protocol. diff --git a/configs/example/gem5_library/x86-ubuntu-run-with-kvm.py b/configs/example/gem5_library/x86-ubuntu-run-with-kvm.py index 00c00d1459..ec361dcd6e 100644 --- a/configs/example/gem5_library/x86-ubuntu-run-with-kvm.py +++ b/configs/example/gem5_library/x86-ubuntu-run-with-kvm.py @@ -40,18 +40,18 @@ scons build/X86/gem5.opt ``` """ -from gem5.utils.requires import requires +from gem5.coherence_protocol import CoherenceProtocol from gem5.components.boards.x86_board import X86Board from gem5.components.memory.single_channel import SingleChannelDDR3_1600 +from gem5.components.processors.cpu_types import CPUTypes from gem5.components.processors.simple_switchable_processor import ( SimpleSwitchableProcessor, ) -from gem5.components.processors.cpu_types import CPUTypes from gem5.isas import ISA -from gem5.coherence_protocol import CoherenceProtocol -from gem5.simulate.simulator import Simulator -from gem5.simulate.exit_event import ExitEvent from gem5.resources.resource import obtain_resource +from gem5.simulate.exit_event import ExitEvent +from gem5.simulate.simulator import Simulator +from gem5.utils.requires import requires # This runs a check to ensure the gem5 binary is compiled to X86 and to the # MESI Two Level coherence protocol. diff --git a/configs/example/gem5_library/x86-ubuntu-run.py b/configs/example/gem5_library/x86-ubuntu-run.py index fe72d653f5..3b7b754b90 100644 --- a/configs/example/gem5_library/x86-ubuntu-run.py +++ b/configs/example/gem5_library/x86-ubuntu-run.py @@ -48,7 +48,6 @@ from gem5.prebuilt.demo.x86_demo_board import X86DemoBoard from gem5.resources.resource import obtain_resource from gem5.simulate.simulator import Simulator - # Here we setup the board. The prebuilt X86DemoBoard allows for Full-System X86 # simulation. board = X86DemoBoard() diff --git a/configs/example/gpufs/DisjointNetwork.py b/configs/example/gpufs/DisjointNetwork.py index 9215691476..393ac81385 100644 --- a/configs/example/gpufs/DisjointNetwork.py +++ b/configs/example/gpufs/DisjointNetwork.py @@ -27,13 +27,13 @@ # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE # POSSIBILITY OF SUCH DAMAGE. -from m5.objects import * -from m5.util import fatal - from importlib import * from network import Network +from m5.objects import * +from m5.util import fatal + class DisjointSimple(SimpleNetwork): def __init__(self, ruby_system): diff --git a/configs/example/gpufs/Disjoint_VIPER.py b/configs/example/gpufs/Disjoint_VIPER.py index d4619c01a0..28f0768c2a 100644 --- a/configs/example/gpufs/Disjoint_VIPER.py +++ b/configs/example/gpufs/Disjoint_VIPER.py @@ -27,14 +27,14 @@ # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE # POSSIBILITY OF SUCH DAMAGE. +from example.gpufs.DisjointNetwork import * +from ruby import Ruby +from ruby.GPU_VIPER import * + from m5.defines import buildEnv from m5.objects import * from m5.util import fatal -from example.gpufs.DisjointNetwork import * -from ruby.GPU_VIPER import * -from ruby import Ruby - class DummySystem: def __init__(self, mem_ranges): diff --git a/configs/example/gpufs/hip_cookbook.py b/configs/example/gpufs/hip_cookbook.py index 6a7bb428db..0b2c084a4f 100644 --- a/configs/example/gpufs/hip_cookbook.py +++ b/configs/example/gpufs/hip_cookbook.py @@ -27,18 +27,21 @@ # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE # POSSIBILITY OF SUCH DAMAGE. -import m5 -import runfs -import tempfile import argparse -import sys import os +import sys +import tempfile +import runfs from amd import AmdGPUOptions -from common import Options -from common import GPUTLBOptions +from common import ( + GPUTLBOptions, + Options, +) from ruby import Ruby +import m5 + cookbook_runscript = """\ export LD_LIBRARY_PATH=/opt/rocm/lib:$LD_LIBRARY_PATH export HSA_ENABLE_INTERRUPT=0 diff --git a/configs/example/gpufs/hip_rodinia.py b/configs/example/gpufs/hip_rodinia.py index b8a7858fcd..d93bf957fb 100644 --- a/configs/example/gpufs/hip_rodinia.py +++ b/configs/example/gpufs/hip_rodinia.py @@ -27,19 +27,22 @@ # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE # POSSIBILITY OF SUCH DAMAGE. -import m5 -import runfs -import base64 -import tempfile import argparse -import sys +import base64 import os +import sys +import tempfile +import runfs from amd import AmdGPUOptions -from common import Options -from common import GPUTLBOptions +from common import ( + GPUTLBOptions, + Options, +) from ruby import Ruby +import m5 + rodinia_runscript = """\ export LD_LIBRARY_PATH=/opt/rocm/lib:$LD_LIBRARY_PATH export HSA_ENABLE_INTERRUPT=0 diff --git a/configs/example/gpufs/hip_samples.py b/configs/example/gpufs/hip_samples.py index 9f83c2550e..86fdd0e61d 100644 --- a/configs/example/gpufs/hip_samples.py +++ b/configs/example/gpufs/hip_samples.py @@ -27,18 +27,21 @@ # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE # POSSIBILITY OF SUCH DAMAGE. -import m5 -import runfs -import tempfile import argparse -import sys import os +import sys +import tempfile +import runfs from amd import AmdGPUOptions -from common import Options -from common import GPUTLBOptions +from common import ( + GPUTLBOptions, + Options, +) from ruby import Ruby +import m5 + samples_runscript = """\ export LD_LIBRARY_PATH=/opt/rocm/lib:$LD_LIBRARY_PATH export HSA_ENABLE_INTERRUPT=0 diff --git a/configs/example/gpufs/runfs.py b/configs/example/gpufs/runfs.py index 8192503373..9dcc1187f3 100644 --- a/configs/example/gpufs/runfs.py +++ b/configs/example/gpufs/runfs.py @@ -29,8 +29,8 @@ # System includes import argparse -import math import hashlib +import math # gem5 related import m5 @@ -39,13 +39,15 @@ from m5.util import addToPath # gem5 options and objects addToPath("../../") -from ruby import Ruby -from common import Simulation -from common import ObjectList -from common import Options -from common import GPUTLBOptions -from common import GPUTLBConfig from amd import AmdGPUOptions +from common import ( + GPUTLBConfig, + GPUTLBOptions, + ObjectList, + Options, + Simulation, +) +from ruby import Ruby # GPU FS related from system.system import makeGpuFSSystem diff --git a/configs/example/gpufs/system/system.py b/configs/example/gpufs/system/system.py index ee0e0c0fbf..2803e10fb4 100644 --- a/configs/example/gpufs/system/system.py +++ b/configs/example/gpufs/system/system.py @@ -27,18 +27,18 @@ # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE # POSSIBILITY OF SUCH DAMAGE. +from common import ( + GPUTLBConfig, + Simulation, +) +from common.Benchmarks import * +from common.FSConfig import * +from example.gpufs.Disjoint_VIPER import * +from ruby import Ruby from system.amdgpu import * from m5.util import panic -from common.Benchmarks import * -from common.FSConfig import * -from common import GPUTLBConfig -from common import Simulation -from ruby import Ruby - -from example.gpufs.Disjoint_VIPER import * - def makeGpuFSSystem(args): # Boot options are standard gem5 options plus: diff --git a/configs/example/gpufs/vega10.py b/configs/example/gpufs/vega10.py index 9eff5a2974..ae74efd39b 100644 --- a/configs/example/gpufs/vega10.py +++ b/configs/example/gpufs/vega10.py @@ -27,19 +27,21 @@ # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE # POSSIBILITY OF SUCH DAMAGE. -import m5 -import runfs -import base64 -import tempfile import argparse -import sys +import base64 import os +import sys +import tempfile +import runfs from amd import AmdGPUOptions -from common import Options -from common import GPUTLBOptions +from common import ( + GPUTLBOptions, + Options, +) from ruby import Ruby +import m5 demo_runscript_without_checkpoint = """\ export LD_LIBRARY_PATH=/opt/rocm/lib:$LD_LIBRARY_PATH diff --git a/configs/example/hmc_hello.py b/configs/example/hmc_hello.py index bb1711b977..b2e9af1f60 100644 --- a/configs/example/hmc_hello.py +++ b/configs/example/hmc_hello.py @@ -30,19 +30,21 @@ # # Author: Éder F. Zulian -import sys import argparse +import sys import m5 from m5.objects import * from m5.util import * + from gem5.runtime import get_runtime_isa addToPath("../") -from common import MemConfig -from common import HMC - +from common import ( + HMC, + MemConfig, +) pd = "Simple 'hello world' example using HMC as main memory" parser = argparse.ArgumentParser(description=pd) diff --git a/configs/example/hmctest.py b/configs/example/hmctest.py index eca3c28465..8218da87cf 100644 --- a/configs/example/hmctest.py +++ b/configs/example/hmctest.py @@ -1,6 +1,6 @@ -import sys import argparse import subprocess +import sys from pprint import pprint import m5 @@ -9,8 +9,10 @@ from m5.util import * addToPath("../") -from common import MemConfig -from common import HMC +from common import ( + HMC, + MemConfig, +) def add_options(parser): diff --git a/configs/example/hsaTopology.py b/configs/example/hsaTopology.py index 909b9ef519..2dcbdeca01 100644 --- a/configs/example/hsaTopology.py +++ b/configs/example/hsaTopology.py @@ -27,14 +27,26 @@ # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE # POSSIBILITY OF SUCH DAMAGE. -import m5 - import operator -from os import mkdir, makedirs, getpid, listdir, fsync -from os.path import join as joinpath +from os import ( + fsync, + getpid, + listdir, + makedirs, + mkdir, +) from os.path import isdir -from shutil import rmtree, copyfile -from m5.util.convert import toFrequency, toMemorySize +from os.path import join as joinpath +from shutil import ( + copyfile, + rmtree, +) + +import m5 +from m5.util.convert import ( + toFrequency, + toMemorySize, +) def file_append(path, contents): diff --git a/configs/example/lupv/run_lupv.py b/configs/example/lupv/run_lupv.py index e106d051e7..4be6b924a5 100644 --- a/configs/example/lupv/run_lupv.py +++ b/configs/example/lupv/run_lupv.py @@ -33,18 +33,18 @@ Characteristics * Automatically generates the DTB file """ +import argparse + import m5 from m5.objects import Root from gem5.components.boards.experimental.lupv_board import LupvBoard from gem5.components.memory.single_channel import SingleChannelDDR3_1600 -from gem5.components.processors.simple_processor import SimpleProcessor from gem5.components.processors.cpu_types import CPUTypes +from gem5.components.processors.simple_processor import SimpleProcessor from gem5.isas import ISA -from gem5.utils.requires import requires from gem5.resources.resource import obtain_resource - -import argparse +from gem5.utils.requires import requires # Run a check to ensure the right version of gem5 is being used. requires(isa_required=ISA.RISCV) diff --git a/configs/example/riscv/fs_linux.py b/configs/example/riscv/fs_linux.py index 949c7e2623..075b4a0069 100644 --- a/configs/example/riscv/fs_linux.py +++ b/configs/example/riscv/fs_linux.py @@ -45,23 +45,28 @@ from os import path import m5 from m5.defines import buildEnv from m5.objects import * -from m5.util import addToPath, fatal, warn +from m5.util import ( + addToPath, + fatal, + warn, +) from m5.util.fdthelper import * addToPath("../../") -from ruby import Ruby - +from common import ( + CacheConfig, + CpuConfig, + MemConfig, + ObjectList, + Options, + Simulation, +) +from common.Benchmarks import * +from common.Caches import * from common.FSConfig import * from common.SysPaths import * -from common.Benchmarks import * -from common import Simulation -from common import CacheConfig -from common import CpuConfig -from common import MemConfig -from common import ObjectList -from common.Caches import * -from common import Options +from ruby import Ruby # ------------------------- Usage Instructions ------------------------- # # Common system confirguration options (cpu types, num cpus, checkpointing diff --git a/configs/example/ruby_direct_test.py b/configs/example/ruby_direct_test.py index edbeed4cc7..25139b7253 100644 --- a/configs/example/ruby_direct_test.py +++ b/configs/example/ruby_direct_test.py @@ -25,11 +25,14 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +import argparse +import os +import sys + import m5 -from m5.objects import * from m5.defines import buildEnv +from m5.objects import * from m5.util import addToPath -import os, argparse, sys addToPath("../") diff --git a/configs/example/ruby_gpu_random_test.py b/configs/example/ruby_gpu_random_test.py index 25d5a51892..17915c6a6d 100644 --- a/configs/example/ruby_gpu_random_test.py +++ b/configs/example/ruby_gpu_random_test.py @@ -27,11 +27,14 @@ # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE # POSSIBILITY OF SUCH DAMAGE. +import argparse +import os +import sys + import m5 -from m5.objects import * from m5.defines import buildEnv +from m5.objects import * from m5.util import addToPath -import os, argparse, sys addToPath("../") diff --git a/configs/example/ruby_mem_test.py b/configs/example/ruby_mem_test.py index 9ad6a1b7ad..6a9e8c313c 100644 --- a/configs/example/ruby_mem_test.py +++ b/configs/example/ruby_mem_test.py @@ -25,11 +25,14 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +import argparse +import os +import sys + import m5 -from m5.objects import * from m5.defines import buildEnv +from m5.objects import * from m5.util import addToPath -import os, argparse, sys addToPath("../") diff --git a/configs/example/ruby_random_test.py b/configs/example/ruby_random_test.py index 816864be91..ed1b971a9b 100644 --- a/configs/example/ruby_random_test.py +++ b/configs/example/ruby_random_test.py @@ -25,11 +25,14 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +import argparse +import os +import sys + import m5 -from m5.objects import * from m5.defines import buildEnv +from m5.objects import * from m5.util import addToPath -import os, argparse, sys addToPath("../") diff --git a/configs/example/sc_main.py b/configs/example/sc_main.py index 4a1482d87d..141ac173ac 100755 --- a/configs/example/sc_main.py +++ b/configs/example/sc_main.py @@ -26,7 +26,10 @@ import sys import m5 -from m5.objects import SystemC_Kernel, Root +from m5.objects import ( + Root, + SystemC_Kernel, +) # pylint:disable=unused-variable diff --git a/configs/example/sst/riscv_fs.py b/configs/example/sst/riscv_fs.py index c82ad9a6b9..74cb179114 100644 --- a/configs/example/sst/riscv_fs.py +++ b/configs/example/sst/riscv_fs.py @@ -24,15 +24,15 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +import argparse +from os import path + import m5 from m5.objects import * -from os import path # For downloading the disk image from gem5.resources.resource import obtain_resource -import argparse - def generateMemNode(state, mem_range): node = FdtNode(f"memory@{int(mem_range.start):x}") diff --git a/configs/learning_gem5/part1/two_level.py b/configs/learning_gem5/part1/two_level.py index c6f4f4872f..a105faeca3 100644 --- a/configs/learning_gem5/part1/two_level.py +++ b/configs/learning_gem5/part1/two_level.py @@ -42,6 +42,7 @@ import m5 # import all of the SimObjects from m5.objects import * + from gem5.runtime import get_runtime_isa # Add the common scripts to our path diff --git a/configs/learning_gem5/part3/msi_caches.py b/configs/learning_gem5/part3/msi_caches.py index f628cca96d..0945dc2bbd 100644 --- a/configs/learning_gem5/part3/msi_caches.py +++ b/configs/learning_gem5/part3/msi_caches.py @@ -37,9 +37,11 @@ IMPORTANT: If you modify this file, it's likely that the Learning gem5 book import math from m5.defines import buildEnv -from m5.util import fatal, panic - from m5.objects import * +from m5.util import ( + fatal, + panic, +) class MyCacheSystem(RubySystem): diff --git a/configs/learning_gem5/part3/ruby_caches_MI_example.py b/configs/learning_gem5/part3/ruby_caches_MI_example.py index aec54b1068..eecaded31f 100644 --- a/configs/learning_gem5/part3/ruby_caches_MI_example.py +++ b/configs/learning_gem5/part3/ruby_caches_MI_example.py @@ -39,9 +39,11 @@ IMPORTANT: If you modify this file, it's likely that the Learning gem5 book import math from m5.defines import buildEnv -from m5.util import fatal, panic - from m5.objects import * +from m5.util import ( + fatal, + panic, +) class MyCacheSystem(RubySystem): diff --git a/configs/learning_gem5/part3/ruby_test.py b/configs/learning_gem5/part3/ruby_test.py index 5b00e1169e..67ac697bb3 100644 --- a/configs/learning_gem5/part3/ruby_test.py +++ b/configs/learning_gem5/part3/ruby_test.py @@ -33,14 +33,14 @@ IMPORTANT: If you modify this file, it's likely that the Learning gem5 book """ +from test_caches import TestCacheSystem + # import the m5 (gem5) library created when gem5 is built import m5 # import all of the SimObjects from m5.objects import * -from test_caches import TestCacheSystem - # create the system we are going to simulate system = System() diff --git a/configs/learning_gem5/part3/test_caches.py b/configs/learning_gem5/part3/test_caches.py index ebd646ffab..4e8e8febda 100644 --- a/configs/learning_gem5/part3/test_caches.py +++ b/configs/learning_gem5/part3/test_caches.py @@ -34,12 +34,15 @@ IMPORTANT: If you modify this file, it's likely that the Learning gem5 book """ +from msi_caches import ( + DirController, + L1Cache, + MyNetwork, +) + from m5.defines import buildEnv -from m5.util import fatal - from m5.objects import * - -from msi_caches import L1Cache, DirController, MyNetwork +from m5.util import fatal class TestCacheSystem(RubySystem): diff --git a/configs/network/Network.py b/configs/network/Network.py index dbac88c246..0973809c33 100644 --- a/configs/network/Network.py +++ b/configs/network/Network.py @@ -25,10 +25,15 @@ # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. import math + import m5 -from m5.objects import * from m5.defines import buildEnv -from m5.util import addToPath, fatal, warn +from m5.objects import * +from m5.util import ( + addToPath, + fatal, + warn, +) def define_options(parser): diff --git a/configs/nvm/sweep.py b/configs/nvm/sweep.py index b569cb35b5..d5d23ad76a 100644 --- a/configs/nvm/sweep.py +++ b/configs/nvm/sweep.py @@ -33,18 +33,20 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -import math import argparse +import math import m5 from m5.objects import * -from m5.util import addToPath from m5.stats import periodicStatDump +from m5.util import addToPath addToPath("../") -from common import ObjectList -from common import MemConfig +from common import ( + MemConfig, + ObjectList, +) # this script is helpful to sweep the efficiency of a specific memory # controller configuration, by varying the number of banks accessed, diff --git a/configs/nvm/sweep_hybrid.py b/configs/nvm/sweep_hybrid.py index d1e2994268..669f847eb1 100644 --- a/configs/nvm/sweep_hybrid.py +++ b/configs/nvm/sweep_hybrid.py @@ -33,18 +33,20 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -import math import argparse +import math import m5 from m5.objects import * -from m5.util import addToPath from m5.stats import periodicStatDump +from m5.util import addToPath addToPath("../") -from common import ObjectList -from common import MemConfig +from common import ( + MemConfig, + ObjectList, +) # this script is helpful to sweep the efficiency of a specific memory # controller configuration, by varying the number of banks accessed, diff --git a/configs/ruby/AMD_Base_Constructor.py b/configs/ruby/AMD_Base_Constructor.py index ec06fbad34..ff4246a7e0 100644 --- a/configs/ruby/AMD_Base_Constructor.py +++ b/configs/ruby/AMD_Base_Constructor.py @@ -28,10 +28,15 @@ # POSSIBILITY OF SUCH DAMAGE. import math + import m5 -from m5.objects import * from m5.defines import buildEnv -from m5.util import addToPath, convert +from m5.objects import * +from m5.util import ( + addToPath, + convert, +) + from .CntrlBase import * addToPath("../") diff --git a/configs/ruby/CHI.py b/configs/ruby/CHI.py index 2487f696fd..cb8fe64664 100644 --- a/configs/ruby/CHI.py +++ b/configs/ruby/CHI.py @@ -34,8 +34,9 @@ # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. import m5 -from m5.objects import * from m5.defines import buildEnv +from m5.objects import * + from .Ruby import create_topology @@ -53,8 +54,8 @@ def define_options(parser): def read_config_file(file): """Read file as a module and return it""" - import types import importlib.machinery + import types loader = importlib.machinery.SourceFileLoader("chi_configs", file) chi_configs = types.ModuleType(loader.name) diff --git a/configs/ruby/CHI_config.py b/configs/ruby/CHI_config.py index 3cccfd0676..9c7391c0ec 100644 --- a/configs/ruby/CHI_config.py +++ b/configs/ruby/CHI_config.py @@ -46,6 +46,7 @@ node to router binding. See configs/example/noc_config/2x4.py for an example. """ import math + import m5 from m5.objects import * diff --git a/configs/ruby/GPU_VIPER.py b/configs/ruby/GPU_VIPER.py index 665f739b4b..d853c2ef54 100644 --- a/configs/ruby/GPU_VIPER.py +++ b/configs/ruby/GPU_VIPER.py @@ -28,15 +28,22 @@ # POSSIBILITY OF SUCH DAMAGE. import math + +from common import ( + FileSystemConfig, + MemConfig, + ObjectList, +) + import m5 -from m5.objects import * from m5.defines import buildEnv +from m5.objects import * from m5.util import addToPath -from .Ruby import create_topology -from .Ruby import send_evicts -from common import ObjectList -from common import MemConfig -from common import FileSystemConfig + +from .Ruby import ( + create_topology, + send_evicts, +) addToPath("../") diff --git a/configs/ruby/Garnet_standalone.py b/configs/ruby/Garnet_standalone.py index eb481bb4ad..8329295574 100644 --- a/configs/ruby/Garnet_standalone.py +++ b/configs/ruby/Garnet_standalone.py @@ -26,10 +26,14 @@ # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. import m5 -from m5.objects import * from m5.defines import buildEnv +from m5.objects import * from m5.util import addToPath -from .Ruby import create_topology, create_directories + +from .Ruby import ( + create_directories, + create_topology, +) # diff --git a/configs/ruby/MESI_Three_Level.py b/configs/ruby/MESI_Three_Level.py index 077c461b69..e0de4e0636 100644 --- a/configs/ruby/MESI_Three_Level.py +++ b/configs/ruby/MESI_Three_Level.py @@ -28,13 +28,19 @@ # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. import math -import m5 -from m5.objects import * -from m5.defines import buildEnv -from .Ruby import create_topology, create_directories -from .Ruby import send_evicts + from common import FileSystemConfig +import m5 +from m5.defines import buildEnv +from m5.objects import * + +from .Ruby import ( + create_directories, + create_topology, + send_evicts, +) + # # Declare caches used by the protocol diff --git a/configs/ruby/MESI_Three_Level_HTM.py b/configs/ruby/MESI_Three_Level_HTM.py index f2c2ecfd9f..e6c4e81f91 100644 --- a/configs/ruby/MESI_Three_Level_HTM.py +++ b/configs/ruby/MESI_Three_Level_HTM.py @@ -28,13 +28,19 @@ # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. import math -import m5 -from m5.objects import * -from m5.defines import buildEnv -from .Ruby import create_topology, create_directories -from .Ruby import send_evicts + from common import FileSystemConfig +import m5 +from m5.defines import buildEnv +from m5.objects import * + +from .Ruby import ( + create_directories, + create_topology, + send_evicts, +) + # # Declare caches used by the protocol diff --git a/configs/ruby/MESI_Two_Level.py b/configs/ruby/MESI_Two_Level.py index 7326a6cab8..500afbc199 100644 --- a/configs/ruby/MESI_Two_Level.py +++ b/configs/ruby/MESI_Two_Level.py @@ -26,11 +26,16 @@ # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. import math + import m5 -from m5.objects import * from m5.defines import buildEnv -from .Ruby import create_topology, create_directories -from .Ruby import send_evicts +from m5.objects import * + +from .Ruby import ( + create_directories, + create_topology, + send_evicts, +) # diff --git a/configs/ruby/MI_example.py b/configs/ruby/MI_example.py index 7adf5b8ebd..ba0d446840 100644 --- a/configs/ruby/MI_example.py +++ b/configs/ruby/MI_example.py @@ -26,11 +26,16 @@ # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. import math + import m5 -from m5.objects import * from m5.defines import buildEnv -from .Ruby import create_topology, create_directories -from .Ruby import send_evicts +from m5.objects import * + +from .Ruby import ( + create_directories, + create_topology, + send_evicts, +) # diff --git a/configs/ruby/MOESI_AMD_Base.py b/configs/ruby/MOESI_AMD_Base.py index 2c7d743ede..aeab96a85f 100644 --- a/configs/ruby/MOESI_AMD_Base.py +++ b/configs/ruby/MOESI_AMD_Base.py @@ -28,14 +28,19 @@ # POSSIBILITY OF SUCH DAMAGE. import math -import m5 -from m5.objects import * -from m5.defines import buildEnv -from m5.util import addToPath -from .Ruby import create_topology -from .Ruby import send_evicts + from common import FileSystemConfig +import m5 +from m5.defines import buildEnv +from m5.objects import * +from m5.util import addToPath + +from .Ruby import ( + create_topology, + send_evicts, +) + addToPath("../") from topologies.Cluster import Cluster diff --git a/configs/ruby/MOESI_CMP_directory.py b/configs/ruby/MOESI_CMP_directory.py index ecee4a464e..700967f98a 100644 --- a/configs/ruby/MOESI_CMP_directory.py +++ b/configs/ruby/MOESI_CMP_directory.py @@ -38,11 +38,16 @@ # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. import math + import m5 -from m5.objects import * from m5.defines import buildEnv -from .Ruby import create_topology, create_directories -from .Ruby import send_evicts +from m5.objects import * + +from .Ruby import ( + create_directories, + create_topology, + send_evicts, +) # diff --git a/configs/ruby/MOESI_CMP_token.py b/configs/ruby/MOESI_CMP_token.py index 89852e07c3..b6ee7a3875 100644 --- a/configs/ruby/MOESI_CMP_token.py +++ b/configs/ruby/MOESI_CMP_token.py @@ -26,11 +26,16 @@ # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. import math + import m5 -from m5.objects import * from m5.defines import buildEnv -from .Ruby import create_topology, create_directories -from .Ruby import send_evicts +from m5.objects import * + +from .Ruby import ( + create_directories, + create_topology, + send_evicts, +) # diff --git a/configs/ruby/MOESI_hammer.py b/configs/ruby/MOESI_hammer.py index 6ed6a2d50f..f0e1c3730f 100644 --- a/configs/ruby/MOESI_hammer.py +++ b/configs/ruby/MOESI_hammer.py @@ -26,13 +26,19 @@ # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. import math -import m5 -from m5.objects import * -from m5.defines import buildEnv -from .Ruby import create_topology, create_directories -from .Ruby import send_evicts + from common import FileSystemConfig +import m5 +from m5.defines import buildEnv +from m5.objects import * + +from .Ruby import ( + create_directories, + create_topology, + send_evicts, +) + # # Declare caches used by the protocol diff --git a/configs/ruby/Ruby.py b/configs/ruby/Ruby.py index a7aeb6b16f..ae30d55077 100644 --- a/configs/ruby/Ruby.py +++ b/configs/ruby/Ruby.py @@ -38,21 +38,27 @@ # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. import math + import m5 -from m5.objects import * from m5.defines import buildEnv -from m5.util import addToPath, fatal +from m5.objects import * +from m5.util import ( + addToPath, + fatal, +) + from gem5.isas import ISA from gem5.runtime import get_runtime_isa addToPath("../") -from common import ObjectList -from common import MemConfig -from common import FileSystemConfig - -from topologies import * +from common import ( + FileSystemConfig, + MemConfig, + ObjectList, +) from network import Network +from topologies import * def define_options(parser): diff --git a/configs/splash2/cluster.py b/configs/splash2/cluster.py index f7157d98c2..c43067e29c 100644 --- a/configs/splash2/cluster.py +++ b/configs/splash2/cluster.py @@ -28,8 +28,8 @@ # # "m5 test.py" -import os import argparse +import os import sys import m5 diff --git a/configs/splash2/run.py b/configs/splash2/run.py index 4bc2cf653d..e53983d4b1 100644 --- a/configs/splash2/run.py +++ b/configs/splash2/run.py @@ -27,8 +27,8 @@ # Splash2 Run Script # -import os import argparse +import os import sys import m5 diff --git a/configs/topologies/Crossbar.py b/configs/topologies/Crossbar.py index 45929b18ed..f6d4e545ec 100644 --- a/configs/topologies/Crossbar.py +++ b/configs/topologies/Crossbar.py @@ -24,11 +24,11 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from m5.params import * -from m5.objects import * - from topologies.BaseTopology import SimpleTopology +from m5.objects import * +from m5.params import * + class Crossbar(SimpleTopology): description = "Crossbar" diff --git a/configs/topologies/CrossbarGarnet.py b/configs/topologies/CrossbarGarnet.py index 603e1dfd35..74d69e846f 100644 --- a/configs/topologies/CrossbarGarnet.py +++ b/configs/topologies/CrossbarGarnet.py @@ -24,11 +24,11 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from m5.params import * -from m5.objects import * - from topologies.BaseTopology import SimpleTopology +from m5.objects import * +from m5.params import * + class CrossbarGarnet(SimpleTopology): description = "CrossbarGarnet" diff --git a/configs/topologies/CustomMesh.py b/configs/topologies/CustomMesh.py index 0f0d6765cf..f440e00887 100644 --- a/configs/topologies/CustomMesh.py +++ b/configs/topologies/CustomMesh.py @@ -36,11 +36,10 @@ import math -from m5.util import fatal -from m5.params import * -from m5.objects import * - from m5.defines import buildEnv +from m5.objects import * +from m5.params import * +from m5.util import fatal if buildEnv["PROTOCOL"] == "CHI": import ruby.CHI_config as CHI diff --git a/configs/topologies/MeshDirCorners_XY.py b/configs/topologies/MeshDirCorners_XY.py index 1f6eb4297b..afab634bde 100644 --- a/configs/topologies/MeshDirCorners_XY.py +++ b/configs/topologies/MeshDirCorners_XY.py @@ -24,13 +24,12 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from m5.params import * -from m5.objects import * - from common import FileSystemConfig - from topologies.BaseTopology import SimpleTopology +from m5.objects import * +from m5.params import * + # Creates a Mesh topology with 4 directories, one at each corner. # One L1 (and L2, depending on the protocol) are connected to each router. # XY routing is enforced (using link weights) to guarantee deadlock freedom. diff --git a/configs/topologies/Mesh_XY.py b/configs/topologies/Mesh_XY.py index e5402d3d83..6a01793b12 100644 --- a/configs/topologies/Mesh_XY.py +++ b/configs/topologies/Mesh_XY.py @@ -25,13 +25,12 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from m5.params import * -from m5.objects import * - from common import FileSystemConfig - from topologies.BaseTopology import SimpleTopology +from m5.objects import * +from m5.params import * + # Creates a generic Mesh assuming an equal number of cache # and directory controllers. # XY routing is enforced (using link weights) diff --git a/configs/topologies/Mesh_westfirst.py b/configs/topologies/Mesh_westfirst.py index 45702b759a..a9ed5c145e 100644 --- a/configs/topologies/Mesh_westfirst.py +++ b/configs/topologies/Mesh_westfirst.py @@ -25,11 +25,11 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from m5.params import * -from m5.objects import * - from topologies.BaseTopology import SimpleTopology +from m5.objects import * +from m5.params import * + # Creates a generic Mesh assuming an equal number of cache # and directory controllers. # West-first routing is enforced (using link weights) diff --git a/configs/topologies/Pt2Pt.py b/configs/topologies/Pt2Pt.py index 8d85b31f1e..1268751370 100644 --- a/configs/topologies/Pt2Pt.py +++ b/configs/topologies/Pt2Pt.py @@ -25,11 +25,11 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from m5.params import * -from m5.objects import * - from topologies.BaseTopology import SimpleTopology +from m5.objects import * +from m5.params import * + class Pt2Pt(SimpleTopology): description = "Pt2Pt" diff --git a/ext/testlib/__init__.py b/ext/testlib/__init__.py index 2fad890b65..d2dad35eff 100644 --- a/ext/testlib/__init__.py +++ b/ext/testlib/__init__.py @@ -27,18 +27,18 @@ # Authors: Sean Wilson -from .state import * -from .runner import * -from .test_util import * -from .suite import * -from .loader import * -from .fixture import * -from .configuration import * -from .main import main +# TODO Remove this as an export, users should getcwd from os +from os import getcwd # TODO Remove this awkward bootstrap # FIXME from gem5 import * -# TODO Remove this as an export, users should getcwd from os -from os import getcwd +from .configuration import * +from .fixture import * +from .loader import * +from .main import main +from .runner import * +from .state import * +from .suite import * +from .test_util import * diff --git a/ext/testlib/configuration.py b/ext/testlib/configuration.py index a635b6d3a9..60c0c17654 100644 --- a/ext/testlib/configuration.py +++ b/ext/testlib/configuration.py @@ -82,10 +82,13 @@ import argparse import copy import os import re - from pickle import HIGHEST_PROTOCOL as highest_pickle_protocol -from testlib.helper import absdirpath, AttrDict, FrozenAttrDict +from testlib.helper import ( + AttrDict, + FrozenAttrDict, + absdirpath, +) class UninitialzedAttributeException(Exception): diff --git a/ext/testlib/fixture.py b/ext/testlib/fixture.py index 16fc39c29f..14d42c4724 100644 --- a/ext/testlib/fixture.py +++ b/ext/testlib/fixture.py @@ -26,11 +26,11 @@ # # Authors: Sean Wilson +from typing import Optional + import testlib.helper as helper from testlib.configuration import constants -from typing import Optional - class SkipException(Exception): def __init__(self, fixture, testitem): diff --git a/ext/testlib/handlers.py b/ext/testlib/handlers.py index 6a6f654355..283e04f170 100644 --- a/ext/testlib/handlers.py +++ b/ext/testlib/handlers.py @@ -37,14 +37,16 @@ import sys import threading import time import traceback +from queue import ( + Empty, + Queue, +) import testlib.helper as helper import testlib.log as log import testlib.result as result import testlib.state as state import testlib.terminal as terminal - -from queue import Queue, Empty from testlib.configuration import constants diff --git a/ext/testlib/helper.py b/ext/testlib/helper.py index 0fd0cf539e..a66ce8ad2c 100644 --- a/ext/testlib/helper.py +++ b/ext/testlib/helper.py @@ -41,9 +41,6 @@ """ Helper classes for writing tests with this test library. """ -from collections import namedtuple -from collections.abc import MutableSet - import difflib import errno import os @@ -54,6 +51,8 @@ import subprocess import tempfile import threading import time +from collections import namedtuple +from collections.abc import MutableSet class TimedWaitPID: diff --git a/ext/testlib/loader.py b/ext/testlib/loader.py index 192632adab..d74f76181d 100644 --- a/ext/testlib/loader.py +++ b/ext/testlib/loader.py @@ -70,12 +70,12 @@ import re import sys import traceback +import testlib.fixture as fixture_mod import testlib.log as log import testlib.suite as suite_mod import testlib.test_util as test_mod -import testlib.fixture as fixture_mod -import testlib.wrappers as wrappers import testlib.uid as uid +import testlib.wrappers as wrappers class DuplicateTestItemException(Exception): diff --git a/ext/testlib/main.py b/ext/testlib/main.py index fdd4c17b2f..d93f167a77 100644 --- a/ext/testlib/main.py +++ b/ext/testlib/main.py @@ -26,8 +26,8 @@ # # Authors: Sean Wilson -import os import itertools +import os import testlib.configuration as configuration import testlib.handlers as handlers diff --git a/ext/testlib/query.py b/ext/testlib/query.py index ead567a360..b2c21f8fb4 100644 --- a/ext/testlib/query.py +++ b/ext/testlib/query.py @@ -26,8 +26,8 @@ # # Authors: Sean Wilson -import testlib.terminal as terminal import testlib.log as log +import testlib.terminal as terminal # TODO Refactor print logic out of this so the objects diff --git a/ext/testlib/result.py b/ext/testlib/result.py index b6977d3542..73c8cea5d5 100644 --- a/ext/testlib/result.py +++ b/ext/testlib/result.py @@ -42,9 +42,9 @@ import os import pickle import xml.sax.saxutils -from testlib.configuration import config import testlib.helper as helper import testlib.state as state +from testlib.configuration import config def _create_uid_index(iterable): diff --git a/ext/testlib/runner.py b/ext/testlib/runner.py index 1e3512af2b..540acb35df 100644 --- a/ext/testlib/runner.py +++ b/ext/testlib/runner.py @@ -43,9 +43,11 @@ import traceback import testlib.helper as helper import testlib.log as log - -from testlib.state import Status, Result from testlib.fixture import SkipException +from testlib.state import ( + Result, + Status, +) def compute_aggregate_result(iterable): diff --git a/ext/testlib/terminal.py b/ext/testlib/terminal.py index f295aa2dc4..fa3531093e 100644 --- a/ext/testlib/terminal.py +++ b/ext/testlib/terminal.py @@ -24,10 +24,10 @@ # # Author: Steve Reinhardt -import sys import fcntl -import termios import struct +import sys +import termios # Intended usage example: # diff --git a/ext/testlib/uid.py b/ext/testlib/uid.py index 84403f80fe..70d653bc20 100644 --- a/ext/testlib/uid.py +++ b/ext/testlib/uid.py @@ -26,8 +26,8 @@ # # Authors: Sean Wilson -import os import itertools +import os import testlib.configuration as configuration diff --git a/ext/testlib/wrappers.py b/ext/testlib/wrappers.py index 936d9b604d..4e1be80427 100644 --- a/ext/testlib/wrappers.py +++ b/ext/testlib/wrappers.py @@ -45,7 +45,10 @@ loaded by the testlib :class:`testlib.loader.Loader`. import itertools import testlib.uid as uid -from testlib.state import Status, Result +from testlib.state import ( + Result, + Status, +) class TestCaseMetadata: diff --git a/site_scons/gem5_scons/__init__.py b/site_scons/gem5_scons/__init__.py index 3638d9c561..bed4b48157 100644 --- a/site_scons/gem5_scons/__init__.py +++ b/site_scons/gem5_scons/__init__.py @@ -45,11 +45,11 @@ import sys import tempfile import textwrap -from gem5_scons.util import get_termcap -from gem5_scons.configure import Configure -from gem5_scons.defaults import EnvDefaults import SCons.Node.Python import SCons.Script +from gem5_scons.configure import Configure +from gem5_scons.defaults import EnvDefaults +from gem5_scons.util import get_termcap termcap = get_termcap() diff --git a/site_scons/gem5_scons/builders/blob.py b/site_scons/gem5_scons/builders/blob.py index f4e6d3a0ea..74d5b85259 100644 --- a/site_scons/gem5_scons/builders/blob.py +++ b/site_scons/gem5_scons/builders/blob.py @@ -39,12 +39,13 @@ import os.path -from gem5_scons import Transform, MakeAction -from blob import bytesToCppArray - -from code_formatter import code_formatter - import SCons.Node.Python +from blob import bytesToCppArray +from code_formatter import code_formatter +from gem5_scons import ( + MakeAction, + Transform, +) def build_blob(target, source, env): diff --git a/site_scons/gem5_scons/builders/config_file.py b/site_scons/gem5_scons/builders/config_file.py index 7ee5e4d658..28eb975631 100755 --- a/site_scons/gem5_scons/builders/config_file.py +++ b/site_scons/gem5_scons/builders/config_file.py @@ -38,7 +38,10 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from gem5_scons import Transform, MakeAction +from gem5_scons import ( + MakeAction, + Transform, +) ################################################### # diff --git a/site_scons/gem5_scons/builders/switching_headers.py b/site_scons/gem5_scons/builders/switching_headers.py index 92bd613508..497179422f 100755 --- a/site_scons/gem5_scons/builders/switching_headers.py +++ b/site_scons/gem5_scons/builders/switching_headers.py @@ -40,7 +40,10 @@ import os.path -from gem5_scons import Transform, MakeAction +from gem5_scons import ( + MakeAction, + Transform, +) ################################################### # diff --git a/site_scons/gem5_scons/kconfig.py b/site_scons/gem5_scons/kconfig.py index 42b2eec482..b3b49d27c5 100644 --- a/site_scons/gem5_scons/kconfig.py +++ b/site_scons/gem5_scons/kconfig.py @@ -25,9 +25,10 @@ import os -from . import error import kconfiglib +from . import error + _kconfig_helpers = { "DEFCONFIG_PY": "defconfig.py", "GUICONFIG_PY": "guiconfig.py", diff --git a/site_scons/gem5_scons/util.py b/site_scons/gem5_scons/util.py index ee8efdc49a..be0a5a5880 100644 --- a/site_scons/gem5_scons/util.py +++ b/site_scons/gem5_scons/util.py @@ -66,7 +66,11 @@ def readCommand(cmd, **kwargs): :returns: command stdout :rtype: string """ - from subprocess import Popen, PIPE, STDOUT + from subprocess import ( + PIPE, + STDOUT, + Popen, + ) if isinstance(cmd, str): cmd = cmd.split() diff --git a/site_scons/site_tools/git.py b/site_scons/site_tools/git.py index 362c20b105..40e5d6267e 100644 --- a/site_scons/site_tools/git.py +++ b/site_scons/site_tools/git.py @@ -38,10 +38,10 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from asyncio import subprocess import os -import sys import subprocess +import sys +from asyncio import subprocess import gem5_scons.util import SCons.Script diff --git a/src/arch/amdgpu/common/X86GPUTLB.py b/src/arch/amdgpu/common/X86GPUTLB.py index 59cc549d17..407443b8d7 100644 --- a/src/arch/amdgpu/common/X86GPUTLB.py +++ b/src/arch/amdgpu/common/X86GPUTLB.py @@ -28,10 +28,9 @@ # POSSIBILITY OF SUCH DAMAGE. from m5.defines import buildEnv +from m5.objects.ClockedObject import ClockedObject from m5.params import * from m5.proxy import * - -from m5.objects.ClockedObject import ClockedObject from m5.SimObject import SimObject diff --git a/src/arch/amdgpu/vega/VegaGPUTLB.py b/src/arch/amdgpu/vega/VegaGPUTLB.py index 96b940c544..6ef9630d18 100644 --- a/src/arch/amdgpu/vega/VegaGPUTLB.py +++ b/src/arch/amdgpu/vega/VegaGPUTLB.py @@ -28,11 +28,10 @@ # POSSIBILITY OF SUCH DAMAGE. from m5.defines import buildEnv +from m5.objects.AMDGPU import AMDGPUDevice +from m5.objects.ClockedObject import ClockedObject from m5.params import * from m5.proxy import * - -from m5.objects.ClockedObject import ClockedObject -from m5.objects.AMDGPU import AMDGPUDevice from m5.SimObject import SimObject diff --git a/src/arch/arm/ArmCPU.py b/src/arch/arm/ArmCPU.py index 52c3ba8a0a..35ed712cba 100644 --- a/src/arch/arm/ArmCPU.py +++ b/src/arch/arm/ArmCPU.py @@ -23,18 +23,17 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from m5.proxy import Self - -from m5.objects.BaseAtomicSimpleCPU import BaseAtomicSimpleCPU -from m5.objects.BaseNonCachingSimpleCPU import BaseNonCachingSimpleCPU -from m5.objects.BaseTimingSimpleCPU import BaseTimingSimpleCPU -from m5.objects.BaseO3CPU import BaseO3CPU -from m5.objects.BaseO3Checker import BaseO3Checker -from m5.objects.BaseMinorCPU import BaseMinorCPU from m5.objects.ArmDecoder import ArmDecoder -from m5.objects.ArmMMU import ArmMMU from m5.objects.ArmInterrupts import ArmInterrupts from m5.objects.ArmISA import ArmISA +from m5.objects.ArmMMU import ArmMMU +from m5.objects.BaseAtomicSimpleCPU import BaseAtomicSimpleCPU +from m5.objects.BaseMinorCPU import BaseMinorCPU +from m5.objects.BaseNonCachingSimpleCPU import BaseNonCachingSimpleCPU +from m5.objects.BaseO3Checker import BaseO3Checker +from m5.objects.BaseO3CPU import BaseO3CPU +from m5.objects.BaseTimingSimpleCPU import BaseTimingSimpleCPU +from m5.proxy import Self class ArmCPU: diff --git a/src/arch/arm/ArmDecoder.py b/src/arch/arm/ArmDecoder.py index d4b82e3f4f..f92c81debe 100644 --- a/src/arch/arm/ArmDecoder.py +++ b/src/arch/arm/ArmDecoder.py @@ -35,8 +35,8 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from m5.params import * from m5.objects.InstDecoder import InstDecoder +from m5.params import * class ArmDecoder(InstDecoder): diff --git a/src/arch/arm/ArmFsWorkload.py b/src/arch/arm/ArmFsWorkload.py index a9474fe119..6d2804cb9b 100644 --- a/src/arch/arm/ArmFsWorkload.py +++ b/src/arch/arm/ArmFsWorkload.py @@ -33,10 +33,10 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from m5.params import * -from m5.options import * -from m5.SimObject import * from m5.objects.Workload import KernelWorkload +from m5.options import * +from m5.params import * +from m5.SimObject import * class ArmMachineType(Enum): diff --git a/src/arch/arm/ArmISA.py b/src/arch/arm/ArmISA.py index 97c2609f50..8e8d2b641c 100644 --- a/src/arch/arm/ArmISA.py +++ b/src/arch/arm/ArmISA.py @@ -33,13 +33,16 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +from m5.objects.ArmPMU import ArmPMU +from m5.objects.ArmSystem import ( + ArmRelease, + SmeVectorLength, + SveVectorLength, +) +from m5.objects.BaseISA import BaseISA from m5.params import * from m5.proxy import * - from m5.SimObject import SimObject -from m5.objects.ArmPMU import ArmPMU -from m5.objects.ArmSystem import SveVectorLength, SmeVectorLength, ArmRelease -from m5.objects.BaseISA import BaseISA # Enum for DecoderFlavor diff --git a/src/arch/arm/ArmMMU.py b/src/arch/arm/ArmMMU.py index e2e548b1b3..8cafc2c624 100644 --- a/src/arch/arm/ArmMMU.py +++ b/src/arch/arm/ArmMMU.py @@ -36,7 +36,10 @@ # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. from m5.objects.ArmSystem import ArmRelease -from m5.objects.ArmTLB import ArmTLB, ArmStage2TLB +from m5.objects.ArmTLB import ( + ArmStage2TLB, + ArmTLB, +) from m5.objects.BaseMMU import BaseMMU from m5.objects.ClockedObject import ClockedObject from m5.params import * diff --git a/src/arch/arm/ArmNativeTrace.py b/src/arch/arm/ArmNativeTrace.py index 0c795a6426..09462e1bf6 100644 --- a/src/arch/arm/ArmNativeTrace.py +++ b/src/arch/arm/ArmNativeTrace.py @@ -24,9 +24,9 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from m5.SimObject import SimObject -from m5.params import * from m5.objects.CPUTracers import NativeTrace +from m5.params import * +from m5.SimObject import SimObject class ArmNativeTrace(NativeTrace): diff --git a/src/arch/arm/ArmPMU.py b/src/arch/arm/ArmPMU.py index 3fd619b55d..27a7fa224d 100644 --- a/src/arch/arm/ArmPMU.py +++ b/src/arch/arm/ArmPMU.py @@ -35,11 +35,14 @@ # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. from m5.defines import buildEnv -from m5.SimObject import * +from m5.objects.Gic import ( + ArmInterruptPin, + ArmPPI, +) from m5.params import * from m5.params import isNullPointer from m5.proxy import * -from m5.objects.Gic import ArmInterruptPin, ArmPPI +from m5.SimObject import * from m5.util.fdthelper import * diff --git a/src/arch/arm/ArmSeWorkload.py b/src/arch/arm/ArmSeWorkload.py index 1bf4e3edf3..e01853baeb 100644 --- a/src/arch/arm/ArmSeWorkload.py +++ b/src/arch/arm/ArmSeWorkload.py @@ -23,9 +23,8 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from m5.params import * - from m5.objects.Workload import SEWorkload +from m5.params import * class ArmSEWorkload(SEWorkload): diff --git a/src/arch/arm/ArmSemihosting.py b/src/arch/arm/ArmSemihosting.py index 54322cdec0..8c8375e208 100644 --- a/src/arch/arm/ArmSemihosting.py +++ b/src/arch/arm/ArmSemihosting.py @@ -33,11 +33,10 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from m5.params import * -from m5.SimObject import * - from m5.objects.Serial import SerialDevice from m5.objects.Terminal import Terminal +from m5.params import * +from m5.SimObject import * class ArmSemihosting(SimObject): diff --git a/src/arch/arm/ArmSystem.py b/src/arch/arm/ArmSystem.py index f66c9c83d2..dc138cafc3 100644 --- a/src/arch/arm/ArmSystem.py +++ b/src/arch/arm/ArmSystem.py @@ -33,16 +33,15 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from m5.params import * +from typing import Any + +from m5.objects.ArmSemihosting import ArmSemihosting +from m5.objects.System import System from m5.options import * +from m5.params import * from m5.SimObject import * from m5.util.fdthelper import * -from m5.objects.System import System -from m5.objects.ArmSemihosting import ArmSemihosting - -from typing import Any - class SveVectorLength(UInt8): min = 1 diff --git a/src/arch/arm/ArmTLB.py b/src/arch/arm/ArmTLB.py index 8475a56b5b..c868a322f1 100644 --- a/src/arch/arm/ArmTLB.py +++ b/src/arch/arm/ArmTLB.py @@ -35,10 +35,10 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from m5.SimObject import SimObject +from m5.objects.BaseTLB import BaseTLB from m5.params import * from m5.proxy import * -from m5.objects.BaseTLB import BaseTLB +from m5.SimObject import SimObject class ArmLookupLevel(Enum): diff --git a/src/arch/arm/fastmodel/CortexA76/FastModelCortexA76.py b/src/arch/arm/fastmodel/CortexA76/FastModelCortexA76.py index f690fb5097..4c332f88ad 100644 --- a/src/arch/arm/fastmodel/CortexA76/FastModelCortexA76.py +++ b/src/arch/arm/fastmodel/CortexA76/FastModelCortexA76.py @@ -23,20 +23,25 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +from m5.objects.ArmInterrupts import ArmInterrupts +from m5.objects.ArmISA import ArmISA +from m5.objects.FastModel import ( + AmbaInitiatorSocket, + AmbaTargetSocket, +) +from m5.objects.FastModelGIC import Gicv3CommsTargetSocket +from m5.objects.Gic import ArmPPI +from m5.objects.IntPin import IntSinkPin +from m5.objects.Iris import IrisBaseCPU +from m5.objects.ResetPort import ResetResponsePort +from m5.objects.SystemC import SystemC_ScModule from m5.params import * from m5.proxy import * from m5.SimObject import SimObject - -from m5.objects.ArmInterrupts import ArmInterrupts -from m5.objects.ArmISA import ArmISA -from m5.objects.FastModel import AmbaInitiatorSocket, AmbaTargetSocket -from m5.objects.FastModelGIC import Gicv3CommsTargetSocket -from m5.objects.ResetPort import ResetResponsePort -from m5.objects.IntPin import IntSinkPin -from m5.objects.Gic import ArmPPI -from m5.objects.Iris import IrisBaseCPU -from m5.objects.SystemC import SystemC_ScModule -from m5.util.fdthelper import FdtNode, FdtPropertyWords +from m5.util.fdthelper import ( + FdtNode, + FdtPropertyWords, +) class FastModelCortexA76(IrisBaseCPU): diff --git a/src/arch/arm/fastmodel/CortexR52/FastModelCortexR52.py b/src/arch/arm/fastmodel/CortexR52/FastModelCortexR52.py index fe81e72bd0..acf5087867 100644 --- a/src/arch/arm/fastmodel/CortexR52/FastModelCortexR52.py +++ b/src/arch/arm/fastmodel/CortexR52/FastModelCortexR52.py @@ -23,18 +23,24 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +from m5.objects.ArmInterrupts import ArmInterrupts +from m5.objects.ArmISA import ArmISA +from m5.objects.FastModel import ( + AmbaInitiatorSocket, + AmbaTargetSocket, +) +from m5.objects.IntPin import ( + IntSinkPin, + IntSourcePin, + VectorIntSinkPin, +) +from m5.objects.Iris import IrisBaseCPU +from m5.objects.ResetPort import ResetResponsePort +from m5.objects.SystemC import SystemC_ScModule from m5.params import * from m5.proxy import * from m5.SimObject import SimObject -from m5.objects.ArmInterrupts import ArmInterrupts -from m5.objects.ArmISA import ArmISA -from m5.objects.FastModel import AmbaInitiatorSocket, AmbaTargetSocket -from m5.objects.ResetPort import ResetResponsePort -from m5.objects.IntPin import IntSourcePin, IntSinkPin, VectorIntSinkPin -from m5.objects.Iris import IrisBaseCPU -from m5.objects.SystemC import SystemC_ScModule - class FastModelCortexR52(IrisBaseCPU): type = "FastModelCortexR52" diff --git a/src/arch/arm/fastmodel/FastModel.py b/src/arch/arm/fastmodel/FastModel.py index 8ba537623a..3ba5d8bb78 100644 --- a/src/arch/arm/fastmodel/FastModel.py +++ b/src/arch/arm/fastmodel/FastModel.py @@ -23,12 +23,14 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +from m5.objects.SystemC import SystemC_ScModule +from m5.objects.Tlm import ( + TlmInitiatorSocket, + TlmTargetSocket, +) from m5.params import * from m5.proxy import * -from m5.objects.SystemC import SystemC_ScModule -from m5.objects.Tlm import TlmInitiatorSocket, TlmTargetSocket - def AMBA_TARGET_ROLE(width): return "AMBA TARGET %d" % width diff --git a/src/arch/arm/fastmodel/GIC/FastModelGIC.py b/src/arch/arm/fastmodel/GIC/FastModelGIC.py index b1a9a3c8a1..9d0b5e0fcc 100644 --- a/src/arch/arm/fastmodel/GIC/FastModelGIC.py +++ b/src/arch/arm/fastmodel/GIC/FastModelGIC.py @@ -35,15 +35,17 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from m5.params import * -from m5.util.fdthelper import * -from m5.SimObject import SimObject - -from m5.objects.FastModel import AmbaInitiatorSocket, AmbaTargetSocket +from m5.objects.FastModel import ( + AmbaInitiatorSocket, + AmbaTargetSocket, +) from m5.objects.Gic import BaseGic from m5.objects.IntPin import VectorIntSourcePin from m5.objects.ResetPort import ResetResponsePort from m5.objects.SystemC import SystemC_ScModule +from m5.params import * +from m5.SimObject import SimObject +from m5.util.fdthelper import * GICV3_COMMS_TARGET_ROLE = "GICV3 COMMS TARGET" GICV3_COMMS_INITIATOR_ROLE = "GICV3 COMMS INITIATOR" diff --git a/src/arch/arm/fastmodel/PL330_DMAC/FastModelPL330.py b/src/arch/arm/fastmodel/PL330_DMAC/FastModelPL330.py index 21ead525d3..23b6f711a0 100644 --- a/src/arch/arm/fastmodel/PL330_DMAC/FastModelPL330.py +++ b/src/arch/arm/fastmodel/PL330_DMAC/FastModelPL330.py @@ -23,11 +23,14 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from m5.params import * -from m5.objects.FastModel import AmbaInitiatorSocket, AmbaTargetSocket +from m5.objects.FastModel import ( + AmbaInitiatorSocket, + AmbaTargetSocket, +) from m5.objects.IntPin import IntSourcePin from m5.objects.ResetPort import ResetResponsePort from m5.objects.SystemC import SystemC_ScModule +from m5.params import * class FastModelPL330(SystemC_ScModule): diff --git a/src/arch/arm/fastmodel/arm_fast_model.py b/src/arch/arm/fastmodel/arm_fast_model.py index 45a97d7957..df7b1b63b7 100644 --- a/src/arch/arm/fastmodel/arm_fast_model.py +++ b/src/arch/arm/fastmodel/arm_fast_model.py @@ -29,6 +29,7 @@ import os import socket from m5.defines import buildEnv + import _m5.arm_fast_model ARM_LICENSE_ENV = "ARMLMD_LICENSE_FILE" diff --git a/src/arch/arm/fastmodel/iris/Iris.py b/src/arch/arm/fastmodel/iris/Iris.py index c38db908cc..5129136077 100644 --- a/src/arch/arm/fastmodel/iris/Iris.py +++ b/src/arch/arm/fastmodel/iris/Iris.py @@ -35,14 +35,13 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from m5.params import * -from m5.proxy import * - from m5.objects.BaseCPU import BaseCPU from m5.objects.BaseInterrupts import BaseInterrupts from m5.objects.BaseISA import BaseISA -from m5.objects.BaseTLB import BaseTLB from m5.objects.BaseMMU import BaseMMU +from m5.objects.BaseTLB import BaseTLB +from m5.params import * +from m5.proxy import * class IrisTLB(BaseTLB): diff --git a/src/arch/arm/fastmodel/reset_controller/FastModelResetControllerExample.py b/src/arch/arm/fastmodel/reset_controller/FastModelResetControllerExample.py index 225c5d917b..e2507cbf4c 100644 --- a/src/arch/arm/fastmodel/reset_controller/FastModelResetControllerExample.py +++ b/src/arch/arm/fastmodel/reset_controller/FastModelResetControllerExample.py @@ -23,12 +23,11 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from m5.params import * -from m5.proxy import * - from m5.objects.Device import BasicPioDevice from m5.objects.IntPin import IntSourcePin from m5.objects.Iris import IrisBaseCPU +from m5.params import * +from m5.proxy import * class FastModelResetControllerExample(BasicPioDevice): diff --git a/src/arch/arm/kvm/ArmKvmCPU.py b/src/arch/arm/kvm/ArmKvmCPU.py index 56770a5b0a..d3829f5c71 100644 --- a/src/arch/arm/kvm/ArmKvmCPU.py +++ b/src/arch/arm/kvm/ArmKvmCPU.py @@ -33,8 +33,8 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from m5.params import * from m5.objects.BaseKvmCPU import BaseKvmCPU +from m5.params import * class ArmKvmCPU(BaseKvmCPU): diff --git a/src/arch/arm/kvm/ArmV8KvmCPU.py b/src/arch/arm/kvm/ArmV8KvmCPU.py index a6d83bb610..39f9d0d1ba 100644 --- a/src/arch/arm/kvm/ArmV8KvmCPU.py +++ b/src/arch/arm/kvm/ArmV8KvmCPU.py @@ -33,8 +33,8 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from m5.params import * from m5.objects.BaseArmKvmCPU import BaseArmKvmCPU +from m5.params import * class ArmV8KvmCPU(BaseArmKvmCPU): diff --git a/src/arch/arm/kvm/BaseArmKvmCPU.py b/src/arch/arm/kvm/BaseArmKvmCPU.py index f896256063..415cf78a9e 100644 --- a/src/arch/arm/kvm/BaseArmKvmCPU.py +++ b/src/arch/arm/kvm/BaseArmKvmCPU.py @@ -33,10 +33,10 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from m5.params import * from m5.objects.ArmCPU import ArmCPU from m5.objects.ArmMMU import ArmMMU from m5.objects.BaseKvmCPU import BaseKvmCPU +from m5.params import * class BaseArmKvmCPU(BaseKvmCPU, ArmCPU): diff --git a/src/arch/arm/kvm/KvmGic.py b/src/arch/arm/kvm/KvmGic.py index 1002d3c2f5..a9e1e9341d 100644 --- a/src/arch/arm/kvm/KvmGic.py +++ b/src/arch/arm/kvm/KvmGic.py @@ -33,11 +33,13 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +from m5.objects.Gic import ( + GicV2, + Gicv3, +) from m5.params import * from m5.proxy import * -from m5.objects.Gic import GicV2, Gicv3 - class MuxingKvmGicV2(GicV2): type = "MuxingKvmGicV2" diff --git a/src/arch/arm/tracers/ArmCapstone.py b/src/arch/arm/tracers/ArmCapstone.py index 7f1b6a9e8a..0bceb6dbd6 100644 --- a/src/arch/arm/tracers/ArmCapstone.py +++ b/src/arch/arm/tracers/ArmCapstone.py @@ -33,9 +33,9 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from m5.SimObject import SimObject -from m5.params import * from m5.objects.Capstone import CapstoneDisassembler +from m5.params import * +from m5.SimObject import SimObject class ArmCapstoneDisassembler(CapstoneDisassembler): diff --git a/src/arch/arm/tracers/TarmacTrace.py b/src/arch/arm/tracers/TarmacTrace.py index 82c447aada..e28b19bee4 100644 --- a/src/arch/arm/tracers/TarmacTrace.py +++ b/src/arch/arm/tracers/TarmacTrace.py @@ -33,9 +33,9 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from m5.SimObject import SimObject -from m5.params import * from m5.objects.InstTracer import InstTracer +from m5.params import * +from m5.SimObject import SimObject class TarmacParser(InstTracer): diff --git a/src/arch/isa_parser/isa_parser.py b/src/arch/isa_parser/isa_parser.py index b0b2485cac..0b74d00f29 100755 --- a/src/arch/isa_parser/isa_parser.py +++ b/src/arch/isa_parser/isa_parser.py @@ -46,6 +46,7 @@ import traceback from types import * from grammar import Grammar + from .operand_list import * from .operand_types import * from .util import * diff --git a/src/arch/isa_parser/operand_list.py b/src/arch/isa_parser/operand_list.py index 29062893ec..2fe0ef1739 100755 --- a/src/arch/isa_parser/operand_list.py +++ b/src/arch/isa_parser/operand_list.py @@ -37,8 +37,12 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from .util import assignRE, commentRE, stringRE -from .util import error +from .util import ( + assignRE, + commentRE, + error, + stringRE, +) class OperandList: diff --git a/src/arch/micro_asm.py b/src/arch/micro_asm.py index ec890cbe6d..0329800896 100644 --- a/src/arch/micro_asm.py +++ b/src/arch/micro_asm.py @@ -25,15 +25,17 @@ # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. import os -import sys import re +import sys import traceback # get type names from types import * -from ply import lex -from ply import yacc +from ply import ( + lex, + yacc, +) ########################################################################## # diff --git a/src/arch/micro_asm_test.py b/src/arch/micro_asm_test.py index b6b8918b2d..29724aa2d7 100755 --- a/src/arch/micro_asm_test.py +++ b/src/arch/micro_asm_test.py @@ -24,7 +24,12 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from micro_asm import MicroAssembler, CombinationalMacroop, RomMacroop, Rom +from micro_asm import ( + CombinationalMacroop, + MicroAssembler, + Rom, + RomMacroop, +) class Bah: diff --git a/src/arch/mips/MipsCPU.py b/src/arch/mips/MipsCPU.py index 53b134ad79..558bbf8733 100644 --- a/src/arch/mips/MipsCPU.py +++ b/src/arch/mips/MipsCPU.py @@ -24,14 +24,14 @@ # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. from m5.objects.BaseAtomicSimpleCPU import BaseAtomicSimpleCPU -from m5.objects.BaseNonCachingSimpleCPU import BaseNonCachingSimpleCPU -from m5.objects.BaseTimingSimpleCPU import BaseTimingSimpleCPU -from m5.objects.BaseO3CPU import BaseO3CPU from m5.objects.BaseMinorCPU import BaseMinorCPU +from m5.objects.BaseNonCachingSimpleCPU import BaseNonCachingSimpleCPU +from m5.objects.BaseO3CPU import BaseO3CPU +from m5.objects.BaseTimingSimpleCPU import BaseTimingSimpleCPU from m5.objects.MipsDecoder import MipsDecoder -from m5.objects.MipsMMU import MipsMMU from m5.objects.MipsInterrupts import MipsInterrupts from m5.objects.MipsISA import MipsISA +from m5.objects.MipsMMU import MipsMMU class MipsCPU: diff --git a/src/arch/mips/MipsISA.py b/src/arch/mips/MipsISA.py index 01075dd1b0..f3eb85b8ed 100644 --- a/src/arch/mips/MipsISA.py +++ b/src/arch/mips/MipsISA.py @@ -33,11 +33,10 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +from m5.objects.BaseISA import BaseISA from m5.params import * from m5.proxy import * -from m5.objects.BaseISA import BaseISA - class MipsISA(BaseISA): type = "MipsISA" diff --git a/src/arch/mips/MipsSeWorkload.py b/src/arch/mips/MipsSeWorkload.py index b5f20cd892..ba73c112a4 100644 --- a/src/arch/mips/MipsSeWorkload.py +++ b/src/arch/mips/MipsSeWorkload.py @@ -23,9 +23,8 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from m5.params import * - from m5.objects.Workload import SEWorkload +from m5.params import * class MipsSEWorkload(SEWorkload): diff --git a/src/arch/mips/MipsTLB.py b/src/arch/mips/MipsTLB.py index 2051c662e0..43906f11d3 100644 --- a/src/arch/mips/MipsTLB.py +++ b/src/arch/mips/MipsTLB.py @@ -26,10 +26,9 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from m5.SimObject import SimObject -from m5.params import * - from m5.objects.BaseTLB import BaseTLB +from m5.params import * +from m5.SimObject import SimObject class MipsTLB(BaseTLB): diff --git a/src/arch/power/PowerCPU.py b/src/arch/power/PowerCPU.py index f19c6f6a2f..b634a78c4a 100644 --- a/src/arch/power/PowerCPU.py +++ b/src/arch/power/PowerCPU.py @@ -24,14 +24,14 @@ # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. from m5.objects.BaseAtomicSimpleCPU import BaseAtomicSimpleCPU -from m5.objects.BaseNonCachingSimpleCPU import BaseNonCachingSimpleCPU -from m5.objects.BaseTimingSimpleCPU import BaseTimingSimpleCPU -from m5.objects.BaseO3CPU import BaseO3CPU from m5.objects.BaseMinorCPU import BaseMinorCPU +from m5.objects.BaseNonCachingSimpleCPU import BaseNonCachingSimpleCPU +from m5.objects.BaseO3CPU import BaseO3CPU +from m5.objects.BaseTimingSimpleCPU import BaseTimingSimpleCPU from m5.objects.PowerDecoder import PowerDecoder -from m5.objects.PowerMMU import PowerMMU from m5.objects.PowerInterrupts import PowerInterrupts from m5.objects.PowerISA import PowerISA +from m5.objects.PowerMMU import PowerMMU class PowerCPU: diff --git a/src/arch/power/PowerSeWorkload.py b/src/arch/power/PowerSeWorkload.py index 162104d0dd..4a4116be4b 100644 --- a/src/arch/power/PowerSeWorkload.py +++ b/src/arch/power/PowerSeWorkload.py @@ -23,9 +23,8 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from m5.params import * - from m5.objects.Workload import SEWorkload +from m5.params import * class PowerSEWorkload(SEWorkload): diff --git a/src/arch/power/PowerTLB.py b/src/arch/power/PowerTLB.py index 32c4a68940..9217f24d30 100644 --- a/src/arch/power/PowerTLB.py +++ b/src/arch/power/PowerTLB.py @@ -26,10 +26,9 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from m5.SimObject import SimObject -from m5.params import * - from m5.objects.BaseTLB import BaseTLB +from m5.params import * +from m5.SimObject import SimObject class PowerTLB(BaseTLB): diff --git a/src/arch/riscv/PMAChecker.py b/src/arch/riscv/PMAChecker.py index 581560bd56..c456569b32 100644 --- a/src/arch/riscv/PMAChecker.py +++ b/src/arch/riscv/PMAChecker.py @@ -35,9 +35,9 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from m5.SimObject import SimObject from m5.params import * from m5.proxy import * +from m5.SimObject import SimObject class PMAChecker(SimObject): diff --git a/src/arch/riscv/PMP.py b/src/arch/riscv/PMP.py index a3844c99fd..dc0608d643 100644 --- a/src/arch/riscv/PMP.py +++ b/src/arch/riscv/PMP.py @@ -24,9 +24,9 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from m5.SimObject import SimObject from m5.params import * from m5.proxy import * +from m5.SimObject import SimObject class PMP(SimObject): diff --git a/src/arch/riscv/RiscvCPU.py b/src/arch/riscv/RiscvCPU.py index 1c77045c67..2b1b053b48 100644 --- a/src/arch/riscv/RiscvCPU.py +++ b/src/arch/riscv/RiscvCPU.py @@ -24,14 +24,14 @@ # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. from m5.objects.BaseAtomicSimpleCPU import BaseAtomicSimpleCPU -from m5.objects.BaseNonCachingSimpleCPU import BaseNonCachingSimpleCPU -from m5.objects.BaseTimingSimpleCPU import BaseTimingSimpleCPU -from m5.objects.BaseO3CPU import BaseO3CPU from m5.objects.BaseMinorCPU import BaseMinorCPU +from m5.objects.BaseNonCachingSimpleCPU import BaseNonCachingSimpleCPU +from m5.objects.BaseO3CPU import BaseO3CPU +from m5.objects.BaseTimingSimpleCPU import BaseTimingSimpleCPU from m5.objects.RiscvDecoder import RiscvDecoder -from m5.objects.RiscvMMU import RiscvMMU from m5.objects.RiscvInterrupts import RiscvInterrupts from m5.objects.RiscvISA import RiscvISA +from m5.objects.RiscvMMU import RiscvMMU class RiscvCPU: diff --git a/src/arch/riscv/RiscvFsWorkload.py b/src/arch/riscv/RiscvFsWorkload.py index a71dc1acaf..36580a5498 100644 --- a/src/arch/riscv/RiscvFsWorkload.py +++ b/src/arch/riscv/RiscvFsWorkload.py @@ -27,10 +27,12 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from m5.params import * - from m5.objects.System import System -from m5.objects.Workload import Workload, KernelWorkload +from m5.objects.Workload import ( + KernelWorkload, + Workload, +) +from m5.params import * class RiscvBareMetal(Workload): diff --git a/src/arch/riscv/RiscvISA.py b/src/arch/riscv/RiscvISA.py index bce7f2497f..d4dcf663b7 100644 --- a/src/arch/riscv/RiscvISA.py +++ b/src/arch/riscv/RiscvISA.py @@ -39,9 +39,12 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from m5.params import Enum, UInt32 -from m5.params import Param from m5.objects.BaseISA import BaseISA +from m5.params import ( + Enum, + Param, + UInt32, +) class RiscvVectorLength(UInt32): diff --git a/src/arch/riscv/RiscvMMU.py b/src/arch/riscv/RiscvMMU.py index 312244a85d..6ef4182c88 100644 --- a/src/arch/riscv/RiscvMMU.py +++ b/src/arch/riscv/RiscvMMU.py @@ -35,12 +35,11 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from m5.params import * - from m5.objects.BaseMMU import BaseMMU -from m5.objects.RiscvTLB import RiscvTLB from m5.objects.PMAChecker import PMAChecker from m5.objects.PMP import PMP +from m5.objects.RiscvTLB import RiscvTLB +from m5.params import * class RiscvMMU(BaseMMU): diff --git a/src/arch/riscv/RiscvSeWorkload.py b/src/arch/riscv/RiscvSeWorkload.py index 5df6b786c3..45aa79ed5b 100644 --- a/src/arch/riscv/RiscvSeWorkload.py +++ b/src/arch/riscv/RiscvSeWorkload.py @@ -23,9 +23,8 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from m5.params import * - from m5.objects.Workload import SEWorkload +from m5.params import * class RiscvSEWorkload(SEWorkload): diff --git a/src/arch/riscv/RiscvTLB.py b/src/arch/riscv/RiscvTLB.py index e943d8ddab..05a1c71b19 100644 --- a/src/arch/riscv/RiscvTLB.py +++ b/src/arch/riscv/RiscvTLB.py @@ -28,11 +28,10 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from m5.params import * -from m5.proxy import * - from m5.objects.BaseTLB import BaseTLB from m5.objects.ClockedObject import ClockedObject +from m5.params import * +from m5.proxy import * class RiscvPagetableWalker(ClockedObject): diff --git a/src/arch/sparc/SparcCPU.py b/src/arch/sparc/SparcCPU.py index 44d9ceed08..fdc17729e2 100644 --- a/src/arch/sparc/SparcCPU.py +++ b/src/arch/sparc/SparcCPU.py @@ -24,14 +24,14 @@ # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. from m5.objects.BaseAtomicSimpleCPU import BaseAtomicSimpleCPU -from m5.objects.BaseNonCachingSimpleCPU import BaseNonCachingSimpleCPU -from m5.objects.BaseTimingSimpleCPU import BaseTimingSimpleCPU -from m5.objects.BaseO3CPU import BaseO3CPU from m5.objects.BaseMinorCPU import BaseMinorCPU +from m5.objects.BaseNonCachingSimpleCPU import BaseNonCachingSimpleCPU +from m5.objects.BaseO3CPU import BaseO3CPU +from m5.objects.BaseTimingSimpleCPU import BaseTimingSimpleCPU from m5.objects.SparcDecoder import SparcDecoder -from m5.objects.SparcMMU import SparcMMU from m5.objects.SparcInterrupts import SparcInterrupts from m5.objects.SparcISA import SparcISA +from m5.objects.SparcMMU import SparcMMU class SparcCPU: diff --git a/src/arch/sparc/SparcFsWorkload.py b/src/arch/sparc/SparcFsWorkload.py index ba70dcfa59..89b17a82f9 100644 --- a/src/arch/sparc/SparcFsWorkload.py +++ b/src/arch/sparc/SparcFsWorkload.py @@ -24,9 +24,8 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from m5.params import * - from m5.objects.Workload import Workload +from m5.params import * class SparcFsWorkload(Workload): diff --git a/src/arch/sparc/SparcMMU.py b/src/arch/sparc/SparcMMU.py index 1202594fc6..a00be60685 100644 --- a/src/arch/sparc/SparcMMU.py +++ b/src/arch/sparc/SparcMMU.py @@ -35,10 +35,10 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from m5.SimObject import SimObject -from m5.params import * from m5.objects.BaseMMU import BaseMMU from m5.objects.SparcTLB import SparcTLB +from m5.params import * +from m5.SimObject import SimObject class SparcMMU(BaseMMU): diff --git a/src/arch/sparc/SparcNativeTrace.py b/src/arch/sparc/SparcNativeTrace.py index 0a93126f2c..9b215e19c6 100644 --- a/src/arch/sparc/SparcNativeTrace.py +++ b/src/arch/sparc/SparcNativeTrace.py @@ -24,10 +24,9 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from m5.SimObject import SimObject -from m5.params import * - from m5.objects.CPUTracers import NativeTrace +from m5.params import * +from m5.SimObject import SimObject class SparcNativeTrace(NativeTrace): diff --git a/src/arch/sparc/SparcSeWorkload.py b/src/arch/sparc/SparcSeWorkload.py index 3dbd341801..060bf21005 100644 --- a/src/arch/sparc/SparcSeWorkload.py +++ b/src/arch/sparc/SparcSeWorkload.py @@ -23,9 +23,8 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from m5.params import * - from m5.objects.Workload import SEWorkload +from m5.params import * class SparcSEWorkload(SEWorkload): diff --git a/src/arch/sparc/SparcTLB.py b/src/arch/sparc/SparcTLB.py index e834d62000..6b43d69cfc 100644 --- a/src/arch/sparc/SparcTLB.py +++ b/src/arch/sparc/SparcTLB.py @@ -24,10 +24,9 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from m5.SimObject import SimObject -from m5.params import * - from m5.objects.BaseTLB import BaseTLB +from m5.params import * +from m5.SimObject import SimObject class SparcTLB(BaseTLB): diff --git a/src/arch/x86/X86CPU.py b/src/arch/x86/X86CPU.py index bd39f6d0f5..ac3398bb6d 100644 --- a/src/arch/x86/X86CPU.py +++ b/src/arch/x86/X86CPU.py @@ -23,19 +23,18 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from m5.proxy import Self - from m5.objects.BaseAtomicSimpleCPU import BaseAtomicSimpleCPU -from m5.objects.BaseNonCachingSimpleCPU import BaseNonCachingSimpleCPU -from m5.objects.BaseTimingSimpleCPU import BaseTimingSimpleCPU -from m5.objects.BaseO3CPU import BaseO3CPU from m5.objects.BaseMinorCPU import BaseMinorCPU +from m5.objects.BaseNonCachingSimpleCPU import BaseNonCachingSimpleCPU +from m5.objects.BaseO3CPU import BaseO3CPU +from m5.objects.BaseTimingSimpleCPU import BaseTimingSimpleCPU from m5.objects.FuncUnit import * from m5.objects.FUPool import * from m5.objects.X86Decoder import X86Decoder -from m5.objects.X86MMU import X86MMU -from m5.objects.X86LocalApic import X86LocalApic from m5.objects.X86ISA import X86ISA +from m5.objects.X86LocalApic import X86LocalApic +from m5.objects.X86MMU import X86MMU +from m5.proxy import Self class X86CPU: diff --git a/src/arch/x86/X86FsWorkload.py b/src/arch/x86/X86FsWorkload.py index 277a37988e..6cff4211ae 100644 --- a/src/arch/x86/X86FsWorkload.py +++ b/src/arch/x86/X86FsWorkload.py @@ -33,13 +33,21 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from m5.params import * - -from m5.objects.E820 import X86E820Table, X86E820Entry -from m5.objects.SMBios import X86SMBiosSMBiosTable -from m5.objects.IntelMP import X86IntelMPFloatingPointer, X86IntelMPConfigTable from m5.objects.ACPI import X86ACPIRSDP -from m5.objects.Workload import KernelWorkload, Workload +from m5.objects.E820 import ( + X86E820Entry, + X86E820Table, +) +from m5.objects.IntelMP import ( + X86IntelMPConfigTable, + X86IntelMPFloatingPointer, +) +from m5.objects.SMBios import X86SMBiosSMBiosTable +from m5.objects.Workload import ( + KernelWorkload, + Workload, +) +from m5.params import * class X86BareMetalWorkload(Workload): diff --git a/src/arch/x86/X86LocalApic.py b/src/arch/x86/X86LocalApic.py index d7defce7e5..8b7d9a831d 100644 --- a/src/arch/x86/X86LocalApic.py +++ b/src/arch/x86/X86LocalApic.py @@ -37,12 +37,11 @@ # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. from m5.defines import buildEnv -from m5.params import * -from m5.proxy import * - from m5.objects.BaseInterrupts import BaseInterrupts from m5.objects.ClockDomain import DerivedClockDomain from m5.objects.IntPin import IntSinkPin +from m5.params import * +from m5.proxy import * class X86LocalApic(BaseInterrupts): diff --git a/src/arch/x86/X86NativeTrace.py b/src/arch/x86/X86NativeTrace.py index d0b94ecc40..773071674d 100644 --- a/src/arch/x86/X86NativeTrace.py +++ b/src/arch/x86/X86NativeTrace.py @@ -24,10 +24,9 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from m5.SimObject import SimObject -from m5.params import * - from m5.objects.CPUTracers import NativeTrace +from m5.params import * +from m5.SimObject import SimObject class X86NativeTrace(NativeTrace): diff --git a/src/arch/x86/X86SeWorkload.py b/src/arch/x86/X86SeWorkload.py index 6674bdb9a5..e8e75a3ec3 100644 --- a/src/arch/x86/X86SeWorkload.py +++ b/src/arch/x86/X86SeWorkload.py @@ -23,9 +23,8 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from m5.params import * - from m5.objects.Workload import SEWorkload +from m5.params import * class X86EmuLinux(SEWorkload): diff --git a/src/arch/x86/X86TLB.py b/src/arch/x86/X86TLB.py index 8532ddf8c6..8c3c65cce3 100644 --- a/src/arch/x86/X86TLB.py +++ b/src/arch/x86/X86TLB.py @@ -33,11 +33,10 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from m5.params import * -from m5.proxy import * - from m5.objects.BaseTLB import BaseTLB from m5.objects.ClockedObject import ClockedObject +from m5.params import * +from m5.proxy import * class X86PagetableWalker(ClockedObject): diff --git a/src/arch/x86/kvm/X86KvmCPU.py b/src/arch/x86/kvm/X86KvmCPU.py index df32fe8b40..6f50ba2511 100644 --- a/src/arch/x86/kvm/X86KvmCPU.py +++ b/src/arch/x86/kvm/X86KvmCPU.py @@ -24,12 +24,11 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from m5.params import * -from m5.SimObject import * - from m5.objects.BaseKvmCPU import BaseKvmCPU from m5.objects.X86CPU import X86CPU from m5.objects.X86MMU import X86MMU +from m5.params import * +from m5.SimObject import * class X86KvmCPU(BaseKvmCPU, X86CPU): diff --git a/src/base/Graphics.py b/src/base/Graphics.py index b58e287129..824a3c4a9d 100644 --- a/src/base/Graphics.py +++ b/src/base/Graphics.py @@ -33,8 +33,8 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from m5.SimObject import SimObject from m5.params import * +from m5.SimObject import SimObject # Image Formats: diff --git a/src/base/vnc/Vnc.py b/src/base/vnc/Vnc.py index e7012ecb06..5ee03c3f8b 100644 --- a/src/base/vnc/Vnc.py +++ b/src/base/vnc/Vnc.py @@ -33,9 +33,9 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from m5.SimObject import SimObject -from m5.params import * from m5.objects.Graphics import * +from m5.params import * +from m5.SimObject import SimObject class VncInput(SimObject): diff --git a/src/cpu/BaseCPU.py b/src/cpu/BaseCPU.py index 900c0ae626..9ba60ef1b8 100644 --- a/src/cpu/BaseCPU.py +++ b/src/cpu/BaseCPU.py @@ -40,20 +40,19 @@ import sys -from m5.SimObject import * from m5.defines import buildEnv -from m5.params import * -from m5.proxy import * -from m5.util.fdthelper import * - -from m5.objects.ClockedObject import ClockedObject -from m5.objects.XBar import L2XBar -from m5.objects.InstTracer import InstTracer -from m5.objects.CPUTracers import ExeTracer -from m5.objects.SubSystem import SubSystem from m5.objects.ClockDomain import * +from m5.objects.ClockedObject import ClockedObject +from m5.objects.CPUTracers import ExeTracer +from m5.objects.InstTracer import InstTracer from m5.objects.Platform import Platform from m5.objects.ResetPort import ResetResponsePort +from m5.objects.SubSystem import SubSystem +from m5.objects.XBar import L2XBar +from m5.params import * +from m5.proxy import * +from m5.SimObject import * +from m5.util.fdthelper import * default_tracer = ExeTracer() diff --git a/src/cpu/CPUTracers.py b/src/cpu/CPUTracers.py index f491a0ef43..ce6c3b4e33 100644 --- a/src/cpu/CPUTracers.py +++ b/src/cpu/CPUTracers.py @@ -24,9 +24,9 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from m5.SimObject import SimObject -from m5.params import * from m5.objects.InstTracer import InstTracer +from m5.params import * +from m5.SimObject import SimObject class ExeTracer(InstTracer): diff --git a/src/cpu/Capstone.py b/src/cpu/Capstone.py index 4b6b5fd84a..ac6e0b7e95 100644 --- a/src/cpu/Capstone.py +++ b/src/cpu/Capstone.py @@ -33,9 +33,9 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from m5.SimObject import SimObject -from m5.params import * from m5.objects.InstTracer import InstDisassembler +from m5.params import * +from m5.SimObject import SimObject class CapstoneDisassembler(InstDisassembler): diff --git a/src/cpu/CheckerCPU.py b/src/cpu/CheckerCPU.py index beb04b79e1..9cd0ce4c33 100644 --- a/src/cpu/CheckerCPU.py +++ b/src/cpu/CheckerCPU.py @@ -24,9 +24,8 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from m5.params import * - from m5.objects.BaseCPU import BaseCPU +from m5.params import * from m5.SimObject import SimObject diff --git a/src/cpu/CpuCluster.py b/src/cpu/CpuCluster.py index 42a71122a3..c26bc653af 100644 --- a/src/cpu/CpuCluster.py +++ b/src/cpu/CpuCluster.py @@ -33,8 +33,8 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from m5.params import * from m5.objects.SubSystem import SubSystem +from m5.params import * class CpuCluster(SubSystem): diff --git a/src/cpu/DummyChecker.py b/src/cpu/DummyChecker.py index 916d25a92a..7176498e6c 100644 --- a/src/cpu/DummyChecker.py +++ b/src/cpu/DummyChecker.py @@ -33,8 +33,8 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from m5.params import * from m5.objects.CheckerCPU import CheckerCPU +from m5.params import * class DummyChecker(CheckerCPU): diff --git a/src/cpu/FuncUnit.py b/src/cpu/FuncUnit.py index 012dfd0ee4..cba3eda878 100644 --- a/src/cpu/FuncUnit.py +++ b/src/cpu/FuncUnit.py @@ -36,8 +36,8 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from m5.SimObject import SimObject from m5.params import * +from m5.SimObject import SimObject class OpClass(Enum): diff --git a/src/cpu/InstPBTrace.py b/src/cpu/InstPBTrace.py index 167443d3cd..ca50ed4644 100644 --- a/src/cpu/InstPBTrace.py +++ b/src/cpu/InstPBTrace.py @@ -24,10 +24,9 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from m5.SimObject import SimObject -from m5.params import * - from m5.objects.InstTracer import InstTracer +from m5.params import * +from m5.SimObject import SimObject class InstPBTrace(InstTracer): diff --git a/src/cpu/kvm/BaseKvmCPU.py b/src/cpu/kvm/BaseKvmCPU.py index 610663fa41..2c90acf3e8 100644 --- a/src/cpu/kvm/BaseKvmCPU.py +++ b/src/cpu/kvm/BaseKvmCPU.py @@ -33,12 +33,11 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from m5.SimObject import * -from m5.params import * -from m5.proxy import * - from m5.objects.BaseCPU import BaseCPU from m5.objects.KvmVM import KvmVM +from m5.params import * +from m5.proxy import * +from m5.SimObject import * class BaseKvmCPU(BaseCPU): diff --git a/src/cpu/kvm/KvmVM.py b/src/cpu/kvm/KvmVM.py index cdb826cf6c..5198de10f2 100644 --- a/src/cpu/kvm/KvmVM.py +++ b/src/cpu/kvm/KvmVM.py @@ -35,7 +35,6 @@ from m5.params import * from m5.proxy import * - from m5.SimObject import SimObject diff --git a/src/cpu/minor/BaseMinorCPU.py b/src/cpu/minor/BaseMinorCPU.py index c20a310447..7110caac2c 100644 --- a/src/cpu/minor/BaseMinorCPU.py +++ b/src/cpu/minor/BaseMinorCPU.py @@ -37,15 +37,14 @@ # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. from m5.defines import buildEnv +from m5.objects.BaseCPU import BaseCPU +from m5.objects.BranchPredictor import * +from m5.objects.DummyChecker import DummyChecker +from m5.objects.FuncUnit import OpClass +from m5.objects.TimingExpr import TimingExpr from m5.params import * from m5.proxy import * from m5.SimObject import SimObject -from m5.objects.BaseCPU import BaseCPU -from m5.objects.DummyChecker import DummyChecker -from m5.objects.BranchPredictor import * -from m5.objects.TimingExpr import TimingExpr - -from m5.objects.FuncUnit import OpClass class MinorOpClass(SimObject): diff --git a/src/cpu/o3/BaseO3CPU.py b/src/cpu/o3/BaseO3CPU.py index 2e1a602e4c..dfb1068c7c 100644 --- a/src/cpu/o3/BaseO3CPU.py +++ b/src/cpu/o3/BaseO3CPU.py @@ -37,14 +37,13 @@ # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. from m5.defines import buildEnv -from m5.params import * -from m5.proxy import * - from m5.objects.BaseCPU import BaseCPU -from m5.objects.FUPool import * # from m5.objects.O3Checker import O3Checker from m5.objects.BranchPredictor import * +from m5.objects.FUPool import * +from m5.params import * +from m5.proxy import * class SMTFetchPolicy(ScopedEnum): diff --git a/src/cpu/o3/BaseO3Checker.py b/src/cpu/o3/BaseO3Checker.py index 7b480f8057..cda6dad57e 100644 --- a/src/cpu/o3/BaseO3Checker.py +++ b/src/cpu/o3/BaseO3Checker.py @@ -24,8 +24,8 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from m5.params import * from m5.objects.CheckerCPU import CheckerCPU +from m5.params import * class BaseO3Checker(CheckerCPU): diff --git a/src/cpu/o3/FUPool.py b/src/cpu/o3/FUPool.py index 4e18094ef4..67f523787b 100644 --- a/src/cpu/o3/FUPool.py +++ b/src/cpu/o3/FUPool.py @@ -36,10 +36,10 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from m5.SimObject import SimObject -from m5.params import * from m5.objects.FuncUnit import * from m5.objects.FuncUnitConfig import * +from m5.params import * +from m5.SimObject import SimObject class FUPool(SimObject): diff --git a/src/cpu/o3/FuncUnitConfig.py b/src/cpu/o3/FuncUnitConfig.py index 7ba49c93bf..617cef9749 100644 --- a/src/cpu/o3/FuncUnitConfig.py +++ b/src/cpu/o3/FuncUnitConfig.py @@ -36,11 +36,10 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from m5.SimObject import SimObject from m5.defines import buildEnv -from m5.params import * - from m5.objects.FuncUnit import * +from m5.params import * +from m5.SimObject import SimObject class IntALU(FUDesc): diff --git a/src/cpu/pred/BranchPredictor.py b/src/cpu/pred/BranchPredictor.py index 8589fe5d51..3ac333934e 100644 --- a/src/cpu/pred/BranchPredictor.py +++ b/src/cpu/pred/BranchPredictor.py @@ -37,11 +37,10 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from m5.SimObject import * +from m5.objects.ClockedObject import ClockedObject from m5.params import * from m5.proxy import * - -from m5.objects.ClockedObject import ClockedObject +from m5.SimObject import * class BranchType(Enum): diff --git a/src/cpu/probes/PcCountTracker.py b/src/cpu/probes/PcCountTracker.py index 259ec68f8e..6106970436 100644 --- a/src/cpu/probes/PcCountTracker.py +++ b/src/cpu/probes/PcCountTracker.py @@ -24,10 +24,10 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +from m5.objects import SimObject +from m5.objects.Probe import ProbeListenerObject from m5.params import * from m5.util.pybind import * -from m5.objects.Probe import ProbeListenerObject -from m5.objects import SimObject class PcCountTrackerManager(SimObject): diff --git a/src/cpu/simple/BaseAtomicSimpleCPU.py b/src/cpu/simple/BaseAtomicSimpleCPU.py index 4ee53aef0f..27367bd0cf 100644 --- a/src/cpu/simple/BaseAtomicSimpleCPU.py +++ b/src/cpu/simple/BaseAtomicSimpleCPU.py @@ -36,9 +36,9 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from m5.params import * from m5.objects.BaseSimpleCPU import BaseSimpleCPU from m5.objects.SimPoint import SimPoint +from m5.params import * class BaseAtomicSimpleCPU(BaseSimpleCPU): diff --git a/src/cpu/simple/BaseNonCachingSimpleCPU.py b/src/cpu/simple/BaseNonCachingSimpleCPU.py index 58a7324068..787b4fccb0 100644 --- a/src/cpu/simple/BaseNonCachingSimpleCPU.py +++ b/src/cpu/simple/BaseNonCachingSimpleCPU.py @@ -33,8 +33,8 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from m5.params import * from m5.objects.BaseAtomicSimpleCPU import BaseAtomicSimpleCPU +from m5.params import * class BaseNonCachingSimpleCPU(BaseAtomicSimpleCPU): diff --git a/src/cpu/simple/BaseSimpleCPU.py b/src/cpu/simple/BaseSimpleCPU.py index fe7ad751a7..d4816700c0 100644 --- a/src/cpu/simple/BaseSimpleCPU.py +++ b/src/cpu/simple/BaseSimpleCPU.py @@ -25,11 +25,10 @@ # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. from m5.defines import buildEnv -from m5.params import * - from m5.objects.BaseCPU import BaseCPU -from m5.objects.DummyChecker import DummyChecker from m5.objects.BranchPredictor import * +from m5.objects.DummyChecker import DummyChecker +from m5.params import * class BaseSimpleCPU(BaseCPU): diff --git a/src/cpu/simple/BaseTimingSimpleCPU.py b/src/cpu/simple/BaseTimingSimpleCPU.py index 5761816fa7..6b1a1a7699 100644 --- a/src/cpu/simple/BaseTimingSimpleCPU.py +++ b/src/cpu/simple/BaseTimingSimpleCPU.py @@ -24,9 +24,8 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from m5.params import * - from m5.objects.BaseSimpleCPU import BaseSimpleCPU +from m5.params import * class BaseTimingSimpleCPU(BaseSimpleCPU): diff --git a/src/cpu/simple/probes/SimPoint.py b/src/cpu/simple/probes/SimPoint.py index 6f2f13ba74..73a716760f 100644 --- a/src/cpu/simple/probes/SimPoint.py +++ b/src/cpu/simple/probes/SimPoint.py @@ -33,8 +33,8 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from m5.params import * from m5.objects.Probe import ProbeListenerObject +from m5.params import * class SimPoint(ProbeListenerObject): diff --git a/src/cpu/testers/directedtest/RubyDirectedTester.py b/src/cpu/testers/directedtest/RubyDirectedTester.py index b9297b058b..d01b0bdee2 100644 --- a/src/cpu/testers/directedtest/RubyDirectedTester.py +++ b/src/cpu/testers/directedtest/RubyDirectedTester.py @@ -24,11 +24,10 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from m5.SimObject import SimObject +from m5.objects.ClockedObject import ClockedObject from m5.params import * from m5.proxy import * - -from m5.objects.ClockedObject import ClockedObject +from m5.SimObject import SimObject class DirectedGenerator(SimObject): diff --git a/src/cpu/testers/gpu_ruby_test/CpuThread.py b/src/cpu/testers/gpu_ruby_test/CpuThread.py index f40df272a4..e74301b677 100644 --- a/src/cpu/testers/gpu_ruby_test/CpuThread.py +++ b/src/cpu/testers/gpu_ruby_test/CpuThread.py @@ -27,11 +27,10 @@ # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE # POSSIBILITY OF SUCH DAMAGE. +from m5.objects.TesterThread import TesterThread from m5.params import * from m5.proxy import * -from m5.objects.TesterThread import TesterThread - class CpuThread(TesterThread): type = "CpuThread" diff --git a/src/cpu/testers/gpu_ruby_test/DmaThread.py b/src/cpu/testers/gpu_ruby_test/DmaThread.py index 0a3dbc7289..c1b9b91a43 100644 --- a/src/cpu/testers/gpu_ruby_test/DmaThread.py +++ b/src/cpu/testers/gpu_ruby_test/DmaThread.py @@ -27,11 +27,10 @@ # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE # POSSIBILITY OF SUCH DAMAGE. +from m5.objects.TesterThread import TesterThread from m5.params import * from m5.proxy import * -from m5.objects.TesterThread import TesterThread - class DmaThread(TesterThread): type = "DmaThread" diff --git a/src/cpu/testers/gpu_ruby_test/GpuWavefront.py b/src/cpu/testers/gpu_ruby_test/GpuWavefront.py index 625af91fa4..2a22f4d7c7 100644 --- a/src/cpu/testers/gpu_ruby_test/GpuWavefront.py +++ b/src/cpu/testers/gpu_ruby_test/GpuWavefront.py @@ -27,11 +27,10 @@ # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE # POSSIBILITY OF SUCH DAMAGE. +from m5.objects.TesterThread import TesterThread from m5.params import * from m5.proxy import * -from m5.objects.TesterThread import TesterThread - class GpuWavefront(TesterThread): type = "GpuWavefront" diff --git a/src/cpu/testers/memtest/MemTest.py b/src/cpu/testers/memtest/MemTest.py index 2d6a0e33c5..db22d86e4e 100644 --- a/src/cpu/testers/memtest/MemTest.py +++ b/src/cpu/testers/memtest/MemTest.py @@ -36,11 +36,10 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +from m5.objects.ClockedObject import ClockedObject from m5.params import * from m5.proxy import * -from m5.objects.ClockedObject import ClockedObject - class MemTest(ClockedObject): type = "MemTest" diff --git a/src/cpu/testers/rubytest/RubyTester.py b/src/cpu/testers/rubytest/RubyTester.py index a90cfe1f82..e613eff79c 100644 --- a/src/cpu/testers/rubytest/RubyTester.py +++ b/src/cpu/testers/rubytest/RubyTester.py @@ -25,11 +25,10 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. # +from m5.objects.ClockedObject import ClockedObject from m5.params import * from m5.proxy import * -from m5.objects.ClockedObject import ClockedObject - class RubyTester(ClockedObject): type = "RubyTester" diff --git a/src/cpu/testers/traffic_gen/BaseTrafficGen.py b/src/cpu/testers/traffic_gen/BaseTrafficGen.py index 7fdfda22e5..48700e0747 100644 --- a/src/cpu/testers/traffic_gen/BaseTrafficGen.py +++ b/src/cpu/testers/traffic_gen/BaseTrafficGen.py @@ -33,9 +33,9 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +from m5.objects.ClockedObject import ClockedObject from m5.params import * from m5.proxy import * -from m5.objects.ClockedObject import ClockedObject # Types of Stream Generators. diff --git a/src/cpu/testers/traffic_gen/GUPSGen.py b/src/cpu/testers/traffic_gen/GUPSGen.py index 6b8b3f72df..747a8de994 100644 --- a/src/cpu/testers/traffic_gen/GUPSGen.py +++ b/src/cpu/testers/traffic_gen/GUPSGen.py @@ -25,9 +25,9 @@ # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. # +from m5.objects.ClockedObject import ClockedObject from m5.params import * from m5.proxy import * -from m5.objects.ClockedObject import ClockedObject class GUPSGen(ClockedObject): diff --git a/src/cpu/testers/traffic_gen/PyTrafficGen.py b/src/cpu/testers/traffic_gen/PyTrafficGen.py index c3a660f053..be61ec1e56 100644 --- a/src/cpu/testers/traffic_gen/PyTrafficGen.py +++ b/src/cpu/testers/traffic_gen/PyTrafficGen.py @@ -34,9 +34,8 @@ # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. from m5.defines import buildEnv -from m5.SimObject import * - from m5.objects.BaseTrafficGen import * +from m5.SimObject import * class PyTrafficGen(BaseTrafficGen): diff --git a/src/cpu/testers/traffic_gen/TrafficGen.py b/src/cpu/testers/traffic_gen/TrafficGen.py index 15190120cc..d5242099d1 100644 --- a/src/cpu/testers/traffic_gen/TrafficGen.py +++ b/src/cpu/testers/traffic_gen/TrafficGen.py @@ -33,8 +33,8 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from m5.params import * from m5.objects.BaseTrafficGen import * +from m5.params import * # The behaviour of this traffic generator is specified in a diff --git a/src/cpu/trace/TraceCPU.py b/src/cpu/trace/TraceCPU.py index 5e82fd9f9f..7b053e569f 100644 --- a/src/cpu/trace/TraceCPU.py +++ b/src/cpu/trace/TraceCPU.py @@ -33,9 +33,9 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +from m5.objects.ClockedObject import ClockedObject from m5.params import * from m5.proxy import * -from m5.objects.ClockedObject import ClockedObject class TraceCPU(ClockedObject): diff --git a/src/dev/BadDevice.py b/src/dev/BadDevice.py index 2b630c087e..f31ecc346e 100644 --- a/src/dev/BadDevice.py +++ b/src/dev/BadDevice.py @@ -24,8 +24,8 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from m5.params import * from m5.objects.Device import BasicPioDevice +from m5.params import * class BadDevice(BasicPioDevice): diff --git a/src/dev/Device.py b/src/dev/Device.py index 7f8428e6ff..15a68c3eaa 100644 --- a/src/dev/Device.py +++ b/src/dev/Device.py @@ -36,12 +36,11 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +from m5.objects.ClockedObject import ClockedObject from m5.params import * from m5.proxy import * from m5.util.fdthelper import * -from m5.objects.ClockedObject import ClockedObject - class PioDevice(ClockedObject): type = "PioDevice" diff --git a/src/dev/IntPin.py b/src/dev/IntPin.py index 61c645af2f..d66e172433 100644 --- a/src/dev/IntPin.py +++ b/src/dev/IntPin.py @@ -23,7 +23,10 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from m5.params import Port, VectorPort +from m5.params import ( + Port, + VectorPort, +) INT_SOURCE_ROLE = "Int Source Pin" INT_SINK_ROLE = "Int Sink Pin" diff --git a/src/dev/Platform.py b/src/dev/Platform.py index 5a18f83010..5680eb6cbf 100644 --- a/src/dev/Platform.py +++ b/src/dev/Platform.py @@ -24,9 +24,9 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from m5.SimObject import SimObject from m5.params import * from m5.proxy import * +from m5.SimObject import SimObject class Platform(SimObject): diff --git a/src/dev/ResetPort.py b/src/dev/ResetPort.py index 467771a258..1c952ed380 100644 --- a/src/dev/ResetPort.py +++ b/src/dev/ResetPort.py @@ -23,7 +23,10 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from m5.params import Port, VectorPort +from m5.params import ( + Port, + VectorPort, +) RESET_REQUEST_ROLE = "Reset Request" RESET_RESPONSE_ROLE = "Reset Response" diff --git a/src/dev/amdgpu/AMDGPU.py b/src/dev/amdgpu/AMDGPU.py index 7873794109..0370f09e01 100644 --- a/src/dev/amdgpu/AMDGPU.py +++ b/src/dev/amdgpu/AMDGPU.py @@ -27,12 +27,19 @@ # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE # POSSIBILITY OF SUCH DAMAGE. +from m5.objects.ClockedObject import ClockedObject +from m5.objects.Device import ( + DmaDevice, + DmaVirtDevice, +) +from m5.objects.PciDevice import ( + PciDevice, + PciLegacyIoBar, + PciMemBar, + PciMemUpperBar, +) from m5.params import * from m5.proxy import * -from m5.objects.PciDevice import PciDevice -from m5.objects.PciDevice import PciMemBar, PciMemUpperBar, PciLegacyIoBar -from m5.objects.Device import DmaDevice, DmaVirtDevice -from m5.objects.ClockedObject import ClockedObject # PCI device model for an AMD Vega 10 based GPU. The PCI codes and BARs diff --git a/src/dev/arm/Doorbell.py b/src/dev/arm/Doorbell.py index 106a184902..3832553924 100644 --- a/src/dev/arm/Doorbell.py +++ b/src/dev/arm/Doorbell.py @@ -33,8 +33,8 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from m5.SimObject import SimObject from m5.params import * +from m5.SimObject import SimObject class Doorbell(SimObject): diff --git a/src/dev/arm/EnergyCtrl.py b/src/dev/arm/EnergyCtrl.py index 91296143c8..6a9cf99608 100644 --- a/src/dev/arm/EnergyCtrl.py +++ b/src/dev/arm/EnergyCtrl.py @@ -33,10 +33,10 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from m5.params import * -from m5.SimObject import SimObject from m5.objects.Device import BasicPioDevice +from m5.params import * from m5.proxy import * +from m5.SimObject import SimObject from m5.util.fdthelper import * diff --git a/src/dev/arm/FlashDevice.py b/src/dev/arm/FlashDevice.py index 7bd365a2ba..795e735d7c 100644 --- a/src/dev/arm/FlashDevice.py +++ b/src/dev/arm/FlashDevice.py @@ -33,11 +33,10 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +from m5.objects.AbstractNVM import * from m5.params import * from m5.proxy import * -from m5.objects.AbstractNVM import * - # Distribution of the data. # sequential: sequential (address n+1 is likely to be on the same plane as n) diff --git a/src/dev/arm/GenericTimer.py b/src/dev/arm/GenericTimer.py index 4b104ade92..fe7c1f5988 100644 --- a/src/dev/arm/GenericTimer.py +++ b/src/dev/arm/GenericTimer.py @@ -33,12 +33,22 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from m5.SimObject import SimObject from m5.objects.Device import PioDevice -from m5.params import Param, MaxAddr, NULL, VectorParam +from m5.params import ( + NULL, + MaxAddr, + Param, + VectorParam, +) from m5.proxy import Parent +from m5.SimObject import SimObject from m5.util import fatal -from m5.util.fdthelper import FdtNode, FdtProperty, FdtPropertyWords, FdtState +from m5.util.fdthelper import ( + FdtNode, + FdtProperty, + FdtPropertyWords, + FdtState, +) class SystemCounter(SimObject): diff --git a/src/dev/arm/Gic.py b/src/dev/arm/Gic.py index 6fd8eb235f..6cb03c8cb9 100644 --- a/src/dev/arm/Gic.py +++ b/src/dev/arm/Gic.py @@ -33,14 +33,16 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +from m5.objects.Device import ( + BasicPioDevice, + PioDevice, +) +from m5.objects.IntPin import IntSourcePin +from m5.objects.Platform import Platform from m5.params import * from m5.proxy import * -from m5.util.fdthelper import * from m5.SimObject import SimObject - -from m5.objects.Device import PioDevice, BasicPioDevice -from m5.objects.Platform import Platform -from m5.objects.IntPin import IntSourcePin +from m5.util.fdthelper import * class BaseGic(PioDevice): diff --git a/src/dev/arm/NoMali.py b/src/dev/arm/NoMali.py index c7d0d4259c..ea20cdf3a3 100644 --- a/src/dev/arm/NoMali.py +++ b/src/dev/arm/NoMali.py @@ -33,10 +33,9 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from m5.params import * - from m5.objects.Device import BasicPioDevice from m5.objects.Gic import * +from m5.params import * class NoMaliGpuType(Enum): diff --git a/src/dev/arm/RealView.py b/src/dev/arm/RealView.py index e71f6cee5a..a0540ec50c 100644 --- a/src/dev/arm/RealView.py +++ b/src/dev/arm/RealView.py @@ -37,48 +37,66 @@ # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. from m5.defines import buildEnv +from m5.objects.ArmSystem import ArmExtension +from m5.objects.CfiMemory import CfiMemory +from m5.objects.ClockDomain import ( + ClockDomain, + SrcClockDomain, +) +from m5.objects.ClockedObject import ClockedObject +from m5.objects.Device import ( + BadAddr, + BasicPioDevice, + DmaDevice, + IsaFake, + PioDevice, +) +from m5.objects.Display import ( + Display, + Display1080p, +) +from m5.objects.EnergyCtrl import EnergyCtrl +from m5.objects.Ethernet import ( + IGbE_e1000, + IGbE_igb, + NSGigE, +) +from m5.objects.GenericTimer import * +from m5.objects.Gic import * +from m5.objects.Graphics import ImageFormat +from m5.objects.Ide import * +from m5.objects.MHU import ( + MHU, + Ap2ScpDoorbell, + Scp2ApDoorbell, +) +from m5.objects.PciDevice import ( + PciIoBar, + PciLegacyIoBar, +) +from m5.objects.PciHost import * +from m5.objects.Platform import Platform +from m5.objects.PS2 import * +from m5.objects.Scmi import * +from m5.objects.SimpleMemory import SimpleMemory +from m5.objects.SMMUv3 import SMMUv3 +from m5.objects.SubSystem import SubSystem +from m5.objects.Terminal import Terminal +from m5.objects.Uart import Uart +from m5.objects.VirtIOMMIO import MmioVirtIO +from m5.objects.VoltageDomain import VoltageDomain from m5.params import * from m5.proxy import * from m5.util.fdthelper import * -from m5.objects.ArmSystem import ArmExtension -from m5.objects.ClockDomain import ClockDomain, SrcClockDomain -from m5.objects.VoltageDomain import VoltageDomain -from m5.objects.Device import ( - BasicPioDevice, - PioDevice, - IsaFake, - BadAddr, - DmaDevice, -) -from m5.objects.PciHost import * -from m5.objects.Ethernet import NSGigE, IGbE_igb, IGbE_e1000 -from m5.objects.Ide import * -from m5.objects.Platform import Platform -from m5.objects.Terminal import Terminal -from m5.objects.Uart import Uart -from m5.objects.SimpleMemory import SimpleMemory -from m5.objects.GenericTimer import * -from m5.objects.Gic import * -from m5.objects.MHU import MHU, Scp2ApDoorbell, Ap2ScpDoorbell -from m5.objects.EnergyCtrl import EnergyCtrl -from m5.objects.ClockedObject import ClockedObject -from m5.objects.SubSystem import SubSystem -from m5.objects.Graphics import ImageFormat -from m5.objects.ClockedObject import ClockedObject -from m5.objects.PS2 import * -from m5.objects.VirtIOMMIO import MmioVirtIO -from m5.objects.Display import Display, Display1080p -from m5.objects.Scmi import * -from m5.objects.SMMUv3 import SMMUv3 -from m5.objects.PciDevice import PciLegacyIoBar, PciIoBar - -from m5.objects.CfiMemory import CfiMemory # Platforms with KVM support should generally use in-kernel GIC # emulation. Use a GIC model that automatically switches between # gem5's GIC model and KVM's GIC model if KVM is available. try: - from m5.objects.KvmGic import MuxingKvmGicV2, MuxingKvmGicV3 + from m5.objects.KvmGic import ( + MuxingKvmGicV2, + MuxingKvmGicV3, + ) kvm_gicv2_class = MuxingKvmGicV2 kvm_gicv3_class = MuxingKvmGicV3 diff --git a/src/dev/arm/SMMUv3.py b/src/dev/arm/SMMUv3.py index 46fad3bf68..28c2c6fe24 100644 --- a/src/dev/arm/SMMUv3.py +++ b/src/dev/arm/SMMUv3.py @@ -33,11 +33,11 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +from m5.objects.ClockedObject import ClockedObject from m5.params import * from m5.proxy import * -from m5.util.fdthelper import * from m5.SimObject import * -from m5.objects.ClockedObject import ClockedObject +from m5.util.fdthelper import * class SMMUv3DeviceInterface(ClockedObject): diff --git a/src/dev/arm/UFSHostDevice.py b/src/dev/arm/UFSHostDevice.py index 46ed7ddd24..3de0684487 100644 --- a/src/dev/arm/UFSHostDevice.py +++ b/src/dev/arm/UFSHostDevice.py @@ -34,10 +34,11 @@ # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. import sys + +from m5.objects.AbstractNVM import * +from m5.objects.Device import DmaDevice from m5.params import * from m5.proxy import * -from m5.objects.Device import DmaDevice -from m5.objects.AbstractNVM import * class UFSHostDevice(DmaDevice): diff --git a/src/dev/arm/VExpressFastmodel.py b/src/dev/arm/VExpressFastmodel.py index 0dfddb7735..1135bd8b92 100644 --- a/src/dev/arm/VExpressFastmodel.py +++ b/src/dev/arm/VExpressFastmodel.py @@ -23,9 +23,15 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from m5.objects.FastModelGIC import FastModelGIC, SCFastModelGIC +from m5.objects.FastModelGIC import ( + FastModelGIC, + SCFastModelGIC, +) from m5.objects.Gic import ArmSPI -from m5.objects.RealView import VExpress_GEM5_Base, HDLcd +from m5.objects.RealView import ( + HDLcd, + VExpress_GEM5_Base, +) from m5.objects.SubSystem import SubSystem diff --git a/src/dev/arm/VirtIOMMIO.py b/src/dev/arm/VirtIOMMIO.py index eecd703e3a..d51f2aa69d 100644 --- a/src/dev/arm/VirtIOMMIO.py +++ b/src/dev/arm/VirtIOMMIO.py @@ -35,13 +35,15 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from m5.SimObject import SimObject -from m5.params import * -from m5.proxy import * - from m5.objects.Device import BasicPioDevice from m5.objects.Gic import ArmInterruptPin -from m5.objects.VirtIO import VirtIODeviceBase, VirtIODummyDevice +from m5.objects.VirtIO import ( + VirtIODeviceBase, + VirtIODummyDevice, +) +from m5.params import * +from m5.proxy import * +from m5.SimObject import SimObject class MmioVirtIO(BasicPioDevice): diff --git a/src/dev/arm/css/Scmi.py b/src/dev/arm/css/Scmi.py index 1246e69343..4ae616d209 100644 --- a/src/dev/arm/css/Scmi.py +++ b/src/dev/arm/css/Scmi.py @@ -33,12 +33,12 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +from m5.objects.Doorbell import Doorbell +from m5.objects.Scp import Scp from m5.params import * from m5.proxy import * -from m5.objects.Scp import Scp -from m5.objects.Doorbell import Doorbell -from m5.util.fdthelper import * from m5.SimObject import SimObject +from m5.util.fdthelper import * class ScmiChannel(SimObject): diff --git a/src/dev/hsa/HSADevice.py b/src/dev/hsa/HSADevice.py index b22269d5bb..ed3b2d8086 100644 --- a/src/dev/hsa/HSADevice.py +++ b/src/dev/hsa/HSADevice.py @@ -27,11 +27,11 @@ # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE # POSSIBILITY OF SUCH DAMAGE. -from m5.SimObject import SimObject -from m5.params import * -from m5.proxy import * from m5.objects.Device import DmaVirtDevice from m5.objects.VegaGPUTLB import VegaPagetableWalker +from m5.params import * +from m5.proxy import * +from m5.SimObject import SimObject class HSAPacketProcessor(DmaVirtDevice): diff --git a/src/dev/hsa/HSADriver.py b/src/dev/hsa/HSADriver.py index c3e12df4d2..99c81ecc86 100644 --- a/src/dev/hsa/HSADriver.py +++ b/src/dev/hsa/HSADriver.py @@ -27,10 +27,10 @@ # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE # POSSIBILITY OF SUCH DAMAGE. -from m5.SimObject import SimObject +from m5.objects.Process import EmulatedDriver from m5.params import * from m5.proxy import * -from m5.objects.Process import EmulatedDriver +from m5.SimObject import SimObject class HSADriver(EmulatedDriver): diff --git a/src/dev/i2c/I2C.py b/src/dev/i2c/I2C.py index 1d3de26d29..df0743f5d8 100644 --- a/src/dev/i2c/I2C.py +++ b/src/dev/i2c/I2C.py @@ -33,9 +33,9 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from m5.SimObject import SimObject -from m5.params import * from m5.objects.Device import BasicPioDevice +from m5.params import * +from m5.SimObject import SimObject class I2CDevice(SimObject): diff --git a/src/dev/lupio/LupioBLK.py b/src/dev/lupio/LupioBLK.py index e230e23fed..a41a6f249a 100644 --- a/src/dev/lupio/LupioBLK.py +++ b/src/dev/lupio/LupioBLK.py @@ -25,7 +25,6 @@ # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. from m5.objects.Device import DmaDevice - from m5.params import Param from m5.proxy import Parent diff --git a/src/dev/lupio/LupioTTY.py b/src/dev/lupio/LupioTTY.py index ff35004481..6c0f2efff5 100644 --- a/src/dev/lupio/LupioTTY.py +++ b/src/dev/lupio/LupioTTY.py @@ -24,11 +24,10 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +from m5.objects.Device import BasicPioDevice from m5.params import Param from m5.proxy import Parent -from m5.objects.Device import BasicPioDevice - class LupioTTY(BasicPioDevice): type = "LupioTTY" diff --git a/src/dev/mips/Malta.py b/src/dev/mips/Malta.py index 9199bd5b3f..a8def0b0c0 100755 --- a/src/dev/mips/Malta.py +++ b/src/dev/mips/Malta.py @@ -24,13 +24,12 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from m5.params import * -from m5.proxy import * - from m5.objects.BadDevice import BadDevice from m5.objects.Device import BasicPioDevice from m5.objects.Platform import Platform from m5.objects.Uart import Uart8250 +from m5.params import * +from m5.proxy import * class MaltaCChip(BasicPioDevice): diff --git a/src/dev/net/Ethernet.py b/src/dev/net/Ethernet.py index 72f2061b2b..495e7da211 100644 --- a/src/dev/net/Ethernet.py +++ b/src/dev/net/Ethernet.py @@ -37,10 +37,14 @@ # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. from m5.defines import buildEnv -from m5.SimObject import SimObject +from m5.objects.PciDevice import ( + PciDevice, + PciIoBar, + PciMemBar, +) from m5.params import * from m5.proxy import * -from m5.objects.PciDevice import PciDevice, PciIoBar, PciMemBar +from m5.SimObject import SimObject ETHERNET_ROLE = "ETHERNET" Port.compat(ETHERNET_ROLE, ETHERNET_ROLE) diff --git a/src/dev/pci/CopyEngine.py b/src/dev/pci/CopyEngine.py index 821f7c5cf0..89d01e19b3 100644 --- a/src/dev/pci/CopyEngine.py +++ b/src/dev/pci/CopyEngine.py @@ -24,11 +24,13 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from m5.SimObject import SimObject +from m5.objects.PciDevice import ( + PciDevice, + PciMemBar, +) from m5.params import * from m5.proxy import * - -from m5.objects.PciDevice import PciDevice, PciMemBar +from m5.SimObject import SimObject class CopyEngine(PciDevice): diff --git a/src/dev/pci/PciDevice.py b/src/dev/pci/PciDevice.py index 8466101287..f8c0c1ba6e 100644 --- a/src/dev/pci/PciDevice.py +++ b/src/dev/pci/PciDevice.py @@ -36,11 +36,11 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from m5.SimObject import SimObject -from m5.params import * -from m5.proxy import * from m5.objects.Device import DmaDevice from m5.objects.PciHost import PciHost +from m5.params import * +from m5.proxy import * +from m5.SimObject import SimObject class PciBar(SimObject): diff --git a/src/dev/pci/PciHost.py b/src/dev/pci/PciHost.py index 58f8eb5a78..5fef19eb92 100644 --- a/src/dev/pci/PciHost.py +++ b/src/dev/pci/PciHost.py @@ -33,11 +33,11 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from m5.SimObject import SimObject -from m5.params import * -from m5.proxy import * from m5.objects.Device import PioDevice from m5.objects.Platform import Platform +from m5.params import * +from m5.proxy import * +from m5.SimObject import SimObject class PciHost(PioDevice): diff --git a/src/dev/ps2/PS2.py b/src/dev/ps2/PS2.py index 9a0b16495f..6aa3373535 100644 --- a/src/dev/ps2/PS2.py +++ b/src/dev/ps2/PS2.py @@ -33,9 +33,9 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from m5.SimObject import SimObject from m5.params import * from m5.proxy import * +from m5.SimObject import SimObject class PS2Device(SimObject): diff --git a/src/dev/qemu/QemuFwCfg.py b/src/dev/qemu/QemuFwCfg.py index bb237b9bfc..a71a07e52f 100644 --- a/src/dev/qemu/QemuFwCfg.py +++ b/src/dev/qemu/QemuFwCfg.py @@ -23,9 +23,9 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from m5.params import * -from m5.objects.SimObject import SimObject from m5.objects.Device import PioDevice +from m5.objects.SimObject import SimObject +from m5.params import * class QemuFwCfgItem(SimObject): diff --git a/src/dev/riscv/HiFive.py b/src/dev/riscv/HiFive.py index c3d51aa5e7..04b2672ea8 100755 --- a/src/dev/riscv/HiFive.py +++ b/src/dev/riscv/HiFive.py @@ -35,19 +35,18 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from m5.objects.Platform import Platform -from m5.objects.PMAChecker import PMAChecker from m5.objects.Clint import Clint +from m5.objects.PciHost import GenericPciHost +from m5.objects.Platform import Platform from m5.objects.Plic import Plic +from m5.objects.PMAChecker import PMAChecker from m5.objects.RTC import RiscvRTC -from m5.objects.Uart import RiscvUart8250 from m5.objects.Terminal import Terminal +from m5.objects.Uart import RiscvUart8250 from m5.params import * from m5.proxy import * from m5.util.fdthelper import * -from m5.objects.PciHost import GenericPciHost - class GenericRiscvPciHost(GenericPciHost): type = "GenericRiscvPciHost" diff --git a/src/dev/riscv/RTC.py b/src/dev/riscv/RTC.py index a6559eaf48..66f691e79c 100644 --- a/src/dev/riscv/RTC.py +++ b/src/dev/riscv/RTC.py @@ -33,10 +33,10 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +from m5.objects.IntPin import IntSourcePin from m5.params import * from m5.proxy import * from m5.SimObject import SimObject -from m5.objects.IntPin import IntSourcePin class RiscvRTC(SimObject): diff --git a/src/dev/riscv/RiscvVirtIOMMIO.py b/src/dev/riscv/RiscvVirtIOMMIO.py index 17019502fa..7a343715ad 100644 --- a/src/dev/riscv/RiscvVirtIOMMIO.py +++ b/src/dev/riscv/RiscvVirtIOMMIO.py @@ -34,13 +34,12 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from m5.SimObject import SimObject -from m5.params import * -from m5.proxy import * -from m5.util.fdthelper import * - from m5.objects.PlicDevice import PlicIntDevice from m5.objects.VirtIO import VirtIODummyDevice +from m5.params import * +from m5.proxy import * +from m5.SimObject import SimObject +from m5.util.fdthelper import * class RiscvMmioVirtIO(PlicIntDevice): diff --git a/src/dev/serial/Terminal.py b/src/dev/serial/Terminal.py index a08a18fe1e..28abf7572a 100644 --- a/src/dev/serial/Terminal.py +++ b/src/dev/serial/Terminal.py @@ -36,11 +36,10 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from m5.SimObject import SimObject +from m5.objects.Serial import SerialDevice from m5.params import * from m5.proxy import * - -from m5.objects.Serial import SerialDevice +from m5.SimObject import SimObject class TerminalDump(ScopedEnum): diff --git a/src/dev/serial/Uart.py b/src/dev/serial/Uart.py index fb0d91efa4..7de6582ba0 100644 --- a/src/dev/serial/Uart.py +++ b/src/dev/serial/Uart.py @@ -36,13 +36,12 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +from m5.defines import buildEnv +from m5.objects.Device import BasicPioDevice +from m5.objects.Serial import SerialDevice from m5.params import * from m5.proxy import * from m5.util.fdthelper import * -from m5.defines import buildEnv - -from m5.objects.Device import BasicPioDevice -from m5.objects.Serial import SerialDevice class Uart(BasicPioDevice): diff --git a/src/dev/sparc/T1000.py b/src/dev/sparc/T1000.py index d797c5fc13..b4042ecb9f 100644 --- a/src/dev/sparc/T1000.py +++ b/src/dev/sparc/T1000.py @@ -24,13 +24,17 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from m5.params import * -from m5.proxy import * - -from m5.objects.Device import BasicPioDevice, PioDevice, IsaFake, BadAddr +from m5.objects.Device import ( + BadAddr, + BasicPioDevice, + IsaFake, + PioDevice, +) from m5.objects.Platform import Platform from m5.objects.Terminal import Terminal from m5.objects.Uart import Uart8250 +from m5.params import * +from m5.proxy import * class MmDisk(BasicPioDevice): diff --git a/src/dev/storage/DiskImage.py b/src/dev/storage/DiskImage.py index e7657e556c..c02d65fbef 100644 --- a/src/dev/storage/DiskImage.py +++ b/src/dev/storage/DiskImage.py @@ -24,8 +24,8 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from m5.SimObject import SimObject from m5.params import * +from m5.SimObject import SimObject class DiskImage(SimObject): diff --git a/src/dev/storage/Ide.py b/src/dev/storage/Ide.py index 7498a52ecb..348e9e3d7b 100644 --- a/src/dev/storage/Ide.py +++ b/src/dev/storage/Ide.py @@ -24,9 +24,12 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from m5.SimObject import SimObject +from m5.objects.PciDevice import ( + PciDevice, + PciIoBar, +) from m5.params import * -from m5.objects.PciDevice import PciDevice, PciIoBar +from m5.SimObject import SimObject class IdeID(Enum): diff --git a/src/dev/storage/SimpleDisk.py b/src/dev/storage/SimpleDisk.py index 252ce38a42..21ff037630 100644 --- a/src/dev/storage/SimpleDisk.py +++ b/src/dev/storage/SimpleDisk.py @@ -24,9 +24,9 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from m5.SimObject import SimObject from m5.params import * from m5.proxy import * +from m5.SimObject import SimObject class SimpleDisk(SimObject): diff --git a/src/dev/virtio/VirtIO.py b/src/dev/virtio/VirtIO.py index 1d652bca64..a009745caf 100644 --- a/src/dev/virtio/VirtIO.py +++ b/src/dev/virtio/VirtIO.py @@ -35,11 +35,14 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from m5.SimObject import SimObject +from m5.objects.Device import PioDevice +from m5.objects.PciDevice import ( + PciDevice, + PciIoBar, +) from m5.params import * from m5.proxy import * -from m5.objects.Device import PioDevice -from m5.objects.PciDevice import PciDevice, PciIoBar +from m5.SimObject import SimObject class VirtIODeviceBase(SimObject): diff --git a/src/dev/virtio/VirtIO9P.py b/src/dev/virtio/VirtIO9P.py index b6611713b7..37c9e481cb 100644 --- a/src/dev/virtio/VirtIO9P.py +++ b/src/dev/virtio/VirtIO9P.py @@ -35,9 +35,9 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +from m5.objects.VirtIO import VirtIODeviceBase from m5.params import * from m5.proxy import * -from m5.objects.VirtIO import VirtIODeviceBase class VirtIO9PBase(VirtIODeviceBase): diff --git a/src/dev/virtio/VirtIOBlock.py b/src/dev/virtio/VirtIOBlock.py index 6a75c00956..bc9394cf2f 100644 --- a/src/dev/virtio/VirtIOBlock.py +++ b/src/dev/virtio/VirtIOBlock.py @@ -35,9 +35,9 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +from m5.objects.VirtIO import VirtIODeviceBase from m5.params import * from m5.proxy import * -from m5.objects.VirtIO import VirtIODeviceBase class VirtIOBlock(VirtIODeviceBase): diff --git a/src/dev/virtio/VirtIOConsole.py b/src/dev/virtio/VirtIOConsole.py index 72826aa6fb..b1f5e850e7 100644 --- a/src/dev/virtio/VirtIOConsole.py +++ b/src/dev/virtio/VirtIOConsole.py @@ -35,10 +35,10 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +from m5.objects.Serial import SerialDevice +from m5.objects.VirtIO import VirtIODeviceBase from m5.params import * from m5.proxy import * -from m5.objects.VirtIO import VirtIODeviceBase -from m5.objects.Serial import SerialDevice class VirtIOConsole(VirtIODeviceBase): diff --git a/src/dev/virtio/VirtIORng 2.py b/src/dev/virtio/VirtIORng 2.py index 925fccdabe..5d5db04992 100644 --- a/src/dev/virtio/VirtIORng 2.py +++ b/src/dev/virtio/VirtIORng 2.py @@ -36,9 +36,9 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +from m5.objects.VirtIO import VirtIODeviceBase from m5.params import * from m5.proxy import * -from m5.objects.VirtIO import VirtIODeviceBase class VirtIORng(VirtIODeviceBase): diff --git a/src/dev/virtio/VirtIORng.py b/src/dev/virtio/VirtIORng.py index 925fccdabe..5d5db04992 100644 --- a/src/dev/virtio/VirtIORng.py +++ b/src/dev/virtio/VirtIORng.py @@ -36,9 +36,9 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +from m5.objects.VirtIO import VirtIODeviceBase from m5.params import * from m5.proxy import * -from m5.objects.VirtIO import VirtIODeviceBase class VirtIORng(VirtIODeviceBase): diff --git a/src/dev/x86/Cmos.py b/src/dev/x86/Cmos.py index ccc14de8c1..049cc4ea33 100644 --- a/src/dev/x86/Cmos.py +++ b/src/dev/x86/Cmos.py @@ -24,10 +24,10 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from m5.params import * -from m5.proxy import * from m5.objects.Device import BasicPioDevice from m5.objects.IntPin import IntSourcePin +from m5.params import * +from m5.proxy import * class Cmos(BasicPioDevice): diff --git a/src/dev/x86/I8042.py b/src/dev/x86/I8042.py index 0dae054588..e357ac91f3 100644 --- a/src/dev/x86/I8042.py +++ b/src/dev/x86/I8042.py @@ -24,11 +24,11 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from m5.params import * -from m5.proxy import * from m5.objects.Device import PioDevice from m5.objects.IntPin import IntSourcePin from m5.objects.PS2 import * +from m5.params import * +from m5.proxy import * class I8042(PioDevice): diff --git a/src/dev/x86/I82094AA.py b/src/dev/x86/I82094AA.py index 228bc5a5eb..45ee9a3d2b 100644 --- a/src/dev/x86/I82094AA.py +++ b/src/dev/x86/I82094AA.py @@ -24,10 +24,10 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from m5.params import * -from m5.proxy import * from m5.objects.Device import BasicPioDevice from m5.objects.IntPin import VectorIntSinkPin +from m5.params import * +from m5.proxy import * class I82094AA(BasicPioDevice): diff --git a/src/dev/x86/I8237.py b/src/dev/x86/I8237.py index b8a8a8ce51..60f472f48c 100644 --- a/src/dev/x86/I8237.py +++ b/src/dev/x86/I8237.py @@ -24,9 +24,9 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +from m5.objects.Device import BasicPioDevice from m5.params import * from m5.proxy import * -from m5.objects.Device import BasicPioDevice class I8237(BasicPioDevice): diff --git a/src/dev/x86/I8254.py b/src/dev/x86/I8254.py index 545f13739a..660bee0e62 100644 --- a/src/dev/x86/I8254.py +++ b/src/dev/x86/I8254.py @@ -24,10 +24,10 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from m5.params import * -from m5.proxy import * from m5.objects.Device import BasicPioDevice from m5.objects.IntPin import IntSourcePin +from m5.params import * +from m5.proxy import * class I8254(BasicPioDevice): diff --git a/src/dev/x86/I8259.py b/src/dev/x86/I8259.py index 5fcef01f3c..6791c57be2 100644 --- a/src/dev/x86/I8259.py +++ b/src/dev/x86/I8259.py @@ -24,10 +24,13 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +from m5.objects.Device import BasicPioDevice +from m5.objects.IntPin import ( + IntSourcePin, + VectorIntSinkPin, +) from m5.params import * from m5.proxy import * -from m5.objects.Device import BasicPioDevice -from m5.objects.IntPin import IntSourcePin, VectorIntSinkPin class X86I8259CascadeMode(Enum): diff --git a/src/dev/x86/Pc.py b/src/dev/x86/Pc.py index 0039d67230..fd51e14268 100644 --- a/src/dev/x86/Pc.py +++ b/src/dev/x86/Pc.py @@ -24,16 +24,18 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from m5.params import * -from m5.proxy import * - -from m5.objects.Device import IsaFake, BadAddr +from m5.objects.Device import ( + BadAddr, + IsaFake, +) +from m5.objects.PciHost import GenericPciHost from m5.objects.Platform import Platform from m5.objects.SouthBridge import SouthBridge from m5.objects.Terminal import Terminal from m5.objects.Uart import Uart8250 -from m5.objects.PciHost import GenericPciHost from m5.objects.XBar import IOXBar +from m5.params import * +from m5.proxy import * def x86IOAddress(port): diff --git a/src/dev/x86/PcSpeaker.py b/src/dev/x86/PcSpeaker.py index 3337b6a07b..1ca7d25967 100644 --- a/src/dev/x86/PcSpeaker.py +++ b/src/dev/x86/PcSpeaker.py @@ -24,9 +24,9 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +from m5.objects.Device import BasicPioDevice from m5.params import * from m5.proxy import * -from m5.objects.Device import BasicPioDevice class PcSpeaker(BasicPioDevice): diff --git a/src/dev/x86/SouthBridge.py b/src/dev/x86/SouthBridge.py index 670f687175..ec117c917b 100644 --- a/src/dev/x86/SouthBridge.py +++ b/src/dev/x86/SouthBridge.py @@ -24,17 +24,20 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from m5.params import * -from m5.proxy import * from m5.objects.Cmos import Cmos from m5.objects.I8042 import I8042 -from m5.objects.I82094AA import I82094AA from m5.objects.I8237 import I8237 from m5.objects.I8254 import I8254 from m5.objects.I8259 import I8259 -from m5.objects.PciDevice import PciLegacyIoBar, PciIoBar +from m5.objects.I82094AA import I82094AA +from m5.objects.PciDevice import ( + PciIoBar, + PciLegacyIoBar, +) from m5.objects.PcSpeaker import PcSpeaker from m5.objects.X86Ide import X86IdeController +from m5.params import * +from m5.proxy import * from m5.SimObject import SimObject diff --git a/src/dev/x86/X86Ide.py b/src/dev/x86/X86Ide.py index 9ae0704503..50ac43e396 100644 --- a/src/dev/x86/X86Ide.py +++ b/src/dev/x86/X86Ide.py @@ -23,11 +23,11 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from m5.SimObject import SimObject -from m5.params import * from m5.objects.Ide import IdeController from m5.objects.IntPin import IntSourcePin from m5.objects.PciDevice import PciLegacyIoBar +from m5.params import * +from m5.SimObject import SimObject class X86IdeController(IdeController): diff --git a/src/dev/x86/X86QemuFwCfg.py b/src/dev/x86/X86QemuFwCfg.py index 4998f9a8b5..b9451f4f50 100644 --- a/src/dev/x86/X86QemuFwCfg.py +++ b/src/dev/x86/X86QemuFwCfg.py @@ -23,9 +23,12 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from m5.params import * from m5.objects.E820 import X86E820Entry -from m5.objects.QemuFwCfg import QemuFwCfgIo, QemuFwCfgItem +from m5.objects.QemuFwCfg import ( + QemuFwCfgIo, + QemuFwCfgItem, +) +from m5.params import * def x86IOAddress(port): diff --git a/src/gpu-compute/GPU.py b/src/gpu-compute/GPU.py index 1b6c6a7494..3c294648a9 100644 --- a/src/gpu-compute/GPU.py +++ b/src/gpu-compute/GPU.py @@ -29,16 +29,15 @@ from m5.citations import add_citation from m5.defines import buildEnv -from m5.params import * -from m5.proxy import * -from m5.SimObject import SimObject - from m5.objects.Bridge import Bridge from m5.objects.ClockedObject import ClockedObject from m5.objects.Device import DmaVirtDevice from m5.objects.LdsState import LdsState from m5.objects.Process import EmulatedDriver from m5.objects.VegaGPUTLB import VegaPagetableWalker +from m5.params import * +from m5.proxy import * +from m5.SimObject import SimObject class PrefetchType(Enum): diff --git a/src/gpu-compute/LdsState.py b/src/gpu-compute/LdsState.py index c81859331c..e57ed9cc5b 100644 --- a/src/gpu-compute/LdsState.py +++ b/src/gpu-compute/LdsState.py @@ -28,11 +28,10 @@ # POSSIBILITY OF SUCH DAMAGE. from m5.defines import buildEnv +from m5.objects.ClockedObject import ClockedObject from m5.params import * from m5.proxy import * -from m5.objects.ClockedObject import ClockedObject - class LdsState(ClockedObject): type = "LdsState" diff --git a/src/learning_gem5/part2/SimpleCache.py b/src/learning_gem5/part2/SimpleCache.py index 6cdce84580..86c09fc09d 100644 --- a/src/learning_gem5/part2/SimpleCache.py +++ b/src/learning_gem5/part2/SimpleCache.py @@ -24,9 +24,9 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +from m5.objects.ClockedObject import ClockedObject from m5.params import * from m5.proxy import * -from m5.objects.ClockedObject import ClockedObject class SimpleCache(ClockedObject): diff --git a/src/mem/AbstractMemory.py b/src/mem/AbstractMemory.py index 7ab24bc118..57e47adcb1 100644 --- a/src/mem/AbstractMemory.py +++ b/src/mem/AbstractMemory.py @@ -36,8 +36,8 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from m5.params import * from m5.objects.ClockedObject import ClockedObject +from m5.params import * class AbstractMemory(ClockedObject): diff --git a/src/mem/Bridge.py b/src/mem/Bridge.py index 8131d62ef8..ff89d742b6 100644 --- a/src/mem/Bridge.py +++ b/src/mem/Bridge.py @@ -36,8 +36,8 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from m5.params import * from m5.objects.ClockedObject import ClockedObject +from m5.params import * class Bridge(ClockedObject): diff --git a/src/mem/CfiMemory.py b/src/mem/CfiMemory.py index c8de9e511e..5af534a6a9 100644 --- a/src/mem/CfiMemory.py +++ b/src/mem/CfiMemory.py @@ -36,9 +36,12 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from m5.params import * from m5.objects.AbstractMemory import AbstractMemory -from m5.util.fdthelper import FdtNode, FdtPropertyWords +from m5.params import * +from m5.util.fdthelper import ( + FdtNode, + FdtPropertyWords, +) class CfiMemory(AbstractMemory): diff --git a/src/mem/CommMonitor.py b/src/mem/CommMonitor.py index e0040b74e0..739ecad8bf 100644 --- a/src/mem/CommMonitor.py +++ b/src/mem/CommMonitor.py @@ -33,9 +33,9 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +from m5.objects.System import System from m5.params import * from m5.proxy import * -from m5.objects.System import System from m5.SimObject import SimObject diff --git a/src/mem/DRAMSim2.py b/src/mem/DRAMSim2.py index 037baaa8b5..032fd80a35 100644 --- a/src/mem/DRAMSim2.py +++ b/src/mem/DRAMSim2.py @@ -35,8 +35,8 @@ from citations import add_citation -from m5.params import * from m5.objects.AbstractMemory import * +from m5.params import * # A wrapper for DRAMSim2 multi-channel memory controller diff --git a/src/mem/DRAMSys.py b/src/mem/DRAMSys.py index 4b2df67dde..04c7a66487 100644 --- a/src/mem/DRAMSys.py +++ b/src/mem/DRAMSys.py @@ -25,13 +25,11 @@ # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. from m5.citations import add_citation - -from m5.SimObject import * +from m5.objects.AbstractMemory import * +from m5.objects.Tlm import TlmTargetSocket from m5.params import * from m5.proxy import * - -from m5.objects.Tlm import TlmTargetSocket -from m5.objects.AbstractMemory import * +from m5.SimObject import * class DRAMSys(AbstractMemory): diff --git a/src/mem/DRAMsim3.py b/src/mem/DRAMsim3.py index de70293258..3500c18ecd 100644 --- a/src/mem/DRAMsim3.py +++ b/src/mem/DRAMsim3.py @@ -34,9 +34,8 @@ # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. from m5.citations import add_citation - -from m5.params import * from m5.objects.AbstractMemory import * +from m5.params import * # A wrapper for DRAMSim3 multi-channel memory controller diff --git a/src/mem/HBMCtrl.py b/src/mem/HBMCtrl.py index 45d89a76c9..292ad40ff0 100644 --- a/src/mem/HBMCtrl.py +++ b/src/mem/HBMCtrl.py @@ -24,9 +24,9 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +from m5.objects.MemCtrl import * from m5.params import * from m5.proxy import * -from m5.objects.MemCtrl import * # HBMCtrl manages two pseudo channels of HBM2 diff --git a/src/mem/HMCController.py b/src/mem/HMCController.py index ba5495b71f..dfae48374b 100644 --- a/src/mem/HMCController.py +++ b/src/mem/HMCController.py @@ -36,8 +36,8 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from m5.params import * from m5.objects.XBar import * +from m5.params import * # References: # [1] http://www.open-silicon.com/open-silicon-ips/hmc/ diff --git a/src/mem/HeteroMemCtrl.py b/src/mem/HeteroMemCtrl.py index 8bddc94086..f54da2ec91 100644 --- a/src/mem/HeteroMemCtrl.py +++ b/src/mem/HeteroMemCtrl.py @@ -38,9 +38,9 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +from m5.objects.MemCtrl import * from m5.params import * from m5.proxy import * -from m5.objects.MemCtrl import * # HeteroMemCtrl controls a dram and an nvm interface diff --git a/src/mem/MemChecker.py b/src/mem/MemChecker.py index fcee653265..4fab7b9a7a 100644 --- a/src/mem/MemChecker.py +++ b/src/mem/MemChecker.py @@ -33,9 +33,9 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from m5.SimObject import SimObject from m5.params import * from m5.proxy import * +from m5.SimObject import SimObject class MemChecker(SimObject): diff --git a/src/mem/MemCtrl.py b/src/mem/MemCtrl.py index eca15877e5..215ae271eb 100644 --- a/src/mem/MemCtrl.py +++ b/src/mem/MemCtrl.py @@ -38,10 +38,10 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +from m5.citations import add_citation +from m5.objects.QoSMemCtrl import * from m5.params import * from m5.proxy import * -from m5.objects.QoSMemCtrl import * -from m5.citations import add_citation # Enum for memory scheduling algorithms, currently First-Come diff --git a/src/mem/MemDelay.py b/src/mem/MemDelay.py index eb4aaa7bf1..52124f0b56 100644 --- a/src/mem/MemDelay.py +++ b/src/mem/MemDelay.py @@ -33,8 +33,8 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from m5.params import * from m5.objects.ClockedObject import ClockedObject +from m5.params import * class MemDelay(ClockedObject): diff --git a/src/mem/MemInterface.py b/src/mem/MemInterface.py index 424e6320ac..512acab405 100644 --- a/src/mem/MemInterface.py +++ b/src/mem/MemInterface.py @@ -38,11 +38,10 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +from m5.objects.AbstractMemory import AbstractMemory from m5.params import * from m5.proxy import * -from m5.objects.AbstractMemory import AbstractMemory - # Enum for the address mapping. With Ch, Ra, Ba, Ro and Co denoting # channel, rank, bank, row and column, respectively, and going from diff --git a/src/mem/NVMInterface.py b/src/mem/NVMInterface.py index 66b1f9401e..8289fd29c7 100644 --- a/src/mem/NVMInterface.py +++ b/src/mem/NVMInterface.py @@ -33,11 +33,11 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from m5.params import * -from m5.proxy import * +from m5.objects.DRAMInterface import AddrMap from m5.objects.MemCtrl import MemCtrl from m5.objects.MemInterface import MemInterface -from m5.objects.DRAMInterface import AddrMap +from m5.params import * +from m5.proxy import * # The following interface aims to model byte-addressable NVM diff --git a/src/mem/SerialLink.py b/src/mem/SerialLink.py index 6b767050d6..66d87786f2 100644 --- a/src/mem/SerialLink.py +++ b/src/mem/SerialLink.py @@ -37,8 +37,8 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from m5.params import * from m5.objects.ClockedObject import ClockedObject +from m5.params import * # SerialLink is a simple variation of the Bridge class, with the ability to # account for the latency of packet serialization. diff --git a/src/mem/SharedMemoryServer.py b/src/mem/SharedMemoryServer.py index 97004224de..b0461b614d 100644 --- a/src/mem/SharedMemoryServer.py +++ b/src/mem/SharedMemoryServer.py @@ -1,6 +1,6 @@ -from m5.SimObject import SimObject from m5.params import Param from m5.proxy import Parent +from m5.SimObject import SimObject class SharedMemoryServer(SimObject): diff --git a/src/mem/SimpleMemory.py b/src/mem/SimpleMemory.py index fefda187f2..e0256d7df1 100644 --- a/src/mem/SimpleMemory.py +++ b/src/mem/SimpleMemory.py @@ -36,8 +36,8 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from m5.params import * from m5.objects.AbstractMemory import * +from m5.params import * class SimpleMemory(AbstractMemory): diff --git a/src/mem/ThreadBridge.py b/src/mem/ThreadBridge.py index f0ee0897ce..9f76655976 100644 --- a/src/mem/ThreadBridge.py +++ b/src/mem/ThreadBridge.py @@ -23,8 +23,8 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from m5.SimObject import SimObject from m5.params import * +from m5.SimObject import SimObject class ThreadBridge(SimObject): diff --git a/src/mem/XBar.py b/src/mem/XBar.py index d0becc22a8..927d3bbe36 100644 --- a/src/mem/XBar.py +++ b/src/mem/XBar.py @@ -36,13 +36,12 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +from m5.objects.ClockedObject import ClockedObject from m5.objects.System import System from m5.params import * from m5.proxy import * from m5.SimObject import SimObject -from m5.objects.ClockedObject import ClockedObject - class BaseXBar(ClockedObject): type = "BaseXBar" diff --git a/src/mem/cache/Cache.py b/src/mem/cache/Cache.py index d853a08cd9..ed4851e69a 100644 --- a/src/mem/cache/Cache.py +++ b/src/mem/cache/Cache.py @@ -36,15 +36,14 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from m5.params import * -from m5.proxy import * -from m5.SimObject import SimObject - from m5.objects.ClockedObject import ClockedObject from m5.objects.Compressors import BaseCacheCompressor from m5.objects.Prefetcher import BasePrefetcher from m5.objects.ReplacementPolicies import * from m5.objects.Tags import * +from m5.params import * +from m5.proxy import * +from m5.SimObject import SimObject # Enum for cache clusivity, currently mostly inclusive or mostly diff --git a/src/mem/cache/compressors/Compressors.py b/src/mem/cache/compressors/Compressors.py index eef5f77a18..8bd9a1a6a2 100644 --- a/src/mem/cache/compressors/Compressors.py +++ b/src/mem/cache/compressors/Compressors.py @@ -24,13 +24,12 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +from m5.objects.IndexingPolicies import * +from m5.objects.ReplacementPolicies import * from m5.params import * from m5.proxy import * from m5.SimObject import * -from m5.objects.IndexingPolicies import * -from m5.objects.ReplacementPolicies import * - class BaseCacheCompressor(SimObject): type = "BaseCacheCompressor" diff --git a/src/mem/cache/prefetch/Prefetcher.py b/src/mem/cache/prefetch/Prefetcher.py index ecc67f4857..0a8c91d538 100644 --- a/src/mem/cache/prefetch/Prefetcher.py +++ b/src/mem/cache/prefetch/Prefetcher.py @@ -36,13 +36,12 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from m5.SimObject import * -from m5.params import * -from m5.proxy import * - from m5.objects.ClockedObject import ClockedObject from m5.objects.IndexingPolicies import * from m5.objects.ReplacementPolicies import * +from m5.params import * +from m5.proxy import * +from m5.SimObject import * class HWPProbeEvent: diff --git a/src/mem/cache/tags/Tags.py b/src/mem/cache/tags/Tags.py index ade187fa39..2717373829 100644 --- a/src/mem/cache/tags/Tags.py +++ b/src/mem/cache/tags/Tags.py @@ -33,10 +33,10 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from m5.params import * -from m5.proxy import * from m5.objects.ClockedObject import ClockedObject from m5.objects.IndexingPolicies import * +from m5.params import * +from m5.proxy import * class BaseTags(ClockedObject): diff --git a/src/mem/probes/MemFootprintProbe.py b/src/mem/probes/MemFootprintProbe.py index 707a8b688f..46831415f5 100644 --- a/src/mem/probes/MemFootprintProbe.py +++ b/src/mem/probes/MemFootprintProbe.py @@ -34,11 +34,10 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +from m5.objects.BaseMemProbe import BaseMemProbe from m5.params import * from m5.proxy import * -from m5.objects.BaseMemProbe import BaseMemProbe - class MemFootprintProbe(BaseMemProbe): type = "MemFootprintProbe" diff --git a/src/mem/probes/MemTraceProbe.py b/src/mem/probes/MemTraceProbe.py index d848e9ed61..6820e0732e 100644 --- a/src/mem/probes/MemTraceProbe.py +++ b/src/mem/probes/MemTraceProbe.py @@ -33,9 +33,9 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +from m5.objects.BaseMemProbe import BaseMemProbe from m5.params import * from m5.proxy import * -from m5.objects.BaseMemProbe import BaseMemProbe class MemTraceProbe(BaseMemProbe): diff --git a/src/mem/probes/StackDistProbe.py b/src/mem/probes/StackDistProbe.py index 5b44d9d333..a62fb5a5b5 100644 --- a/src/mem/probes/StackDistProbe.py +++ b/src/mem/probes/StackDistProbe.py @@ -33,9 +33,9 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +from m5.objects.BaseMemProbe import BaseMemProbe from m5.params import * from m5.proxy import * -from m5.objects.BaseMemProbe import BaseMemProbe class StackDistProbe(BaseMemProbe): diff --git a/src/mem/qos/QoSMemCtrl.py b/src/mem/qos/QoSMemCtrl.py index 86ed03196f..280d1d1e1b 100644 --- a/src/mem/qos/QoSMemCtrl.py +++ b/src/mem/qos/QoSMemCtrl.py @@ -33,10 +33,10 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from m5.params import * -from m5.proxy import * from m5.objects.ClockedObject import ClockedObject from m5.objects.QoSTurnaround import * +from m5.params import * +from m5.proxy import * # QoS Queue Selection policy used to select packets among same-QoS queues diff --git a/src/mem/qos/QoSMemSinkCtrl.py b/src/mem/qos/QoSMemSinkCtrl.py index dac0fb5be6..8eed316d28 100644 --- a/src/mem/qos/QoSMemSinkCtrl.py +++ b/src/mem/qos/QoSMemSinkCtrl.py @@ -35,9 +35,9 @@ # # Author: Matteo Andreozzi -from m5.params import * from m5.objects.QoSMemCtrl import * from m5.objects.QoSMemSinkInterface import * +from m5.params import * class QoSMemSinkCtrl(QoSMemCtrl): diff --git a/src/mem/qos/QoSPolicy.py b/src/mem/qos/QoSPolicy.py index ef44121567..0736d0367d 100644 --- a/src/mem/qos/QoSPolicy.py +++ b/src/mem/qos/QoSPolicy.py @@ -33,8 +33,8 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from m5.SimObject import * from m5.params import * +from m5.SimObject import * # QoS scheduler policy used to serve incoming transaction diff --git a/src/mem/ruby/network/BasicRouter.py b/src/mem/ruby/network/BasicRouter.py index 933470daec..ee74eaa1f4 100644 --- a/src/mem/ruby/network/BasicRouter.py +++ b/src/mem/ruby/network/BasicRouter.py @@ -24,9 +24,8 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from m5.params import * - from m5.objects.ClockedObject import ClockedObject +from m5.params import * class BasicRouter(ClockedObject): diff --git a/src/mem/ruby/network/Network.py b/src/mem/ruby/network/Network.py index 3e9f549f89..72934efa30 100644 --- a/src/mem/ruby/network/Network.py +++ b/src/mem/ruby/network/Network.py @@ -24,10 +24,10 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +from m5.objects.BasicLink import BasicLink +from m5.objects.ClockedObject import ClockedObject from m5.params import * from m5.proxy import * -from m5.objects.ClockedObject import ClockedObject -from m5.objects.BasicLink import BasicLink class RubyNetwork(ClockedObject): diff --git a/src/mem/ruby/network/garnet/GarnetLink.py b/src/mem/ruby/network/garnet/GarnetLink.py index 3cc44e4614..5cd9abe71f 100644 --- a/src/mem/ruby/network/garnet/GarnetLink.py +++ b/src/mem/ruby/network/garnet/GarnetLink.py @@ -25,10 +25,13 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +from m5.objects.BasicLink import ( + BasicExtLink, + BasicIntLink, +) +from m5.objects.ClockedObject import ClockedObject from m5.params import * from m5.proxy import * -from m5.objects.ClockedObject import ClockedObject -from m5.objects.BasicLink import BasicIntLink, BasicExtLink class CDCType(Enum): diff --git a/src/mem/ruby/network/garnet/GarnetNetwork.py b/src/mem/ruby/network/garnet/GarnetNetwork.py index bf5a0bad33..b735260b4d 100644 --- a/src/mem/ruby/network/garnet/GarnetNetwork.py +++ b/src/mem/ruby/network/garnet/GarnetNetwork.py @@ -29,11 +29,11 @@ # from m5.citations import add_citation -from m5.params import * -from m5.proxy import * -from m5.objects.Network import RubyNetwork from m5.objects.BasicRouter import BasicRouter from m5.objects.ClockedObject import ClockedObject +from m5.objects.Network import RubyNetwork +from m5.params import * +from m5.proxy import * class GarnetNetwork(RubyNetwork): diff --git a/src/mem/ruby/network/simple/SimpleLink.py b/src/mem/ruby/network/simple/SimpleLink.py index 0d3f20698d..83aa2fbe71 100644 --- a/src/mem/ruby/network/simple/SimpleLink.py +++ b/src/mem/ruby/network/simple/SimpleLink.py @@ -36,12 +36,15 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +from m5.objects.BasicLink import ( + BasicExtLink, + BasicIntLink, +) +from m5.objects.MessageBuffer import MessageBuffer from m5.params import * from m5.proxy import * -from m5.util import fatal from m5.SimObject import SimObject -from m5.objects.BasicLink import BasicIntLink, BasicExtLink -from m5.objects.MessageBuffer import MessageBuffer +from m5.util import fatal class SimpleExtLink(BasicExtLink): diff --git a/src/mem/ruby/network/simple/SimpleNetwork.py b/src/mem/ruby/network/simple/SimpleNetwork.py index aa553deee3..e52333b24d 100644 --- a/src/mem/ruby/network/simple/SimpleNetwork.py +++ b/src/mem/ruby/network/simple/SimpleNetwork.py @@ -36,14 +36,13 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from m5.params import * -from m5.proxy import * - -from m5.util import fatal -from m5.SimObject import SimObject -from m5.objects.Network import RubyNetwork from m5.objects.BasicRouter import BasicRouter from m5.objects.MessageBuffer import MessageBuffer +from m5.objects.Network import RubyNetwork +from m5.params import * +from m5.proxy import * +from m5.SimObject import SimObject +from m5.util import fatal class SimpleNetwork(RubyNetwork): diff --git a/src/mem/ruby/slicc_interface/Controller.py b/src/mem/ruby/slicc_interface/Controller.py index 42447f1cca..ef8a0afbf1 100644 --- a/src/mem/ruby/slicc_interface/Controller.py +++ b/src/mem/ruby/slicc_interface/Controller.py @@ -36,9 +36,9 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +from m5.objects.ClockedObject import ClockedObject from m5.params import * from m5.proxy import * -from m5.objects.ClockedObject import ClockedObject class RubyController(ClockedObject): diff --git a/src/mem/ruby/structures/RubyCache.py b/src/mem/ruby/structures/RubyCache.py index 7446ac3de0..2f457f5c4a 100644 --- a/src/mem/ruby/structures/RubyCache.py +++ b/src/mem/ruby/structures/RubyCache.py @@ -24,9 +24,9 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +from m5.objects.ReplacementPolicies import * from m5.params import * from m5.proxy import * -from m5.objects.ReplacementPolicies import * from m5.SimObject import SimObject diff --git a/src/mem/ruby/structures/RubyPrefetcher.py b/src/mem/ruby/structures/RubyPrefetcher.py index cea6ec9604..d4189ae7d5 100644 --- a/src/mem/ruby/structures/RubyPrefetcher.py +++ b/src/mem/ruby/structures/RubyPrefetcher.py @@ -36,11 +36,10 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from m5.SimObject import SimObject +from m5.objects.System import System from m5.params import * from m5.proxy import * - -from m5.objects.System import System +from m5.SimObject import SimObject class RubyPrefetcher(SimObject): diff --git a/src/mem/ruby/system/GPUCoalescer.py b/src/mem/ruby/system/GPUCoalescer.py index fcf49e38b7..d69314eb54 100644 --- a/src/mem/ruby/system/GPUCoalescer.py +++ b/src/mem/ruby/system/GPUCoalescer.py @@ -27,11 +27,10 @@ # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE # POSSIBILITY OF SUCH DAMAGE. +from m5.objects.Sequencer import * from m5.params import * from m5.proxy import * -from m5.objects.Sequencer import * - class RubyGPUCoalescer(RubyPort): type = "RubyGPUCoalescer" diff --git a/src/mem/ruby/system/RubySystem.py b/src/mem/ruby/system/RubySystem.py index 64e39bda4c..5dbcde90ec 100644 --- a/src/mem/ruby/system/RubySystem.py +++ b/src/mem/ruby/system/RubySystem.py @@ -24,10 +24,10 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from m5.params import * -from m5.proxy import * from m5.objects.ClockedObject import ClockedObject from m5.objects.SimpleMemory import * +from m5.params import * +from m5.proxy import * class RubySystem(ClockedObject): diff --git a/src/mem/ruby/system/Sequencer.py b/src/mem/ruby/system/Sequencer.py index eb1003692f..3f570fb952 100644 --- a/src/mem/ruby/system/Sequencer.py +++ b/src/mem/ruby/system/Sequencer.py @@ -37,9 +37,9 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +from m5.objects.ClockedObject import ClockedObject from m5.params import * from m5.proxy import * -from m5.objects.ClockedObject import ClockedObject class RubyPort(ClockedObject): diff --git a/src/mem/ruby/system/VIPERCoalescer.py b/src/mem/ruby/system/VIPERCoalescer.py index af43cddb2c..d2411f858c 100644 --- a/src/mem/ruby/system/VIPERCoalescer.py +++ b/src/mem/ruby/system/VIPERCoalescer.py @@ -27,9 +27,9 @@ # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE # POSSIBILITY OF SUCH DAMAGE. +from m5.objects.GPUCoalescer import * from m5.params import * from m5.proxy import * -from m5.objects.GPUCoalescer import * class VIPERCoalescer(RubyGPUCoalescer): diff --git a/src/mem/slicc/ast/AST.py b/src/mem/slicc/ast/AST.py index ff8e3326ad..52700f9dc9 100644 --- a/src/mem/slicc/ast/AST.py +++ b/src/mem/slicc/ast/AST.py @@ -25,7 +25,10 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from slicc.util import PairContainer, Location +from slicc.util import ( + Location, + PairContainer, +) class AST(PairContainer): diff --git a/src/mem/slicc/ast/ActionDeclAST.py b/src/mem/slicc/ast/ActionDeclAST.py index ff6a4ff9d5..375f4109c1 100644 --- a/src/mem/slicc/ast/ActionDeclAST.py +++ b/src/mem/slicc/ast/ActionDeclAST.py @@ -26,7 +26,11 @@ # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. from slicc.ast.DeclAST import DeclAST -from slicc.symbols import Action, Type, Var +from slicc.symbols import ( + Action, + Type, + Var, +) class ActionDeclAST(DeclAST): diff --git a/src/mem/slicc/ast/EnumDeclAST.py b/src/mem/slicc/ast/EnumDeclAST.py index 19eb1eeddd..f7ff5c3cfd 100644 --- a/src/mem/slicc/ast/EnumDeclAST.py +++ b/src/mem/slicc/ast/EnumDeclAST.py @@ -26,7 +26,10 @@ # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. from slicc.ast.DeclAST import DeclAST -from slicc.symbols import Func, Type +from slicc.symbols import ( + Func, + Type, +) class EnumDeclAST(DeclAST): diff --git a/src/mem/slicc/ast/ExprStatementAST.py b/src/mem/slicc/ast/ExprStatementAST.py index 9545ef3e41..2aa7456816 100644 --- a/src/mem/slicc/ast/ExprStatementAST.py +++ b/src/mem/slicc/ast/ExprStatementAST.py @@ -26,8 +26,8 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from slicc.ast.StatementAST import StatementAST from slicc.ast.LocalVariableAST import LocalVariableAST +from slicc.ast.StatementAST import StatementAST from slicc.symbols import Type diff --git a/src/mem/slicc/ast/FuncCallExprAST.py b/src/mem/slicc/ast/FuncCallExprAST.py index 01b604c8bf..b807a5f933 100644 --- a/src/mem/slicc/ast/FuncCallExprAST.py +++ b/src/mem/slicc/ast/FuncCallExprAST.py @@ -39,7 +39,10 @@ # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. from slicc.ast.ExprAST import ExprAST -from slicc.symbols import Func, Type +from slicc.symbols import ( + Func, + Type, +) class FuncCallExprAST(ExprAST): diff --git a/src/mem/slicc/ast/FuncDeclAST.py b/src/mem/slicc/ast/FuncDeclAST.py index 38898ff9e5..2e28dfd75c 100644 --- a/src/mem/slicc/ast/FuncDeclAST.py +++ b/src/mem/slicc/ast/FuncDeclAST.py @@ -26,7 +26,10 @@ # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. from slicc.ast.DeclAST import DeclAST -from slicc.symbols import Func, Type +from slicc.symbols import ( + Func, + Type, +) class FuncDeclAST(DeclAST): diff --git a/src/mem/slicc/ast/InPortDeclAST.py b/src/mem/slicc/ast/InPortDeclAST.py index 2cbf3bb617..6f1c121075 100644 --- a/src/mem/slicc/ast/InPortDeclAST.py +++ b/src/mem/slicc/ast/InPortDeclAST.py @@ -39,7 +39,11 @@ from slicc.ast.DeclAST import DeclAST from slicc.ast.TypeAST import TypeAST -from slicc.symbols import Func, Type, Var +from slicc.symbols import ( + Func, + Type, + Var, +) class InPortDeclAST(DeclAST): diff --git a/src/mem/slicc/ast/MachineAST.py b/src/mem/slicc/ast/MachineAST.py index 0d9c0ec31b..a6cb8a93ee 100644 --- a/src/mem/slicc/ast/MachineAST.py +++ b/src/mem/slicc/ast/MachineAST.py @@ -26,7 +26,10 @@ # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. from slicc.ast.DeclAST import DeclAST -from slicc.symbols import StateMachine, Type +from slicc.symbols import ( + StateMachine, + Type, +) class MachineAST(DeclAST): diff --git a/src/mem/slicc/ast/OutPortDeclAST.py b/src/mem/slicc/ast/OutPortDeclAST.py index e21a4a6fa7..e6899c8700 100644 --- a/src/mem/slicc/ast/OutPortDeclAST.py +++ b/src/mem/slicc/ast/OutPortDeclAST.py @@ -27,8 +27,10 @@ from slicc.ast.DeclAST import DeclAST from slicc.ast.TypeAST import TypeAST -from slicc.symbols import Var -from slicc.symbols import Type +from slicc.symbols import ( + Type, + Var, +) class OutPortDeclAST(DeclAST): diff --git a/src/mem/slicc/ast/StateDeclAST.py b/src/mem/slicc/ast/StateDeclAST.py index 3ff3ab4e89..1455c50599 100644 --- a/src/mem/slicc/ast/StateDeclAST.py +++ b/src/mem/slicc/ast/StateDeclAST.py @@ -25,7 +25,10 @@ # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. from slicc.ast.DeclAST import DeclAST -from slicc.symbols import Func, Type +from slicc.symbols import ( + Func, + Type, +) class StateDeclAST(DeclAST): diff --git a/src/mem/slicc/ast/TypeAST.py b/src/mem/slicc/ast/TypeAST.py index 92c3190fe2..7da9a21593 100644 --- a/src/mem/slicc/ast/TypeAST.py +++ b/src/mem/slicc/ast/TypeAST.py @@ -26,7 +26,6 @@ # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. from slicc.ast.AST import AST - from slicc.symbols import Type diff --git a/src/mem/slicc/ast/TypeFieldEnumAST.py b/src/mem/slicc/ast/TypeFieldEnumAST.py index 68dd0cd0fa..6a8fe2f191 100644 --- a/src/mem/slicc/ast/TypeFieldEnumAST.py +++ b/src/mem/slicc/ast/TypeFieldEnumAST.py @@ -26,7 +26,11 @@ # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. from slicc.ast.TypeFieldAST import TypeFieldAST -from slicc.symbols import Event, State, RequestType +from slicc.symbols import ( + Event, + RequestType, + State, +) class TypeFieldEnumAST(TypeFieldAST): diff --git a/src/mem/slicc/ast/TypeFieldStateAST.py b/src/mem/slicc/ast/TypeFieldStateAST.py index b04a708f21..4bef5136d4 100644 --- a/src/mem/slicc/ast/TypeFieldStateAST.py +++ b/src/mem/slicc/ast/TypeFieldStateAST.py @@ -25,7 +25,10 @@ # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. from slicc.ast.TypeFieldAST import TypeFieldAST -from slicc.symbols import Event, State +from slicc.symbols import ( + Event, + State, +) class TypeFieldStateAST(TypeFieldAST): diff --git a/src/mem/slicc/ast/VarExprAST.py b/src/mem/slicc/ast/VarExprAST.py index 3c4023e8fe..8431dd132c 100644 --- a/src/mem/slicc/ast/VarExprAST.py +++ b/src/mem/slicc/ast/VarExprAST.py @@ -27,7 +27,10 @@ # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. from slicc.ast.ExprAST import ExprAST -from slicc.symbols import Type, Var +from slicc.symbols import ( + Type, + Var, +) class VarExprAST(ExprAST): diff --git a/src/mem/slicc/ast/__init__.py b/src/mem/slicc/ast/__init__.py index 247546fb8f..86f9b09479 100644 --- a/src/mem/slicc/ast/__init__.py +++ b/src/mem/slicc/ast/__init__.py @@ -36,13 +36,13 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from slicc.ast.AST import * - # actual ASTs from slicc.ast.ActionDeclAST import * from slicc.ast.AssignStatementAST import * +from slicc.ast.AST import * from slicc.ast.CheckAllocateStatementAST import * from slicc.ast.CheckNextCycleAST import * +from slicc.ast.CheckProbeStatementAST import * from slicc.ast.DeclAST import * from slicc.ast.DeclListAST import * from slicc.ast.DeferEnqueueingStatementAST import * @@ -63,8 +63,8 @@ from slicc.ast.MachineAST import * from slicc.ast.MemberExprAST import * from slicc.ast.MethodCallExprAST import * from slicc.ast.NewExprAST import * -from slicc.ast.OodAST import * from slicc.ast.ObjDeclAST import * +from slicc.ast.OodAST import * from slicc.ast.OperatorExprAST import * from slicc.ast.OutPortDeclAST import * from slicc.ast.PairAST import * @@ -72,7 +72,6 @@ from slicc.ast.PairListAST import * from slicc.ast.PeekStatementAST import * from slicc.ast.ReturnStatementAST import * from slicc.ast.StallAndWaitStatementAST import * -from slicc.ast.WakeupPortStatementAST import * from slicc.ast.StateDeclAST import * from slicc.ast.StatementAST import * from slicc.ast.StatementListAST import * @@ -84,4 +83,4 @@ from slicc.ast.TypeFieldAST import * from slicc.ast.TypeFieldEnumAST import * from slicc.ast.TypeFieldStateAST import * from slicc.ast.VarExprAST import * -from slicc.ast.CheckProbeStatementAST import * +from slicc.ast.WakeupPortStatementAST import * diff --git a/src/mem/slicc/parser.py b/src/mem/slicc/parser.py index af47ddb639..dba82d8480 100644 --- a/src/mem/slicc/parser.py +++ b/src/mem/slicc/parser.py @@ -42,7 +42,10 @@ import re import sys from code_formatter import code_formatter -from grammar import Grammar, ParseError +from grammar import ( + Grammar, + ParseError, +) import slicc.ast as ast import slicc.util as util diff --git a/src/mem/slicc/symbols/StateMachine.py b/src/mem/slicc/symbols/StateMachine.py index 68a1a6a8af..078e666d26 100644 --- a/src/mem/slicc/symbols/StateMachine.py +++ b/src/mem/slicc/symbols/StateMachine.py @@ -38,12 +38,12 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +import re from collections import OrderedDict +import slicc.generate.html as html from slicc.symbols.Symbol import Symbol from slicc.symbols.Var import Var -import slicc.generate.html as html -import re python_class_map = { "int": "Int", diff --git a/src/mem/slicc/symbols/Symbol.py b/src/mem/slicc/symbols/Symbol.py index 74863724d2..261aac5720 100644 --- a/src/mem/slicc/symbols/Symbol.py +++ b/src/mem/slicc/symbols/Symbol.py @@ -44,8 +44,8 @@ class Symbol(PairContainer): def __init__(self, symtab, ident, location, pairs=None): super().__init__() - from slicc.util import Location from slicc.symbols import SymbolTable + from slicc.util import Location if not isinstance(symtab, SymbolTable): raise AttributeError diff --git a/src/mem/slicc/symbols/Transition.py b/src/mem/slicc/symbols/Transition.py index 385065f972..67e05c6997 100644 --- a/src/mem/slicc/symbols/Transition.py +++ b/src/mem/slicc/symbols/Transition.py @@ -25,8 +25,8 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from slicc.symbols.Symbol import Symbol from slicc.symbols.State import WildcardState +from slicc.symbols.Symbol import Symbol class Transition(Symbol): diff --git a/src/mem/slicc/symbols/Type.py b/src/mem/slicc/symbols/Type.py index 7010461e0c..535a4165b3 100644 --- a/src/mem/slicc/symbols/Type.py +++ b/src/mem/slicc/symbols/Type.py @@ -39,9 +39,9 @@ from collections import OrderedDict -from slicc.util import PairContainer from slicc.symbols.Symbol import Symbol from slicc.symbols.Var import Var +from slicc.util import PairContainer class DataMember(Var): diff --git a/src/mem/slicc/symbols/__init__.py b/src/mem/slicc/symbols/__init__.py index e4ce4826fa..58e039f988 100644 --- a/src/mem/slicc/symbols/__init__.py +++ b/src/mem/slicc/symbols/__init__.py @@ -27,8 +27,8 @@ from slicc.symbols.Action import Action from slicc.symbols.Event import Event from slicc.symbols.Func import Func -from slicc.symbols.State import State from slicc.symbols.RequestType import RequestType +from slicc.symbols.State import State from slicc.symbols.StateMachine import StateMachine from slicc.symbols.Symbol import Symbol from slicc.symbols.SymbolTable import SymbolTable diff --git a/src/python/gem5/components/boards/abstract_board.py b/src/python/gem5/components/boards/abstract_board.py index aba080e239..7d251e8296 100644 --- a/src/python/gem5/components/boards/abstract_board.py +++ b/src/python/gem5/components/boards/abstract_board.py @@ -24,23 +24,33 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from abc import ABCMeta, abstractmethod import inspect - -from .mem_mode import MemMode, mem_mode_to_string -from ...resources.resource import WorkloadResource +from abc import ( + ABCMeta, + abstractmethod, +) +from typing import ( + List, + Optional, + Sequence, + Tuple, +) from m5.objects import ( AddrRange, - System, - Port, - IOXBar, ClockDomain, + IOXBar, + Port, SrcClockDomain, + System, VoltageDomain, ) -from typing import List, Optional, Sequence, Tuple +from ...resources.resource import WorkloadResource +from .mem_mode import ( + MemMode, + mem_mode_to_string, +) class AbstractBoard: diff --git a/src/python/gem5/components/boards/abstract_system_board.py b/src/python/gem5/components/boards/abstract_system_board.py index 2812b37260..471a9458cd 100644 --- a/src/python/gem5/components/boards/abstract_system_board.py +++ b/src/python/gem5/components/boards/abstract_system_board.py @@ -26,10 +26,13 @@ from abc import ABCMeta -from .abstract_board import AbstractBoard -from ...utils.override import overrides +from m5.objects import ( + SimObject, + System, +) -from m5.objects import System, SimObject +from ...utils.override import overrides +from .abstract_board import AbstractBoard class AbstractSystemBoard(System, AbstractBoard): diff --git a/src/python/gem5/components/boards/arm_board.py b/src/python/gem5/components/boards/arm_board.py index 032a863fd3..e976d71836 100644 --- a/src/python/gem5/components/boards/arm_board.py +++ b/src/python/gem5/components/boards/arm_board.py @@ -24,43 +24,48 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from m5.objects import ( - Port, - IOXBar, - Bridge, - BadAddr, - Terminal, - PciVirtIO, - VncServer, - AddrRange, - ArmSystem, - ArmRelease, - ArmFsLinux, - VirtIOBlock, - CowDiskImage, - RawDiskImage, - VoltageDomain, - SrcClockDomain, - ArmDefaultRelease, - VExpress_GEM5_Base, - VExpress_GEM5_Foundation, - SimObject, +import os +from abc import ABCMeta +from typing import ( + List, + Sequence, + Tuple, ) -import os import m5 -from abc import ABCMeta +from m5.objects import ( + AddrRange, + ArmDefaultRelease, + ArmFsLinux, + ArmRelease, + ArmSystem, + BadAddr, + Bridge, + CowDiskImage, + IOXBar, + PciVirtIO, + Port, + RawDiskImage, + SimObject, + SrcClockDomain, + Terminal, + VExpress_GEM5_Base, + VExpress_GEM5_Foundation, + VirtIOBlock, + VncServer, + VoltageDomain, +) + from ...isas import ISA -from ...utils.requires import requires -from ...utils.override import overrides -from typing import List, Sequence, Tuple -from .abstract_board import AbstractBoard from ...resources.resource import AbstractResource -from .kernel_disk_workload import KernelDiskWorkload -from ..cachehierarchies.classic.no_cache import NoCache -from ..processors.abstract_processor import AbstractProcessor -from ..memory.abstract_memory_system import AbstractMemorySystem +from ...utils.override import overrides +from ...utils.requires import requires from ..cachehierarchies.abstract_cache_hierarchy import AbstractCacheHierarchy +from ..cachehierarchies.classic.no_cache import NoCache +from ..memory.abstract_memory_system import AbstractMemorySystem +from ..processors.abstract_processor import AbstractProcessor +from .abstract_board import AbstractBoard +from .kernel_disk_workload import KernelDiskWorkload class ArmBoard(ArmSystem, AbstractBoard, KernelDiskWorkload): diff --git a/src/python/gem5/components/boards/experimental/lupv_board.py b/src/python/gem5/components/boards/experimental/lupv_board.py index 85843b89e2..a27d57e902 100644 --- a/src/python/gem5/components/boards/experimental/lupv_board.py +++ b/src/python/gem5/components/boards/experimental/lupv_board.py @@ -27,42 +27,31 @@ import os from typing import List -from ....utils.override import overrides -from ..abstract_system_board import AbstractSystemBoard -from ...processors.abstract_processor import AbstractProcessor -from ...memory.abstract_memory_system import AbstractMemorySystem -from ...cachehierarchies.abstract_cache_hierarchy import AbstractCacheHierarchy -from ..kernel_disk_workload import KernelDiskWorkload -from ....resources.resource import AbstractResource -from ....isas import ISA - import m5 from m5.objects import ( - Bridge, - PMAChecker, - RiscvLinux, - RiscvRTC, AddrRange, - IOXBar, + Bridge, Clint, - Plic, - Terminal, + CowDiskImage, + Frequency, + IOXBar, LupioBLK, LupioIPI, LupioPIC, LupioRNG, LupioRTC, + LupioSYS, LupioTMR, LupioTTY, - LupioSYS, LupV, - AddrRange, - CowDiskImage, - RawDiskImage, - Frequency, + Plic, + PMAChecker, Port, + RawDiskImage, + RiscvLinux, + RiscvRTC, + Terminal, ) - from m5.util.fdthelper import ( Fdt, FdtNode, @@ -72,6 +61,15 @@ from m5.util.fdthelper import ( FdtState, ) +from ....isas import ISA +from ....resources.resource import AbstractResource +from ....utils.override import overrides +from ...cachehierarchies.abstract_cache_hierarchy import AbstractCacheHierarchy +from ...memory.abstract_memory_system import AbstractMemorySystem +from ...processors.abstract_processor import AbstractProcessor +from ..abstract_system_board import AbstractSystemBoard +from ..kernel_disk_workload import KernelDiskWorkload + class LupvBoard(AbstractSystemBoard, KernelDiskWorkload): """ diff --git a/src/python/gem5/components/boards/kernel_disk_workload.py b/src/python/gem5/components/boards/kernel_disk_workload.py index 72b143e6ff..16c196208b 100644 --- a/src/python/gem5/components/boards/kernel_disk_workload.py +++ b/src/python/gem5/components/boards/kernel_disk_workload.py @@ -24,22 +24,25 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +import os from abc import abstractmethod - -from .abstract_board import AbstractBoard -from ...resources.resource import ( - DiskImageResource, - BootloaderResource, - CheckpointResource, - KernelResource, +from pathlib import Path +from typing import ( + List, + Optional, + Union, ) -from typing import List, Optional, Union -import os -from pathlib import Path - import m5 +from ...resources.resource import ( + BootloaderResource, + CheckpointResource, + DiskImageResource, + KernelResource, +) +from .abstract_board import AbstractBoard + class KernelDiskWorkload: """ diff --git a/src/python/gem5/components/boards/riscv_board.py b/src/python/gem5/components/boards/riscv_board.py index 5e5af815a4..0ce9d0192b 100644 --- a/src/python/gem5/components/boards/riscv_board.py +++ b/src/python/gem5/components/boards/riscv_board.py @@ -26,41 +26,28 @@ # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. import os - from typing import List -from ...utils.override import overrides -from .abstract_system_board import AbstractSystemBoard -from .kernel_disk_workload import KernelDiskWorkload -from ..processors.abstract_processor import AbstractProcessor -from ..memory.abstract_memory_system import AbstractMemorySystem -from ..cachehierarchies.abstract_cache_hierarchy import AbstractCacheHierarchy -from ...resources.resource import AbstractResource - -from ...isas import ISA - import m5 - from m5.objects import ( + AddrRange, BadAddr, Bridge, - PMAChecker, - RiscvLinux, - AddrRange, - IOXBar, - RiscvRTC, - HiFive, - GenericRiscvPciHost, - IGbE_e1000, CowDiskImage, + Frequency, + GenericRiscvPciHost, + HiFive, + IGbE_e1000, + IOXBar, + PMAChecker, + Port, RawDiskImage, + RiscvLinux, RiscvMmioVirtIO, + RiscvRTC, VirtIOBlock, VirtIORng, - Frequency, - Port, ) - from m5.util.fdthelper import ( Fdt, FdtNode, @@ -70,6 +57,15 @@ from m5.util.fdthelper import ( FdtState, ) +from ...isas import ISA +from ...resources.resource import AbstractResource +from ...utils.override import overrides +from ..cachehierarchies.abstract_cache_hierarchy import AbstractCacheHierarchy +from ..memory.abstract_memory_system import AbstractMemorySystem +from ..processors.abstract_processor import AbstractProcessor +from .abstract_system_board import AbstractSystemBoard +from .kernel_disk_workload import KernelDiskWorkload + class RiscvBoard(AbstractSystemBoard, KernelDiskWorkload): """ diff --git a/src/python/gem5/components/boards/se_binary_workload.py b/src/python/gem5/components/boards/se_binary_workload.py index cba268b2df..0c13ffedd1 100644 --- a/src/python/gem5/components/boards/se_binary_workload.py +++ b/src/python/gem5/components/boards/se_binary_workload.py @@ -24,27 +24,32 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from .abstract_board import AbstractBoard - -from ...resources.resource import ( - FileResource, - AbstractResource, - BinaryResource, - CheckpointResource, - SimpointResource, - SimpointDirectoryResource, +from pathlib import Path +from typing import ( + List, + Optional, + Union, ) -from ..processors.switchable_processor import SwitchableProcessor +from m5.objects import ( + Process, + SEWorkload, +) +from m5.util import warn from gem5.resources.elfie import ELFieInfo from gem5.resources.looppoint import Looppoint -from m5.objects import SEWorkload, Process - -from typing import Optional, List, Union -from m5.util import warn -from pathlib import Path +from ...resources.resource import ( + AbstractResource, + BinaryResource, + CheckpointResource, + FileResource, + SimpointDirectoryResource, + SimpointResource, +) +from ..processors.switchable_processor import SwitchableProcessor +from .abstract_board import AbstractBoard class SEBinaryWorkload: diff --git a/src/python/gem5/components/boards/simple_board.py b/src/python/gem5/components/boards/simple_board.py index 2e4122e061..1891dfd345 100644 --- a/src/python/gem5/components/boards/simple_board.py +++ b/src/python/gem5/components/boards/simple_board.py @@ -24,16 +24,20 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from m5.objects import AddrRange, IOXBar, Port +from typing import List +from m5.objects import ( + AddrRange, + IOXBar, + Port, +) + +from ...utils.override import overrides +from ..cachehierarchies.abstract_cache_hierarchy import AbstractCacheHierarchy +from ..memory.abstract_memory_system import AbstractMemorySystem +from ..processors.abstract_processor import AbstractProcessor from .abstract_system_board import AbstractSystemBoard from .se_binary_workload import SEBinaryWorkload -from ..processors.abstract_processor import AbstractProcessor -from ..memory.abstract_memory_system import AbstractMemorySystem -from ..cachehierarchies.abstract_cache_hierarchy import AbstractCacheHierarchy -from ...utils.override import overrides - -from typing import List class SimpleBoard(AbstractSystemBoard, SEBinaryWorkload): diff --git a/src/python/gem5/components/boards/test_board.py b/src/python/gem5/components/boards/test_board.py index dea5adab56..0c0407f888 100644 --- a/src/python/gem5/components/boards/test_board.py +++ b/src/python/gem5/components/boards/test_board.py @@ -24,17 +24,23 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from m5.objects import Port, IOXBar, AddrRange +from typing import ( + List, + Optional, +) + +from m5.objects import ( + AddrRange, + IOXBar, + Port, +) from ...utils.override import overrides +from ..cachehierarchies.abstract_cache_hierarchy import AbstractCacheHierarchy +from ..memory.abstract_memory_system import AbstractMemorySystem +from ..processors.abstract_generator import AbstractGenerator from .abstract_board import AbstractBoard from .abstract_system_board import AbstractSystemBoard -from ..processors.abstract_generator import AbstractGenerator -from ..memory.abstract_memory_system import AbstractMemorySystem -from ..cachehierarchies.abstract_cache_hierarchy import AbstractCacheHierarchy - - -from typing import List, Optional class TestBoard(AbstractSystemBoard): diff --git a/src/python/gem5/components/boards/x86_board.py b/src/python/gem5/components/boards/x86_board.py index e7e65ecf71..764688da60 100644 --- a/src/python/gem5/components/boards/x86_board.py +++ b/src/python/gem5/components/boards/x86_board.py @@ -25,40 +25,41 @@ # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from .kernel_disk_workload import KernelDiskWorkload -from ...resources.resource import AbstractResource -from ...utils.override import overrides -from .abstract_system_board import AbstractSystemBoard -from ...isas import ISA - -from m5.objects import ( - Pc, - AddrRange, - X86FsLinux, - Addr, - X86SMBiosBiosInformation, - X86IntelMPProcessor, - X86IntelMPIOAPIC, - X86IntelMPBus, - X86IntelMPBusHierarchy, - X86IntelMPIOIntAssignment, - X86E820Entry, - Bridge, - IOXBar, - IdeDisk, - CowDiskImage, - RawDiskImage, - BaseXBar, - Port, +from typing import ( + List, + Sequence, ) +from m5.objects import ( + Addr, + AddrRange, + BaseXBar, + Bridge, + CowDiskImage, + IdeDisk, + IOXBar, + Pc, + Port, + RawDiskImage, + X86E820Entry, + X86FsLinux, + X86IntelMPBus, + X86IntelMPBusHierarchy, + X86IntelMPIOAPIC, + X86IntelMPIOIntAssignment, + X86IntelMPProcessor, + X86SMBiosBiosInformation, +) from m5.util.convert import toMemorySize -from ..processors.abstract_processor import AbstractProcessor -from ..memory.abstract_memory_system import AbstractMemorySystem +from ...isas import ISA +from ...resources.resource import AbstractResource +from ...utils.override import overrides from ..cachehierarchies.abstract_cache_hierarchy import AbstractCacheHierarchy - -from typing import List, Sequence +from ..memory.abstract_memory_system import AbstractMemorySystem +from ..processors.abstract_processor import AbstractProcessor +from .abstract_system_board import AbstractSystemBoard +from .kernel_disk_workload import KernelDiskWorkload class X86Board(AbstractSystemBoard, KernelDiskWorkload): diff --git a/src/python/gem5/components/cachehierarchies/abstract_cache_hierarchy.py b/src/python/gem5/components/cachehierarchies/abstract_cache_hierarchy.py index 8d59a383f1..d8722a1df7 100644 --- a/src/python/gem5/components/cachehierarchies/abstract_cache_hierarchy.py +++ b/src/python/gem5/components/cachehierarchies/abstract_cache_hierarchy.py @@ -24,12 +24,15 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from abc import ABCMeta, abstractmethod - -from ..boards.abstract_board import AbstractBoard +from abc import ( + ABCMeta, + abstractmethod, +) from m5.objects import SubSystem +from ..boards.abstract_board import AbstractBoard + class AbstractCacheHierarchy(SubSystem): __metaclass__ = ABCMeta diff --git a/src/python/gem5/components/cachehierarchies/chi/nodes/abstract_node.py b/src/python/gem5/components/cachehierarchies/chi/nodes/abstract_node.py index ed8c3e0d5a..beb0d467d1 100644 --- a/src/python/gem5/components/cachehierarchies/chi/nodes/abstract_node.py +++ b/src/python/gem5/components/cachehierarchies/chi/nodes/abstract_node.py @@ -24,14 +24,18 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from abc import abstractmethod -from gem5.isas import ISA -from gem5.components.processors.cpu_types import CPUTypes -from gem5.components.processors.abstract_core import AbstractCore - -from m5.objects import Cache_Controller, MessageBuffer, RubyNetwork - import math +from abc import abstractmethod + +from m5.objects import ( + Cache_Controller, + MessageBuffer, + RubyNetwork, +) + +from gem5.components.processors.abstract_core import AbstractCore +from gem5.components.processors.cpu_types import CPUTypes +from gem5.isas import ISA class TriggerMessageBuffer(MessageBuffer): diff --git a/src/python/gem5/components/cachehierarchies/chi/nodes/directory.py b/src/python/gem5/components/cachehierarchies/chi/nodes/directory.py index b93112a620..7d7a16cd5f 100644 --- a/src/python/gem5/components/cachehierarchies/chi/nodes/directory.py +++ b/src/python/gem5/components/cachehierarchies/chi/nodes/directory.py @@ -24,9 +24,14 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from .abstract_node import AbstractNode +from m5.objects import ( + NULL, + ClockDomain, + RubyCache, + RubyNetwork, +) -from m5.objects import ClockDomain, NULL, RubyCache, RubyNetwork +from .abstract_node import AbstractNode class SimpleDirectory(AbstractNode): diff --git a/src/python/gem5/components/cachehierarchies/chi/nodes/dma_requestor.py b/src/python/gem5/components/cachehierarchies/chi/nodes/dma_requestor.py index f6b63e0649..2997c33ce7 100644 --- a/src/python/gem5/components/cachehierarchies/chi/nodes/dma_requestor.py +++ b/src/python/gem5/components/cachehierarchies/chi/nodes/dma_requestor.py @@ -24,13 +24,16 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +from m5.objects import ( + ClockDomain, + RubyCache, +) + from gem5.components.processors.abstract_core import AbstractCore from gem5.isas import ISA from .abstract_node import AbstractNode -from m5.objects import ClockDomain, RubyCache - class DMARequestor(AbstractNode): def __init__(self, network, cache_line_size, clk_domain: ClockDomain): diff --git a/src/python/gem5/components/cachehierarchies/chi/nodes/private_l1_moesi_cache.py b/src/python/gem5/components/cachehierarchies/chi/nodes/private_l1_moesi_cache.py index 2f618491ca..477c0f9b63 100644 --- a/src/python/gem5/components/cachehierarchies/chi/nodes/private_l1_moesi_cache.py +++ b/src/python/gem5/components/cachehierarchies/chi/nodes/private_l1_moesi_cache.py @@ -24,13 +24,17 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +from m5.objects import ( + ClockDomain, + RubyCache, + RubyNetwork, +) + from gem5.components.processors.abstract_core import AbstractCore from gem5.isas import ISA from .abstract_node import AbstractNode -from m5.objects import ClockDomain, RubyCache, RubyNetwork - class PrivateL1MOESICache(AbstractNode): def __init__( diff --git a/src/python/gem5/components/cachehierarchies/chi/private_l1_cache_hierarchy.py b/src/python/gem5/components/cachehierarchies/chi/private_l1_cache_hierarchy.py index 7be9239331..92b240da26 100644 --- a/src/python/gem5/components/cachehierarchies/chi/private_l1_cache_hierarchy.py +++ b/src/python/gem5/components/cachehierarchies/chi/private_l1_cache_hierarchy.py @@ -27,30 +27,34 @@ from itertools import chain from typing import List -from m5.objects.SubSystem import SubSystem -from gem5.components.cachehierarchies.ruby.abstract_ruby_cache_hierarchy import ( - AbstractRubyCacheHierarchy, +from m5.objects import ( + NULL, + RubyPortProxy, + RubySequencer, + RubySystem, ) +from m5.objects.SubSystem import SubSystem + +from gem5.coherence_protocol import CoherenceProtocol +from gem5.components.boards.abstract_board import AbstractBoard from gem5.components.cachehierarchies.abstract_cache_hierarchy import ( AbstractCacheHierarchy, ) -from gem5.coherence_protocol import CoherenceProtocol -from gem5.isas import ISA -from gem5.utils.requires import requires -from gem5.utils.override import overrides -from gem5.components.boards.abstract_board import AbstractBoard -from gem5.components.processors.abstract_core import AbstractCore - +from gem5.components.cachehierarchies.ruby.abstract_ruby_cache_hierarchy import ( + AbstractRubyCacheHierarchy, +) from gem5.components.cachehierarchies.ruby.topologies.simple_pt2pt import ( SimplePt2Pt, ) +from gem5.components.processors.abstract_core import AbstractCore +from gem5.isas import ISA +from gem5.utils.override import overrides +from gem5.utils.requires import requires -from .nodes.private_l1_moesi_cache import PrivateL1MOESICache -from .nodes.dma_requestor import DMARequestor from .nodes.directory import SimpleDirectory +from .nodes.dma_requestor import DMARequestor from .nodes.memory_controller import MemoryController - -from m5.objects import NULL, RubySystem, RubySequencer, RubyPortProxy +from .nodes.private_l1_moesi_cache import PrivateL1MOESICache class PrivateL1CacheHierarchy(AbstractRubyCacheHierarchy): diff --git a/src/python/gem5/components/cachehierarchies/classic/abstract_classic_cache_hierarchy.py b/src/python/gem5/components/cachehierarchies/classic/abstract_classic_cache_hierarchy.py index 3423c9ca9a..7531b2a3f1 100644 --- a/src/python/gem5/components/cachehierarchies/classic/abstract_classic_cache_hierarchy.py +++ b/src/python/gem5/components/cachehierarchies/classic/abstract_classic_cache_hierarchy.py @@ -25,11 +25,12 @@ # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. from abc import abstractmethod -from ....utils.override import overrides -from ..abstract_cache_hierarchy import AbstractCacheHierarchy from m5.objects import Port +from ....utils.override import overrides +from ..abstract_cache_hierarchy import AbstractCacheHierarchy + class AbstractClassicCacheHierarchy(AbstractCacheHierarchy): """ diff --git a/src/python/gem5/components/cachehierarchies/classic/caches/l1dcache.py b/src/python/gem5/components/cachehierarchies/classic/caches/l1dcache.py index da4a4ead9b..6165870129 100644 --- a/src/python/gem5/components/cachehierarchies/classic/caches/l1dcache.py +++ b/src/python/gem5/components/cachehierarchies/classic/caches/l1dcache.py @@ -24,12 +24,16 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from .....utils.override import * - -from m5.objects import Cache, BasePrefetcher, StridePrefetcher - from typing import Type +from m5.objects import ( + BasePrefetcher, + Cache, + StridePrefetcher, +) + +from .....utils.override import * + class L1DCache(Cache): """ diff --git a/src/python/gem5/components/cachehierarchies/classic/caches/l1icache.py b/src/python/gem5/components/cachehierarchies/classic/caches/l1icache.py index f1ac89cf1d..d5130b2b28 100644 --- a/src/python/gem5/components/cachehierarchies/classic/caches/l1icache.py +++ b/src/python/gem5/components/cachehierarchies/classic/caches/l1icache.py @@ -26,7 +26,11 @@ from typing import Type -from m5.objects import Cache, BasePrefetcher, StridePrefetcher +from m5.objects import ( + BasePrefetcher, + Cache, + StridePrefetcher, +) from .....utils.override import * diff --git a/src/python/gem5/components/cachehierarchies/classic/caches/l2cache.py b/src/python/gem5/components/cachehierarchies/classic/caches/l2cache.py index 86b69855b6..aa796f4ceb 100644 --- a/src/python/gem5/components/cachehierarchies/classic/caches/l2cache.py +++ b/src/python/gem5/components/cachehierarchies/classic/caches/l2cache.py @@ -24,12 +24,17 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from .....utils.override import * - -from m5.objects import Cache, Clusivity, BasePrefetcher, StridePrefetcher - from typing import Type +from m5.objects import ( + BasePrefetcher, + Cache, + Clusivity, + StridePrefetcher, +) + +from .....utils.override import * + class L2Cache(Cache): """ diff --git a/src/python/gem5/components/cachehierarchies/classic/caches/mmu_cache.py b/src/python/gem5/components/cachehierarchies/classic/caches/mmu_cache.py index a6eb43cfb4..2da494aa6c 100644 --- a/src/python/gem5/components/cachehierarchies/classic/caches/mmu_cache.py +++ b/src/python/gem5/components/cachehierarchies/classic/caches/mmu_cache.py @@ -24,9 +24,13 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from .....utils.override import * +from m5.objects import ( + BasePrefetcher, + Cache, + StridePrefetcher, +) -from m5.objects import Cache, BasePrefetcher, StridePrefetcher +from .....utils.override import * class MMUCache(Cache): diff --git a/src/python/gem5/components/cachehierarchies/classic/no_cache.py b/src/python/gem5/components/cachehierarchies/classic/no_cache.py index b7af6ed02f..b43e6f69cb 100644 --- a/src/python/gem5/components/cachehierarchies/classic/no_cache.py +++ b/src/python/gem5/components/cachehierarchies/classic/no_cache.py @@ -24,14 +24,19 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from .abstract_classic_cache_hierarchy import AbstractClassicCacheHierarchy -from ..abstract_cache_hierarchy import AbstractCacheHierarchy -from ...boards.abstract_board import AbstractBoard +from m5.objects import ( + BadAddr, + BaseXBar, + Bridge, + Port, + SystemXBar, +) + from ....isas import ISA - -from m5.objects import Bridge, BaseXBar, SystemXBar, BadAddr, Port - from ....utils.override import * +from ...boards.abstract_board import AbstractBoard +from ..abstract_cache_hierarchy import AbstractCacheHierarchy +from .abstract_classic_cache_hierarchy import AbstractClassicCacheHierarchy class NoCache(AbstractClassicCacheHierarchy): diff --git a/src/python/gem5/components/cachehierarchies/classic/private_l1_cache_hierarchy.py b/src/python/gem5/components/cachehierarchies/classic/private_l1_cache_hierarchy.py index 9a40c39550..b5be4905df 100644 --- a/src/python/gem5/components/cachehierarchies/classic/private_l1_cache_hierarchy.py +++ b/src/python/gem5/components/cachehierarchies/classic/private_l1_cache_hierarchy.py @@ -24,17 +24,22 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +from m5.objects import ( + BadAddr, + BaseXBar, + Cache, + Port, + SystemXBar, +) + +from ....isas import ISA +from ....utils.override import * +from ...boards.abstract_board import AbstractBoard from ..abstract_cache_hierarchy import AbstractCacheHierarchy from .abstract_classic_cache_hierarchy import AbstractClassicCacheHierarchy from .caches.l1dcache import L1DCache from .caches.l1icache import L1ICache from .caches.mmu_cache import MMUCache -from ...boards.abstract_board import AbstractBoard -from ....isas import ISA - -from m5.objects import Cache, BaseXBar, SystemXBar, BadAddr, Port - -from ....utils.override import * class PrivateL1CacheHierarchy(AbstractClassicCacheHierarchy): diff --git a/src/python/gem5/components/cachehierarchies/classic/private_l1_private_l2_cache_hierarchy.py b/src/python/gem5/components/cachehierarchies/classic/private_l1_private_l2_cache_hierarchy.py index b27ced916c..748f7e1f5c 100644 --- a/src/python/gem5/components/cachehierarchies/classic/private_l1_private_l2_cache_hierarchy.py +++ b/src/python/gem5/components/cachehierarchies/classic/private_l1_private_l2_cache_hierarchy.py @@ -24,18 +24,25 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +from m5.objects import ( + BadAddr, + BaseXBar, + Cache, + L2XBar, + Port, + SystemXBar, +) + +from ....isas import ISA +from ....utils.override import * +from ...boards.abstract_board import AbstractBoard from ..abstract_cache_hierarchy import AbstractCacheHierarchy -from .abstract_classic_cache_hierarchy import AbstractClassicCacheHierarchy from ..abstract_two_level_cache_hierarchy import AbstractTwoLevelCacheHierarchy +from .abstract_classic_cache_hierarchy import AbstractClassicCacheHierarchy from .caches.l1dcache import L1DCache from .caches.l1icache import L1ICache from .caches.l2cache import L2Cache from .caches.mmu_cache import MMUCache -from ...boards.abstract_board import AbstractBoard -from ....isas import ISA -from m5.objects import Cache, L2XBar, BaseXBar, SystemXBar, BadAddr, Port - -from ....utils.override import * class PrivateL1PrivateL2CacheHierarchy( diff --git a/src/python/gem5/components/cachehierarchies/classic/private_l1_shared_l2_cache_hierarchy.py b/src/python/gem5/components/cachehierarchies/classic/private_l1_shared_l2_cache_hierarchy.py index be2dfbe79c..68671738c8 100644 --- a/src/python/gem5/components/cachehierarchies/classic/private_l1_shared_l2_cache_hierarchy.py +++ b/src/python/gem5/components/cachehierarchies/classic/private_l1_shared_l2_cache_hierarchy.py @@ -24,18 +24,25 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +from m5.objects import ( + BadAddr, + BaseXBar, + Cache, + L2XBar, + Port, + SystemXBar, +) + +from ....isas import ISA +from ....utils.override import * +from ...boards.abstract_board import AbstractBoard from ..abstract_cache_hierarchy import AbstractCacheHierarchy -from .abstract_classic_cache_hierarchy import AbstractClassicCacheHierarchy from ..abstract_two_level_cache_hierarchy import AbstractTwoLevelCacheHierarchy +from .abstract_classic_cache_hierarchy import AbstractClassicCacheHierarchy from .caches.l1dcache import L1DCache from .caches.l1icache import L1ICache from .caches.l2cache import L2Cache from .caches.mmu_cache import MMUCache -from ...boards.abstract_board import AbstractBoard -from ....isas import ISA -from m5.objects import Cache, L2XBar, BaseXBar, SystemXBar, BadAddr, Port - -from ....utils.override import * class PrivateL1SharedL2CacheHierarchy( diff --git a/src/python/gem5/components/cachehierarchies/ruby/caches/abstract_l1_cache.py b/src/python/gem5/components/cachehierarchies/ruby/caches/abstract_l1_cache.py index 237cd606df..a9944c4d03 100644 --- a/src/python/gem5/components/cachehierarchies/ruby/caches/abstract_l1_cache.py +++ b/src/python/gem5/components/cachehierarchies/ruby/caches/abstract_l1_cache.py @@ -24,14 +24,14 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +import math from abc import abstractmethod -from .....isas import ISA -from ....processors.cpu_types import CPUTypes -from ....processors.abstract_core import AbstractCore from m5.objects import L1Cache_Controller -import math +from .....isas import ISA +from ....processors.abstract_core import AbstractCore +from ....processors.cpu_types import CPUTypes class AbstractL1Cache(L1Cache_Controller): diff --git a/src/python/gem5/components/cachehierarchies/ruby/caches/mesi_three_level/directory.py b/src/python/gem5/components/cachehierarchies/ruby/caches/mesi_three_level/directory.py index 58676daaf0..4840e3b264 100644 --- a/src/python/gem5/components/cachehierarchies/ruby/caches/mesi_three_level/directory.py +++ b/src/python/gem5/components/cachehierarchies/ruby/caches/mesi_three_level/directory.py @@ -24,11 +24,14 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +from m5.objects import ( + MessageBuffer, + RubyDirectoryMemory, +) + from ......utils.override import overrides from ..abstract_directory import AbstractDirectory -from m5.objects import MessageBuffer, RubyDirectoryMemory - class Directory(AbstractDirectory): def __init__(self, network, cache_line_size, mem_range, port): diff --git a/src/python/gem5/components/cachehierarchies/ruby/caches/mesi_three_level/dma_controller.py b/src/python/gem5/components/cachehierarchies/ruby/caches/mesi_three_level/dma_controller.py index f731869f54..145757c15a 100644 --- a/src/python/gem5/components/cachehierarchies/ruby/caches/mesi_three_level/dma_controller.py +++ b/src/python/gem5/components/cachehierarchies/ruby/caches/mesi_three_level/dma_controller.py @@ -24,9 +24,12 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from ......utils.override import overrides +from m5.objects import ( + DMA_Controller, + MessageBuffer, +) -from m5.objects import MessageBuffer, DMA_Controller +from ......utils.override import overrides class DMAController(DMA_Controller): diff --git a/src/python/gem5/components/cachehierarchies/ruby/caches/mesi_three_level/l1_cache.py b/src/python/gem5/components/cachehierarchies/ruby/caches/mesi_three_level/l1_cache.py index 0d7f436193..6d203f978a 100644 --- a/src/python/gem5/components/cachehierarchies/ruby/caches/mesi_three_level/l1_cache.py +++ b/src/python/gem5/components/cachehierarchies/ruby/caches/mesi_three_level/l1_cache.py @@ -24,20 +24,20 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from .....processors.abstract_core import AbstractCore -from ......isas import ISA -from ......utils.override import * +import math from m5.objects import ( - MessageBuffer, - RubyPrefetcher, - RubyCache, - ClockDomain, LRURP, + ClockDomain, L0Cache_Controller, + MessageBuffer, + RubyCache, + RubyPrefetcher, ) -import math +from ......isas import ISA +from ......utils.override import * +from .....processors.abstract_core import AbstractCore # L0Cache_Controller is the ruby backend's terminology corresponding to diff --git a/src/python/gem5/components/cachehierarchies/ruby/caches/mesi_three_level/l2_cache.py b/src/python/gem5/components/cachehierarchies/ruby/caches/mesi_three_level/l2_cache.py index 280c2e4110..ff2b8e3dd9 100644 --- a/src/python/gem5/components/cachehierarchies/ruby/caches/mesi_three_level/l2_cache.py +++ b/src/python/gem5/components/cachehierarchies/ruby/caches/mesi_three_level/l2_cache.py @@ -24,19 +24,19 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from .....processors.abstract_core import AbstractCore -from ......isas import ISA -from ......utils.override import * +import math from m5.objects import ( - MessageBuffer, - RubyPrefetcher, - RubyCache, ClockDomain, L1Cache_Controller, + MessageBuffer, + RubyCache, + RubyPrefetcher, ) -import math +from ......isas import ISA +from ......utils.override import * +from .....processors.abstract_core import AbstractCore # L1Cache_Controller is ruby backend's terminology corresponding to diff --git a/src/python/gem5/components/cachehierarchies/ruby/caches/mesi_three_level/l3_cache.py b/src/python/gem5/components/cachehierarchies/ruby/caches/mesi_three_level/l3_cache.py index 4b05166752..8509a35cfc 100644 --- a/src/python/gem5/components/cachehierarchies/ruby/caches/mesi_three_level/l3_cache.py +++ b/src/python/gem5/components/cachehierarchies/ruby/caches/mesi_three_level/l3_cache.py @@ -24,10 +24,14 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from m5.objects import MessageBuffer, RubyCache, L2Cache_Controller - import math +from m5.objects import ( + L2Cache_Controller, + MessageBuffer, + RubyCache, +) + # L2Cache_Controller is ruby backend's terminology corresponding to # L3 cache in stdlib. diff --git a/src/python/gem5/components/cachehierarchies/ruby/caches/mesi_two_level/directory.py b/src/python/gem5/components/cachehierarchies/ruby/caches/mesi_two_level/directory.py index 58676daaf0..4840e3b264 100644 --- a/src/python/gem5/components/cachehierarchies/ruby/caches/mesi_two_level/directory.py +++ b/src/python/gem5/components/cachehierarchies/ruby/caches/mesi_two_level/directory.py @@ -24,11 +24,14 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +from m5.objects import ( + MessageBuffer, + RubyDirectoryMemory, +) + from ......utils.override import overrides from ..abstract_directory import AbstractDirectory -from m5.objects import MessageBuffer, RubyDirectoryMemory - class Directory(AbstractDirectory): def __init__(self, network, cache_line_size, mem_range, port): diff --git a/src/python/gem5/components/cachehierarchies/ruby/caches/mesi_two_level/dma_controller.py b/src/python/gem5/components/cachehierarchies/ruby/caches/mesi_two_level/dma_controller.py index ab76d4cb5e..aa7a5ad778 100644 --- a/src/python/gem5/components/cachehierarchies/ruby/caches/mesi_two_level/dma_controller.py +++ b/src/python/gem5/components/cachehierarchies/ruby/caches/mesi_two_level/dma_controller.py @@ -24,11 +24,11 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +from m5.objects import MessageBuffer + from ......utils.override import overrides from ..abstract_dma_controller import AbstractDMAController -from m5.objects import MessageBuffer - class DMAController(AbstractDMAController): def __init__(self, network, cache_line_size): diff --git a/src/python/gem5/components/cachehierarchies/ruby/caches/mesi_two_level/l1_cache.py b/src/python/gem5/components/cachehierarchies/ruby/caches/mesi_two_level/l1_cache.py index 0e0e333da9..7787644c9b 100644 --- a/src/python/gem5/components/cachehierarchies/ruby/caches/mesi_two_level/l1_cache.py +++ b/src/python/gem5/components/cachehierarchies/ruby/caches/mesi_two_level/l1_cache.py @@ -24,15 +24,20 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from .....processors.abstract_core import AbstractCore -from ......isas import ISA -from ..abstract_l1_cache import AbstractL1Cache -from ......utils.override import * - -from m5.objects import MessageBuffer, RubyPrefetcher, RubyCache, ClockDomain - import math +from m5.objects import ( + ClockDomain, + MessageBuffer, + RubyCache, + RubyPrefetcher, +) + +from ......isas import ISA +from ......utils.override import * +from .....processors.abstract_core import AbstractCore +from ..abstract_l1_cache import AbstractL1Cache + class L1Cache(AbstractL1Cache): def __init__( diff --git a/src/python/gem5/components/cachehierarchies/ruby/caches/mesi_two_level/l2_cache.py b/src/python/gem5/components/cachehierarchies/ruby/caches/mesi_two_level/l2_cache.py index 81ef4dbe90..4f7c923c54 100644 --- a/src/python/gem5/components/cachehierarchies/ruby/caches/mesi_two_level/l2_cache.py +++ b/src/python/gem5/components/cachehierarchies/ruby/caches/mesi_two_level/l2_cache.py @@ -24,13 +24,16 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from ..abstract_l2_cache import AbstractL2Cache -from ......utils.override import * - -from m5.objects import MessageBuffer, RubyCache - import math +from m5.objects import ( + MessageBuffer, + RubyCache, +) + +from ......utils.override import * +from ..abstract_l2_cache import AbstractL2Cache + class L2Cache(AbstractL2Cache): def __init__( diff --git a/src/python/gem5/components/cachehierarchies/ruby/caches/mi_example/directory.py b/src/python/gem5/components/cachehierarchies/ruby/caches/mi_example/directory.py index 0e7cddf6fe..3d1ae54104 100644 --- a/src/python/gem5/components/cachehierarchies/ruby/caches/mi_example/directory.py +++ b/src/python/gem5/components/cachehierarchies/ruby/caches/mi_example/directory.py @@ -24,11 +24,13 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from ..abstract_directory import AbstractDirectory +from m5.objects import ( + MessageBuffer, + RubyDirectoryMemory, +) + from ......utils.override import overrides - - -from m5.objects import MessageBuffer, RubyDirectoryMemory +from ..abstract_directory import AbstractDirectory class Directory(AbstractDirectory): diff --git a/src/python/gem5/components/cachehierarchies/ruby/caches/mi_example/dma_controller.py b/src/python/gem5/components/cachehierarchies/ruby/caches/mi_example/dma_controller.py index fb6895f4f8..b9c1f4a60f 100644 --- a/src/python/gem5/components/cachehierarchies/ruby/caches/mi_example/dma_controller.py +++ b/src/python/gem5/components/cachehierarchies/ruby/caches/mi_example/dma_controller.py @@ -24,11 +24,11 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from ..abstract_dma_controller import AbstractDMAController -from ......utils.override import overrides - from m5.objects import MessageBuffer +from ......utils.override import overrides +from ..abstract_dma_controller import AbstractDMAController + class DMAController(AbstractDMAController): """ diff --git a/src/python/gem5/components/cachehierarchies/ruby/caches/mi_example/l1_cache.py b/src/python/gem5/components/cachehierarchies/ruby/caches/mi_example/l1_cache.py index 1368b92bfc..2feae222d8 100644 --- a/src/python/gem5/components/cachehierarchies/ruby/caches/mi_example/l1_cache.py +++ b/src/python/gem5/components/cachehierarchies/ruby/caches/mi_example/l1_cache.py @@ -24,13 +24,17 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +from m5.objects import ( + ClockDomain, + MessageBuffer, + RubyCache, +) + +from ......isas import ISA from ......utils.override import overrides from .....processors.abstract_core import AbstractCore -from ......isas import ISA from ..abstract_l1_cache import AbstractL1Cache -from m5.objects import MessageBuffer, RubyCache, ClockDomain - class L1Cache(AbstractL1Cache): def __init__( diff --git a/src/python/gem5/components/cachehierarchies/ruby/caches/prebuilt/octopi_cache/core_complex.py b/src/python/gem5/components/cachehierarchies/ruby/caches/prebuilt/octopi_cache/core_complex.py index f056d76f98..9aa0dc4a36 100644 --- a/src/python/gem5/components/cachehierarchies/ruby/caches/prebuilt/octopi_cache/core_complex.py +++ b/src/python/gem5/components/cachehierarchies/ruby/caches/prebuilt/octopi_cache/core_complex.py @@ -24,11 +24,17 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from typing import List, Tuple +from typing import ( + List, + Tuple, +) + +from m5.objects import ( + RubySequencer, + SubSystem, +) -from gem5.isas import ISA from gem5.components.boards.abstract_board import AbstractBoard -from gem5.components.processors.abstract_core import AbstractCore from gem5.components.cachehierarchies.ruby.caches.mesi_three_level.l1_cache import ( L1Cache, ) @@ -38,14 +44,14 @@ from gem5.components.cachehierarchies.ruby.caches.mesi_three_level.l2_cache impo from gem5.components.cachehierarchies.ruby.caches.mesi_three_level.l3_cache import ( L3Cache, ) - -from m5.objects import SubSystem, RubySequencer +from gem5.components.processors.abstract_core import AbstractCore +from gem5.isas import ISA from .ruby_network_components import ( - RubyRouter, RubyExtLink, RubyIntLink, RubyNetworkComponent, + RubyRouter, ) diff --git a/src/python/gem5/components/cachehierarchies/ruby/caches/prebuilt/octopi_cache/octopi.py b/src/python/gem5/components/cachehierarchies/ruby/caches/prebuilt/octopi_cache/octopi.py index 09ee69e011..f7d4d63de1 100644 --- a/src/python/gem5/components/cachehierarchies/ruby/caches/prebuilt/octopi_cache/octopi.py +++ b/src/python/gem5/components/cachehierarchies/ruby/caches/prebuilt/octopi_cache/octopi.py @@ -24,26 +24,32 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from ...abstract_ruby_cache_hierarchy import AbstractRubyCacheHierarchy -from ....abstract_three_level_cache_hierarchy import ( - AbstractThreeLevelCacheHierarchy, +from m5.objects import ( + DMASequencer, + RubyPortProxy, + RubySystem, ) + from ......coherence_protocol import CoherenceProtocol from ......components.boards.abstract_board import AbstractBoard -from ......utils.requires import requires - from ......components.cachehierarchies.ruby.caches.mesi_three_level.directory import ( Directory, ) from ......components.cachehierarchies.ruby.caches.mesi_three_level.dma_controller import ( DMAController, ) - -from m5.objects import RubySystem, DMASequencer, RubyPortProxy - +from ......utils.requires import requires +from ....abstract_three_level_cache_hierarchy import ( + AbstractThreeLevelCacheHierarchy, +) +from ...abstract_ruby_cache_hierarchy import AbstractRubyCacheHierarchy from .core_complex import CoreComplex from .octopi_network import OctopiNetwork -from .ruby_network_components import RubyRouter, RubyExtLink, RubyIntLink +from .ruby_network_components import ( + RubyExtLink, + RubyIntLink, + RubyRouter, +) # CoreComplex sub-systems own the L1, L2, L3 controllers diff --git a/src/python/gem5/components/cachehierarchies/ruby/caches/prebuilt/octopi_cache/octopi_network.py b/src/python/gem5/components/cachehierarchies/ruby/caches/prebuilt/octopi_cache/octopi_network.py index 8e5befabf7..c175a24778 100644 --- a/src/python/gem5/components/cachehierarchies/ruby/caches/prebuilt/octopi_cache/octopi_network.py +++ b/src/python/gem5/components/cachehierarchies/ruby/caches/prebuilt/octopi_cache/octopi_network.py @@ -27,9 +27,9 @@ from m5.objects import SimpleNetwork from .ruby_network_components import ( + RubyIntLink, RubyNetworkComponent, RubyRouter, - RubyIntLink, ) diff --git a/src/python/gem5/components/cachehierarchies/ruby/caches/prebuilt/octopi_cache/ruby_network_components.py b/src/python/gem5/components/cachehierarchies/ruby/caches/prebuilt/octopi_cache/ruby_network_components.py index 8a413ea59d..70cfe4242d 100644 --- a/src/python/gem5/components/cachehierarchies/ruby/caches/prebuilt/octopi_cache/ruby_network_components.py +++ b/src/python/gem5/components/cachehierarchies/ruby/caches/prebuilt/octopi_cache/ruby_network_components.py @@ -24,7 +24,11 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from m5.objects import Switch, SimpleIntLink, SimpleExtLink +from m5.objects import ( + SimpleExtLink, + SimpleIntLink, + Switch, +) class RubyNetworkComponent: diff --git a/src/python/gem5/components/cachehierarchies/ruby/mesi_three_level_cache_hierarchy.py b/src/python/gem5/components/cachehierarchies/ruby/mesi_three_level_cache_hierarchy.py index 2a8ce30cda..039ba8fb7a 100644 --- a/src/python/gem5/components/cachehierarchies/ruby/mesi_three_level_cache_hierarchy.py +++ b/src/python/gem5/components/cachehierarchies/ruby/mesi_three_level_cache_hierarchy.py @@ -25,23 +25,27 @@ # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from .abstract_ruby_cache_hierarchy import AbstractRubyCacheHierarchy +from m5.objects import ( + DMASequencer, + RubyPortProxy, + RubySequencer, + RubySystem, +) + +from ....coherence_protocol import CoherenceProtocol +from ....isas import ISA +from ....utils.requires import requires +from ...boards.abstract_board import AbstractBoard from ..abstract_three_level_cache_hierarchy import ( AbstractThreeLevelCacheHierarchy, ) -from ....coherence_protocol import CoherenceProtocol -from ....isas import ISA -from ...boards.abstract_board import AbstractBoard -from ....utils.requires import requires - -from .topologies.simple_pt2pt import SimplePt2Pt +from .abstract_ruby_cache_hierarchy import AbstractRubyCacheHierarchy +from .caches.mesi_three_level.directory import Directory +from .caches.mesi_three_level.dma_controller import DMAController from .caches.mesi_three_level.l1_cache import L1Cache from .caches.mesi_three_level.l2_cache import L2Cache from .caches.mesi_three_level.l3_cache import L3Cache -from .caches.mesi_three_level.directory import Directory -from .caches.mesi_three_level.dma_controller import DMAController - -from m5.objects import RubySystem, RubySequencer, DMASequencer, RubyPortProxy +from .topologies.simple_pt2pt import SimplePt2Pt class MESIThreeLevelCacheHierarchy( diff --git a/src/python/gem5/components/cachehierarchies/ruby/mesi_two_level_cache_hierarchy.py b/src/python/gem5/components/cachehierarchies/ruby/mesi_two_level_cache_hierarchy.py index 8c7bba4ed4..083e4d43fe 100644 --- a/src/python/gem5/components/cachehierarchies/ruby/mesi_two_level_cache_hierarchy.py +++ b/src/python/gem5/components/cachehierarchies/ruby/mesi_two_level_cache_hierarchy.py @@ -25,20 +25,24 @@ # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from .abstract_ruby_cache_hierarchy import AbstractRubyCacheHierarchy -from ..abstract_two_level_cache_hierarchy import AbstractTwoLevelCacheHierarchy +from m5.objects import ( + DMASequencer, + RubyPortProxy, + RubySequencer, + RubySystem, +) + from ....coherence_protocol import CoherenceProtocol from ....isas import ISA -from ...boards.abstract_board import AbstractBoard from ....utils.requires import requires - -from .topologies.simple_pt2pt import SimplePt2Pt -from .caches.mesi_two_level.l1_cache import L1Cache -from .caches.mesi_two_level.l2_cache import L2Cache +from ...boards.abstract_board import AbstractBoard +from ..abstract_two_level_cache_hierarchy import AbstractTwoLevelCacheHierarchy +from .abstract_ruby_cache_hierarchy import AbstractRubyCacheHierarchy from .caches.mesi_two_level.directory import Directory from .caches.mesi_two_level.dma_controller import DMAController - -from m5.objects import RubySystem, RubySequencer, DMASequencer, RubyPortProxy +from .caches.mesi_two_level.l1_cache import L1Cache +from .caches.mesi_two_level.l2_cache import L2Cache +from .topologies.simple_pt2pt import SimplePt2Pt class MESITwoLevelCacheHierarchy( diff --git a/src/python/gem5/components/cachehierarchies/ruby/mi_example_cache_hierarchy.py b/src/python/gem5/components/cachehierarchies/ruby/mi_example_cache_hierarchy.py index 93b19591cc..328fb0f998 100644 --- a/src/python/gem5/components/cachehierarchies/ruby/mi_example_cache_hierarchy.py +++ b/src/python/gem5/components/cachehierarchies/ruby/mi_example_cache_hierarchy.py @@ -24,20 +24,24 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from .caches.mi_example.l1_cache import L1Cache -from .caches.mi_example.dma_controller import DMAController -from .caches.mi_example.directory import Directory -from .topologies.simple_pt2pt import SimplePt2Pt -from .abstract_ruby_cache_hierarchy import AbstractRubyCacheHierarchy -from ..abstract_cache_hierarchy import AbstractCacheHierarchy -from ...boards.abstract_board import AbstractBoard +from m5.objects import ( + DMASequencer, + RubyPortProxy, + RubySequencer, + RubySystem, +) + from ....coherence_protocol import CoherenceProtocol from ....isas import ISA from ....utils.override import overrides from ....utils.requires import requires - - -from m5.objects import RubySystem, RubySequencer, DMASequencer, RubyPortProxy +from ...boards.abstract_board import AbstractBoard +from ..abstract_cache_hierarchy import AbstractCacheHierarchy +from .abstract_ruby_cache_hierarchy import AbstractRubyCacheHierarchy +from .caches.mi_example.directory import Directory +from .caches.mi_example.dma_controller import DMAController +from .caches.mi_example.l1_cache import L1Cache +from .topologies.simple_pt2pt import SimplePt2Pt class MIExampleCacheHierarchy(AbstractRubyCacheHierarchy): diff --git a/src/python/gem5/components/cachehierarchies/ruby/topologies/simple_pt2pt.py b/src/python/gem5/components/cachehierarchies/ruby/topologies/simple_pt2pt.py index 649f027d72..65c3ad51c2 100644 --- a/src/python/gem5/components/cachehierarchies/ruby/topologies/simple_pt2pt.py +++ b/src/python/gem5/components/cachehierarchies/ruby/topologies/simple_pt2pt.py @@ -24,7 +24,12 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from m5.objects import SimpleNetwork, Switch, SimpleExtLink, SimpleIntLink +from m5.objects import ( + SimpleExtLink, + SimpleIntLink, + SimpleNetwork, + Switch, +) class SimplePt2Pt(SimpleNetwork): diff --git a/src/python/gem5/components/memory/__init__.py b/src/python/gem5/components/memory/__init__.py index 546d5d98ed..49a8cb8173 100644 --- a/src/python/gem5/components/memory/__init__.py +++ b/src/python/gem5/components/memory/__init__.py @@ -24,26 +24,32 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from .single_channel import SingleChannelDDR3_1600 -from .single_channel import SingleChannelDDR3_2133 -from .single_channel import SingleChannelDDR4_2400 -from .single_channel import SingleChannelHBM -from .single_channel import SingleChannelLPDDR3_1600 -from .single_channel import DIMM_DDR5_4400 -from .single_channel import DIMM_DDR5_6400 -from .single_channel import DIMM_DDR5_8400 -from .multi_channel import DualChannelDDR3_1600 -from .multi_channel import DualChannelDDR3_2133 -from .multi_channel import DualChannelDDR4_2400 -from .multi_channel import DualChannelLPDDR3_1600 from .hbm import HBM2Stack +from .multi_channel import ( + DualChannelDDR3_1600, + DualChannelDDR3_2133, + DualChannelDDR4_2400, + DualChannelLPDDR3_1600, +) +from .single_channel import ( + DIMM_DDR5_4400, + DIMM_DDR5_6400, + DIMM_DDR5_8400, + SingleChannelDDR3_1600, + SingleChannelDDR3_2133, + SingleChannelDDR4_2400, + SingleChannelHBM, + SingleChannelLPDDR3_1600, +) try: - from .dramsys import DRAMSysMem - from .dramsys import DRAMSysDDR4_1866 - from .dramsys import DRAMSysDDR3_1600 - from .dramsys import DRAMSysLPDDR4_3200 - from .dramsys import DRAMSysHBM2 + from .dramsys import ( + DRAMSysDDR3_1600, + DRAMSysDDR4_1866, + DRAMSysHBM2, + DRAMSysLPDDR4_3200, + DRAMSysMem, + ) except: # In the case that DRAMSys is not compiled into the gem5 binary, importing # DRAMSys components will fail. This try-exception statement is needed to diff --git a/src/python/gem5/components/memory/abstract_memory_system.py b/src/python/gem5/components/memory/abstract_memory_system.py index cfbf6ac01c..e985cf1d9b 100644 --- a/src/python/gem5/components/memory/abstract_memory_system.py +++ b/src/python/gem5/components/memory/abstract_memory_system.py @@ -24,14 +24,25 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from abc import ABCMeta, abstractmethod -from typing import Tuple, Sequence, List +from abc import ( + ABCMeta, + abstractmethod, +) +from typing import ( + List, + Sequence, + Tuple, +) +from m5.objects import ( + AddrRange, + MemCtrl, + Port, + SubSystem, +) from ..boards.abstract_board import AbstractBoard -from m5.objects import AddrRange, Port, SubSystem, MemCtrl - class AbstractMemorySystem(SubSystem): __metaclass__ = ABCMeta diff --git a/src/python/gem5/components/memory/dramsim_3.py b/src/python/gem5/components/memory/dramsim_3.py index f154ba354f..fd99df9dbd 100644 --- a/src/python/gem5/components/memory/dramsim_3.py +++ b/src/python/gem5/components/memory/dramsim_3.py @@ -1,8 +1,19 @@ -import m5 -import os import configparser +import os +from typing import ( + List, + Optional, + Sequence, + Tuple, +) -from m5.objects import DRAMsim3, AddrRange, Port, MemCtrl +import m5 +from m5.objects import ( + AddrRange, + DRAMsim3, + MemCtrl, + Port, +) from m5.util.convert import toMemorySize from ...utils.override import overrides @@ -10,9 +21,6 @@ from ..boards.abstract_board import AbstractBoard from .abstract_memory_system import AbstractMemorySystem -from typing import Optional, Tuple, Sequence, List - - def config_ds3(mem_type: str, num_chnls: int) -> Tuple[str, str]: """ This function creates a config file that will be used to create a memory diff --git a/src/python/gem5/components/memory/dramsys.py b/src/python/gem5/components/memory/dramsys.py index a09d2fa0fc..25e1c84b5a 100644 --- a/src/python/gem5/components/memory/dramsys.py +++ b/src/python/gem5/components/memory/dramsys.py @@ -24,15 +24,20 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from typing import Tuple, Sequence, List, Optional from pathlib import Path +from typing import ( + List, + Optional, + Sequence, + Tuple, +) from m5.objects import ( - DRAMSys, AddrRange, - Port, - MemCtrl, + DRAMSys, Gem5ToTlmBridge32, + MemCtrl, + Port, SystemC_Kernel, ) from m5.util.convert import toMemorySize @@ -41,7 +46,6 @@ from ...utils.override import overrides from ..boards.abstract_board import AbstractBoard from .abstract_memory_system import AbstractMemorySystem - DEFAULT_DRAMSYS_DIRECTORY = Path("ext/dramsys/DRAMSys") diff --git a/src/python/gem5/components/memory/hbm.py b/src/python/gem5/components/memory/hbm.py index 3f0716c14b..7d59caa478 100644 --- a/src/python/gem5/components/memory/hbm.py +++ b/src/python/gem5/components/memory/hbm.py @@ -27,14 +27,29 @@ """ HBM2 memory system using HBMCtrl """ -from .memory import ChanneledMemory -from .abstract_memory_system import AbstractMemorySystem from math import log +from typing import ( + Optional, + Sequence, + Tuple, + Type, + Union, +) + +from m5.objects import ( + AddrRange, + DRAMInterface, + HBMCtrl, + Port, +) + from ...utils.override import overrides -from m5.objects import AddrRange, DRAMInterface, HBMCtrl, Port -from typing import Type, Optional, Union, Sequence, Tuple -from .memory import _try_convert +from .abstract_memory_system import AbstractMemorySystem from .dram_interfaces.hbm import HBM_2000_4H_1x64 +from .memory import ( + ChanneledMemory, + _try_convert, +) class HighBandwidthMemory(ChanneledMemory): diff --git a/src/python/gem5/components/memory/memory.py b/src/python/gem5/components/memory/memory.py index e7e6cf46e3..6742da2c3f 100644 --- a/src/python/gem5/components/memory/memory.py +++ b/src/python/gem5/components/memory/memory.py @@ -28,12 +28,26 @@ """ from math import log -from ...utils.override import overrides +from typing import ( + List, + Optional, + Sequence, + Tuple, + Type, + Union, +) + +from m5.objects import ( + AddrRange, + DRAMInterface, + MemCtrl, + Port, +) from m5.util.convert import toMemorySize + +from ...utils.override import overrides from ..boards.abstract_board import AbstractBoard from .abstract_memory_system import AbstractMemorySystem -from m5.objects import AddrRange, DRAMInterface, MemCtrl, Port -from typing import Type, Sequence, Tuple, List, Optional, Union def _try_convert(val, cls): diff --git a/src/python/gem5/components/memory/multi_channel.py b/src/python/gem5/components/memory/multi_channel.py index 1f14190c97..59d06fba1f 100644 --- a/src/python/gem5/components/memory/multi_channel.py +++ b/src/python/gem5/components/memory/multi_channel.py @@ -24,14 +24,17 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from .memory import ChanneledMemory -from .abstract_memory_system import AbstractMemorySystem - from typing import Optional -from .dram_interfaces.ddr3 import DDR3_1600_8x8, DDR3_2133_8x8 + +from .abstract_memory_system import AbstractMemorySystem +from .dram_interfaces.ddr3 import ( + DDR3_1600_8x8, + DDR3_2133_8x8, +) from .dram_interfaces.ddr4 import DDR4_2400_8x8 -from .dram_interfaces.lpddr3 import LPDDR3_1600_1x32 from .dram_interfaces.hbm import HBM_1000_4H_1x64 +from .dram_interfaces.lpddr3 import LPDDR3_1600_1x32 +from .memory import ChanneledMemory def DualChannelDDR3_1600( diff --git a/src/python/gem5/components/memory/simple.py b/src/python/gem5/components/memory/simple.py index b650a68ba4..a849641135 100644 --- a/src/python/gem5/components/memory/simple.py +++ b/src/python/gem5/components/memory/simple.py @@ -27,12 +27,23 @@ """Simple memory controllers """ -from ...utils.override import overrides +from typing import ( + List, + Sequence, + Tuple, +) + +from m5.objects import ( + AddrRange, + MemCtrl, + Port, + SimpleMemory, +) from m5.util.convert import toMemorySize -from typing import List, Sequence, Tuple + +from ...utils.override import overrides from ..boards.abstract_board import AbstractBoard from .abstract_memory_system import AbstractMemorySystem -from m5.objects import AddrRange, MemCtrl, Port, SimpleMemory class SingleChannelSimpleMemory(AbstractMemorySystem): diff --git a/src/python/gem5/components/memory/single_channel.py b/src/python/gem5/components/memory/single_channel.py index 9235bbd52d..0efb2979a5 100644 --- a/src/python/gem5/components/memory/single_channel.py +++ b/src/python/gem5/components/memory/single_channel.py @@ -24,16 +24,22 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from .memory import ChanneledMemory -from .abstract_memory_system import AbstractMemorySystem - from typing import Optional -from .dram_interfaces.ddr5 import DDR5_4400_4x8, DDR5_6400_4x8, DDR5_8400_4x8 +from .abstract_memory_system import AbstractMemorySystem +from .dram_interfaces.ddr3 import ( + DDR3_1600_8x8, + DDR3_2133_8x8, +) from .dram_interfaces.ddr4 import DDR4_2400_8x8 +from .dram_interfaces.ddr5 import ( + DDR5_4400_4x8, + DDR5_6400_4x8, + DDR5_8400_4x8, +) from .dram_interfaces.hbm import HBM_1000_4H_1x128 from .dram_interfaces.lpddr3 import LPDDR3_1600_1x32 -from .dram_interfaces.ddr3 import DDR3_1600_8x8, DDR3_2133_8x8 +from .memory import ChanneledMemory def SingleChannelDDR3_1600( diff --git a/src/python/gem5/components/processors/abstract_core.py b/src/python/gem5/components/processors/abstract_core.py index 8259df8a8b..dcde782ce1 100644 --- a/src/python/gem5/components/processors/abstract_core.py +++ b/src/python/gem5/components/processors/abstract_core.py @@ -24,14 +24,25 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from abc import ABCMeta, abstractmethod -from typing import Optional, List +from abc import ( + ABCMeta, + abstractmethod, +) +from typing import ( + List, + Optional, +) + +from m5.objects import ( + BaseMMU, + PcCountTrackerManager, + Port, + SubSystem, +) +from m5.params import PcCountPair from ...isas import ISA -from m5.objects import BaseMMU, Port, SubSystem, PcCountTrackerManager -from m5.params import PcCountPair - class AbstractCore(SubSystem): __metaclass__ = ABCMeta diff --git a/src/python/gem5/components/processors/abstract_generator.py b/src/python/gem5/components/processors/abstract_generator.py index 30e8f17970..0f9acc48ac 100644 --- a/src/python/gem5/components/processors/abstract_generator.py +++ b/src/python/gem5/components/processors/abstract_generator.py @@ -25,14 +25,13 @@ # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. from abc import abstractmethod +from typing import List + from ...utils.override import overrides +from ..boards.abstract_board import AbstractBoard from ..boards.mem_mode import MemMode from .abstract_generator_core import AbstractGeneratorCore - from .abstract_processor import AbstractProcessor -from ..boards.abstract_board import AbstractBoard - -from typing import List def partition_range( diff --git a/src/python/gem5/components/processors/abstract_generator_core.py b/src/python/gem5/components/processors/abstract_generator_core.py index b49e86ee19..ff4285b810 100644 --- a/src/python/gem5/components/processors/abstract_generator_core.py +++ b/src/python/gem5/components/processors/abstract_generator_core.py @@ -26,14 +26,17 @@ from abc import abstractmethod -from m5.objects import Port, PortTerminator -from ...utils.override import overrides - -from .abstract_core import AbstractCore -from ...isas import ISA - from typing import Optional +from m5.objects import ( + Port, + PortTerminator, +) + +from ...isas import ISA +from ...utils.override import overrides +from .abstract_core import AbstractCore + class AbstractGeneratorCore(AbstractCore): """The abstract generator core diff --git a/src/python/gem5/components/processors/abstract_processor.py b/src/python/gem5/components/processors/abstract_processor.py index 8978513562..b34da25906 100644 --- a/src/python/gem5/components/processors/abstract_processor.py +++ b/src/python/gem5/components/processors/abstract_processor.py @@ -24,17 +24,21 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from abc import ABCMeta, abstractmethod - -from ...utils.requires import requires -from .abstract_core import AbstractCore +from abc import ( + ABCMeta, + abstractmethod, +) +from typing import ( + List, + Optional, +) from m5.objects import SubSystem -from ..boards.abstract_board import AbstractBoard from ...isas import ISA - -from typing import List, Optional +from ...utils.requires import requires +from ..boards.abstract_board import AbstractBoard +from .abstract_core import AbstractCore class AbstractProcessor(SubSystem): diff --git a/src/python/gem5/components/processors/base_cpu_core.py b/src/python/gem5/components/processors/base_cpu_core.py index 58d06024bc..710a91f1b8 100644 --- a/src/python/gem5/components/processors/base_cpu_core.py +++ b/src/python/gem5/components/processors/base_cpu_core.py @@ -24,24 +24,26 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from typing import Optional, List -from ...utils.requires import requires -from .abstract_core import AbstractCore +from typing import ( + List, + Optional, +) + +from m5.objects import ( + BaseCPU, + BaseMMU, + PcCountTracker, + PcCountTrackerManager, + Port, + Process, +) +from m5.params import PcCountPair from ...isas import ISA from ...runtime import get_runtime_isa from ...utils.override import overrides from ...utils.requires import requires - -from m5.objects import ( - BaseMMU, - Port, - BaseCPU, - Process, - PcCountTracker, - PcCountTrackerManager, -) -from m5.params import PcCountPair +from .abstract_core import AbstractCore class BaseCPUCore(AbstractCore): diff --git a/src/python/gem5/components/processors/base_cpu_processor.py b/src/python/gem5/components/processors/base_cpu_processor.py index d097682d26..23e37cd262 100644 --- a/src/python/gem5/components/processors/base_cpu_processor.py +++ b/src/python/gem5/components/processors/base_cpu_processor.py @@ -25,23 +25,22 @@ # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from .base_cpu_core import BaseCPUCore -from ..boards.mem_mode import MemMode -from ...utils.override import overrides -from ..boards.mem_mode import MemMode -from .abstract_processor import AbstractProcessor -from ..boards.abstract_board import AbstractBoard - from typing import List -from m5.util import warn from m5.objects import ( - BaseO3CPU, - BaseMinorCPU, BaseAtomicSimpleCPU, + BaseMinorCPU, BaseNonCachingSimpleCPU, + BaseO3CPU, BaseTimingSimpleCPU, ) +from m5.util import warn + +from ...utils.override import overrides +from ..boards.abstract_board import AbstractBoard +from ..boards.mem_mode import MemMode +from .abstract_processor import AbstractProcessor +from .base_cpu_core import BaseCPUCore class BaseCPUProcessor(AbstractProcessor): diff --git a/src/python/gem5/components/processors/complex_generator.py b/src/python/gem5/components/processors/complex_generator.py index 81b94f0c14..9d4c1b33b7 100644 --- a/src/python/gem5/components/processors/complex_generator.py +++ b/src/python/gem5/components/processors/complex_generator.py @@ -24,12 +24,18 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from ...utils.override import overrides -from .complex_generator_core import ComplexGeneratorCore -from .abstract_generator import AbstractGenerator -from .abstract_generator import partition_range +from typing import ( + Any, + Iterator, + List, +) -from typing import Iterator, List, Any +from ...utils.override import overrides +from .abstract_generator import ( + AbstractGenerator, + partition_range, +) +from .complex_generator_core import ComplexGeneratorCore class ComplexGenerator(AbstractGenerator): diff --git a/src/python/gem5/components/processors/complex_generator_core.py b/src/python/gem5/components/processors/complex_generator_core.py index 92f62ded09..058f009df8 100644 --- a/src/python/gem5/components/processors/complex_generator_core.py +++ b/src/python/gem5/components/processors/complex_generator_core.py @@ -24,17 +24,25 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from typing import Iterator, Any -from m5.ticks import fromSeconds -from m5.util.convert import toLatency, toMemoryBandwidth -from m5.objects import PyTrafficGen, Port +from enum import Enum +from typing import ( + Any, + Iterator, +) -from .abstract_core import AbstractCore -from .abstract_generator_core import AbstractGeneratorCore +from m5.objects import ( + Port, + PyTrafficGen, +) +from m5.ticks import fromSeconds +from m5.util.convert import ( + toLatency, + toMemoryBandwidth, +) from ...utils.override import overrides - -from enum import Enum +from .abstract_core import AbstractCore +from .abstract_generator_core import AbstractGeneratorCore class TrafficModes(Enum): diff --git a/src/python/gem5/components/processors/cpu_types.py b/src/python/gem5/components/processors/cpu_types.py index d2bf6548ed..aa3f822300 100644 --- a/src/python/gem5/components/processors/cpu_types.py +++ b/src/python/gem5/components/processors/cpu_types.py @@ -24,11 +24,11 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from ..boards.mem_mode import MemMode - +import os from enum import Enum from typing import Set -import os + +from ..boards.mem_mode import MemMode class CPUTypes(Enum): diff --git a/src/python/gem5/components/processors/gups_generator.py b/src/python/gem5/components/processors/gups_generator.py index 76ea9e64b4..beccd339a7 100644 --- a/src/python/gem5/components/processors/gups_generator.py +++ b/src/python/gem5/components/processors/gups_generator.py @@ -28,8 +28,8 @@ from typing import Optional from m5.objects import Addr -from ...utils.override import overrides +from ...utils.override import overrides from .abstract_generator import AbstractGenerator from .gups_generator_core import GUPSGeneratorCore diff --git a/src/python/gem5/components/processors/gups_generator_core.py b/src/python/gem5/components/processors/gups_generator_core.py index 0090c72847..5bb4ec44d2 100644 --- a/src/python/gem5/components/processors/gups_generator_core.py +++ b/src/python/gem5/components/processors/gups_generator_core.py @@ -26,10 +26,18 @@ from typing import Optional + +from m5.objects import ( + Addr, + GUPSGen, + Port, + SrcClockDomain, + VoltageDomain, +) + from ...utils.override import overrides from .abstract_core import AbstractCore from .abstract_generator_core import AbstractGeneratorCore -from m5.objects import Port, GUPSGen, Addr, SrcClockDomain, VoltageDomain class GUPSGeneratorCore(AbstractGeneratorCore): diff --git a/src/python/gem5/components/processors/gups_generator_ep.py b/src/python/gem5/components/processors/gups_generator_ep.py index 68c9dcea04..bd6adde3e5 100644 --- a/src/python/gem5/components/processors/gups_generator_ep.py +++ b/src/python/gem5/components/processors/gups_generator_ep.py @@ -26,9 +26,11 @@ from typing import Optional + from m5.objects import Addr -from ...utils.override import overrides from m5.util.convert import toMemorySize + +from ...utils.override import overrides from .abstract_generator import AbstractGenerator from .gups_generator_core import GUPSGeneratorCore diff --git a/src/python/gem5/components/processors/gups_generator_par.py b/src/python/gem5/components/processors/gups_generator_par.py index 5f6485b9e2..5db0459dbc 100644 --- a/src/python/gem5/components/processors/gups_generator_par.py +++ b/src/python/gem5/components/processors/gups_generator_par.py @@ -26,12 +26,13 @@ from typing import Optional -from m5.objects import Addr -from ...utils.override import overrides +from m5.objects import Addr + +from ...utils.override import overrides +from ..boards.abstract_board import AbstractBoard from ..boards.mem_mode import MemMode from .abstract_generator import AbstractGenerator -from ..boards.abstract_board import AbstractBoard from .gups_generator_core import GUPSGeneratorCore diff --git a/src/python/gem5/components/processors/linear_generator.py b/src/python/gem5/components/processors/linear_generator.py index 32587d40c2..13779a0f6d 100644 --- a/src/python/gem5/components/processors/linear_generator.py +++ b/src/python/gem5/components/processors/linear_generator.py @@ -24,13 +24,15 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from ...utils.override import overrides -from .linear_generator_core import LinearGeneratorCore -from .abstract_generator import AbstractGenerator -from .abstract_generator import partition_range - from typing import List +from ...utils.override import overrides +from .abstract_generator import ( + AbstractGenerator, + partition_range, +) +from .linear_generator_core import LinearGeneratorCore + class LinearGenerator(AbstractGenerator): def __init__( diff --git a/src/python/gem5/components/processors/linear_generator_core.py b/src/python/gem5/components/processors/linear_generator_core.py index b91b44d6aa..11fdde3a15 100644 --- a/src/python/gem5/components/processors/linear_generator_core.py +++ b/src/python/gem5/components/processors/linear_generator_core.py @@ -24,16 +24,22 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from m5.ticks import fromSeconds -from m5.util.convert import toLatency, toMemoryBandwidth -from m5.objects import PyTrafficGen, Port, BaseTrafficGen +from typing import Iterator -from .abstract_core import AbstractCore -from .abstract_generator_core import AbstractGeneratorCore +from m5.objects import ( + BaseTrafficGen, + Port, + PyTrafficGen, +) +from m5.ticks import fromSeconds +from m5.util.convert import ( + toLatency, + toMemoryBandwidth, +) from ...utils.override import overrides - -from typing import Iterator +from .abstract_core import AbstractCore +from .abstract_generator_core import AbstractGeneratorCore class LinearGeneratorCore(AbstractGeneratorCore): diff --git a/src/python/gem5/components/processors/random_generator.py b/src/python/gem5/components/processors/random_generator.py index ca7ed98f89..496aaf8606 100644 --- a/src/python/gem5/components/processors/random_generator.py +++ b/src/python/gem5/components/processors/random_generator.py @@ -24,15 +24,14 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from ...utils.override import overrides -from ..boards.mem_mode import MemMode -from .random_generator_core import RandomGeneratorCore - -from .abstract_generator import AbstractGenerator -from ..boards.abstract_board import AbstractBoard - from typing import List +from ...utils.override import overrides +from ..boards.abstract_board import AbstractBoard +from ..boards.mem_mode import MemMode +from .abstract_generator import AbstractGenerator +from .random_generator_core import RandomGeneratorCore + class RandomGenerator(AbstractGenerator): def __init__( diff --git a/src/python/gem5/components/processors/random_generator_core.py b/src/python/gem5/components/processors/random_generator_core.py index b5aced620d..aa440ce2d7 100644 --- a/src/python/gem5/components/processors/random_generator_core.py +++ b/src/python/gem5/components/processors/random_generator_core.py @@ -24,16 +24,22 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from m5.ticks import fromSeconds -from m5.util.convert import toLatency, toMemoryBandwidth -from m5.objects import PyTrafficGen, Port, BaseTrafficGen +from typing import Iterator -from .abstract_core import AbstractCore -from .abstract_generator_core import AbstractGeneratorCore +from m5.objects import ( + BaseTrafficGen, + Port, + PyTrafficGen, +) +from m5.ticks import fromSeconds +from m5.util.convert import ( + toLatency, + toMemoryBandwidth, +) from ...utils.override import overrides - -from typing import Iterator +from .abstract_core import AbstractCore +from .abstract_generator_core import AbstractGeneratorCore class RandomGeneratorCore(AbstractGeneratorCore): diff --git a/src/python/gem5/components/processors/simple_core.py b/src/python/gem5/components/processors/simple_core.py index 65c0f0ec83..a79cf5c165 100644 --- a/src/python/gem5/components/processors/simple_core.py +++ b/src/python/gem5/components/processors/simple_core.py @@ -24,15 +24,15 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +import importlib +import platform from typing import Optional + +from ...isas import ISA +from ...runtime import get_runtime_isa from ...utils.requires import requires from .base_cpu_core import BaseCPUCore from .cpu_types import CPUTypes -from ...isas import ISA -from ...utils.requires import requires -from ...runtime import get_runtime_isa -import importlib -import platform class SimpleCore(BaseCPUCore): diff --git a/src/python/gem5/components/processors/simple_processor.py b/src/python/gem5/components/processors/simple_processor.py index 510e37df0e..4b569b1f77 100644 --- a/src/python/gem5/components/processors/simple_processor.py +++ b/src/python/gem5/components/processors/simple_processor.py @@ -25,15 +25,15 @@ # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from m5.util import warn -from .base_cpu_processor import BaseCPUProcessor -from ..processors.simple_core import SimpleCore - -from .cpu_types import CPUTypes -from ...isas import ISA - from typing import Optional +from m5.util import warn + +from ...isas import ISA +from ..processors.simple_core import SimpleCore +from .base_cpu_processor import BaseCPUProcessor +from .cpu_types import CPUTypes + class SimpleProcessor(BaseCPUProcessor): """ diff --git a/src/python/gem5/components/processors/simple_switchable_processor.py b/src/python/gem5/components/processors/simple_switchable_processor.py index e3978412c3..62fc83c4fe 100644 --- a/src/python/gem5/components/processors/simple_switchable_processor.py +++ b/src/python/gem5/components/processors/simple_switchable_processor.py @@ -24,17 +24,20 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from ..boards.mem_mode import MemMode -from ..boards.abstract_board import AbstractBoard -from ..processors.simple_core import SimpleCore -from ..processors.cpu_types import CPUTypes, get_mem_mode -from .switchable_processor import SwitchableProcessor -from ...isas import ISA +from typing import Optional + from m5.util import warn +from ...isas import ISA from ...utils.override import * - -from typing import Optional +from ..boards.abstract_board import AbstractBoard +from ..boards.mem_mode import MemMode +from ..processors.cpu_types import ( + CPUTypes, + get_mem_mode, +) +from ..processors.simple_core import SimpleCore +from .switchable_processor import SwitchableProcessor class SimpleSwitchableProcessor(SwitchableProcessor): diff --git a/src/python/gem5/components/processors/switchable_processor.py b/src/python/gem5/components/processors/switchable_processor.py index 88e5f4cc47..e226702999 100644 --- a/src/python/gem5/components/processors/switchable_processor.py +++ b/src/python/gem5/components/processors/switchable_processor.py @@ -25,17 +25,19 @@ # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from .simple_core import SimpleCore -from .abstract_core import AbstractCore -from .cpu_types import CPUTypes +from typing import ( + Dict, + List, +) import m5 -from typing import Dict, List - -from .abstract_processor import AbstractProcessor -from ..boards.abstract_board import AbstractBoard from ...utils.override import * +from ..boards.abstract_board import AbstractBoard +from .abstract_core import AbstractCore +from .abstract_processor import AbstractProcessor +from .cpu_types import CPUTypes +from .simple_core import SimpleCore class SwitchableProcessor(AbstractProcessor): diff --git a/src/python/gem5/components/processors/traffic_generator.py b/src/python/gem5/components/processors/traffic_generator.py index b4c400a64a..c38a053bb0 100644 --- a/src/python/gem5/components/processors/traffic_generator.py +++ b/src/python/gem5/components/processors/traffic_generator.py @@ -24,13 +24,12 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from ...utils.override import overrides -from .traffic_generator_core import TrafficGeneratorCore - -from .abstract_generator import AbstractGenerator - from typing import List +from ...utils.override import overrides +from .abstract_generator import AbstractGenerator +from .traffic_generator_core import TrafficGeneratorCore + class TrafficGenerator(AbstractGenerator): def __init__( diff --git a/src/python/gem5/components/processors/traffic_generator_core.py b/src/python/gem5/components/processors/traffic_generator_core.py index d542352481..0260d9e72a 100644 --- a/src/python/gem5/components/processors/traffic_generator_core.py +++ b/src/python/gem5/components/processors/traffic_generator_core.py @@ -25,11 +25,14 @@ # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from m5.objects import Port, TrafficGen +from m5.objects import ( + Port, + TrafficGen, +) +from ...utils.override import overrides from .abstract_core import AbstractCore from .abstract_generator_core import AbstractGeneratorCore -from ...utils.override import overrides class TrafficGeneratorCore(AbstractGeneratorCore): diff --git a/src/python/gem5/prebuilt/demo/x86_demo_board.py b/src/python/gem5/prebuilt/demo/x86_demo_board.py index eb38bb3e95..084f1eeffe 100644 --- a/src/python/gem5/prebuilt/demo/x86_demo_board.py +++ b/src/python/gem5/prebuilt/demo/x86_demo_board.py @@ -26,14 +26,14 @@ from m5.util import warn -from ...components.processors.cpu_types import CPUTypes +from ...coherence_protocol import CoherenceProtocol from ...components.boards.x86_board import X86Board -from ...components.memory.single_channel import SingleChannelDDR3_1600 -from ...components.processors.simple_processor import SimpleProcessor from ...components.cachehierarchies.ruby.mesi_two_level_cache_hierarchy import ( MESITwoLevelCacheHierarchy, ) -from ...coherence_protocol import CoherenceProtocol +from ...components.memory.single_channel import SingleChannelDDR3_1600 +from ...components.processors.cpu_types import CPUTypes +from ...components.processors.simple_processor import SimpleProcessor from ...isas import ISA from ...utils.requires import requires diff --git a/src/python/gem5/prebuilt/riscvmatched/riscvmatched_board.py b/src/python/gem5/prebuilt/riscvmatched/riscvmatched_board.py index a4e639801d..55efe2dabc 100644 --- a/src/python/gem5/prebuilt/riscvmatched/riscvmatched_board.py +++ b/src/python/gem5/prebuilt/riscvmatched/riscvmatched_board.py @@ -27,42 +27,30 @@ import os import re - -from typing import List, Optional - -from gem5.utils.override import overrides -from gem5.components.boards.abstract_system_board import AbstractSystemBoard -from gem5.components.boards.kernel_disk_workload import KernelDiskWorkload -from gem5.components.boards.se_binary_workload import SEBinaryWorkload -from gem5.resources.resource import AbstractResource -from gem5.components.memory import SingleChannelDDR4_2400 -from gem5.utils.requires import requires -from gem5.isas import ISA -from .riscvmatched_cache import RISCVMatchedCacheHierarchy -from .riscvmatched_processor import U74Processor -from gem5.isas import ISA - -import m5 - -from m5.objects import ( - BadAddr, - Bridge, - PMAChecker, - RiscvLinux, - AddrRange, - IOXBar, - RiscvRTC, - HiFive, - IGbE_e1000, - CowDiskImage, - RawDiskImage, - RiscvMmioVirtIO, - VirtIOBlock, - VirtIORng, - Frequency, - Port, +from typing import ( + List, + Optional, ) +import m5 +from m5.objects import ( + AddrRange, + BadAddr, + Bridge, + CowDiskImage, + Frequency, + HiFive, + IGbE_e1000, + IOXBar, + PMAChecker, + Port, + RawDiskImage, + RiscvLinux, + RiscvMmioVirtIO, + RiscvRTC, + VirtIOBlock, + VirtIORng, +) from m5.util.fdthelper import ( Fdt, FdtNode, @@ -72,6 +60,18 @@ from m5.util.fdthelper import ( FdtState, ) +from gem5.components.boards.abstract_system_board import AbstractSystemBoard +from gem5.components.boards.kernel_disk_workload import KernelDiskWorkload +from gem5.components.boards.se_binary_workload import SEBinaryWorkload +from gem5.components.memory import SingleChannelDDR4_2400 +from gem5.isas import ISA +from gem5.resources.resource import AbstractResource +from gem5.utils.override import overrides +from gem5.utils.requires import requires + +from .riscvmatched_cache import RISCVMatchedCacheHierarchy +from .riscvmatched_processor import U74Processor + def U74Memory(): """ diff --git a/src/python/gem5/prebuilt/riscvmatched/riscvmatched_cache.py b/src/python/gem5/prebuilt/riscvmatched/riscvmatched_cache.py index dce1c5a964..213b4e7b1e 100644 --- a/src/python/gem5/prebuilt/riscvmatched/riscvmatched_cache.py +++ b/src/python/gem5/prebuilt/riscvmatched/riscvmatched_cache.py @@ -24,25 +24,33 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +from typing import Type + +from m5.objects import ( + BadAddr, + BaseXBar, + Cache, + L2XBar, + Port, + SystemXBar, +) + +from gem5.components.boards.abstract_board import AbstractBoard from gem5.components.cachehierarchies.abstract_cache_hierarchy import ( AbstractCacheHierarchy, ) -from gem5.components.cachehierarchies.classic.abstract_classic_cache_hierarchy import ( - AbstractClassicCacheHierarchy, -) from gem5.components.cachehierarchies.abstract_two_level_cache_hierarchy import ( AbstractTwoLevelCacheHierarchy, ) +from gem5.components.cachehierarchies.classic.abstract_classic_cache_hierarchy import ( + AbstractClassicCacheHierarchy, +) from gem5.components.cachehierarchies.classic.caches.l1dcache import L1DCache from gem5.components.cachehierarchies.classic.caches.l1icache import L1ICache from gem5.components.cachehierarchies.classic.caches.l2cache import L2Cache from gem5.components.cachehierarchies.classic.caches.mmu_cache import MMUCache -from gem5.components.boards.abstract_board import AbstractBoard from gem5.isas import ISA -from m5.objects import Cache, L2XBar, BaseXBar, SystemXBar, BadAddr, Port - from gem5.utils.override import * -from typing import Type class RISCVMatchedCacheHierarchy( diff --git a/src/python/gem5/prebuilt/riscvmatched/riscvmatched_core.py b/src/python/gem5/prebuilt/riscvmatched/riscvmatched_core.py index 19dc2f2e8c..1c7ea38ac1 100644 --- a/src/python/gem5/prebuilt/riscvmatched/riscvmatched_core.py +++ b/src/python/gem5/prebuilt/riscvmatched/riscvmatched_core.py @@ -25,20 +25,21 @@ # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. from typing import Optional -from gem5.utils.requires import requires + +from m5.objects import ( + BaseCPU, + BaseMMU, + Port, + Process, +) +from m5.objects.BaseMinorCPU import * +from m5.objects.RiscvCPU import RiscvMinorCPU + from gem5.components.processors.base_cpu_core import BaseCPUCore from gem5.components.processors.cpu_types import CPUTypes from gem5.isas import ISA from gem5.utils.override import overrides -from m5.objects.RiscvCPU import RiscvMinorCPU -from m5.objects import ( - BaseMMU, - Port, - BaseCPU, - Process, -) -from m5.objects.BaseMinorCPU import * -from gem5.isas import ISA +from gem5.utils.requires import requires class U74IntFU(MinorDefaultIntFU): diff --git a/src/python/gem5/prebuilt/riscvmatched/riscvmatched_processor.py b/src/python/gem5/prebuilt/riscvmatched/riscvmatched_processor.py index 838f810073..a1c9d5b8c2 100644 --- a/src/python/gem5/prebuilt/riscvmatched/riscvmatched_processor.py +++ b/src/python/gem5/prebuilt/riscvmatched/riscvmatched_processor.py @@ -24,14 +24,14 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from gem5.utils.override import overrides -from gem5.components.boards.mem_mode import MemMode - from m5.util import warn +from gem5.components.boards.abstract_board import AbstractBoard +from gem5.components.boards.mem_mode import MemMode from gem5.components.processors.base_cpu_processor import BaseCPUProcessor from gem5.components.processors.cpu_types import CPUTypes -from gem5.components.boards.abstract_board import AbstractBoard +from gem5.utils.override import overrides + from .riscvmatched_core import U74Core diff --git a/src/python/gem5/resources/client.py b/src/python/gem5/resources/client.py index 74475caec2..3428b037e0 100644 --- a/src/python/gem5/resources/client.py +++ b/src/python/gem5/resources/client.py @@ -25,14 +25,25 @@ # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. import json -from pathlib import Path import os -from typing import Optional, Dict, List -from .client_api.client_wrapper import ClientWrapper -from gem5.gem5_default_config import config -from m5.util import inform, warn +from pathlib import Path +from typing import ( + Dict, + List, + Optional, +) + +from m5.util import ( + inform, + warn, +) + from _m5 import core +from gem5.gem5_default_config import config + +from .client_api.client_wrapper import ClientWrapper + def getFileContent(file_path: Path) -> Dict: """ diff --git a/src/python/gem5/resources/client_api/abstract_client.py b/src/python/gem5/resources/client_api/abstract_client.py index 0365b5ca60..b58ac1efe2 100644 --- a/src/python/gem5/resources/client_api/abstract_client.py +++ b/src/python/gem5/resources/client_api/abstract_client.py @@ -24,9 +24,17 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from abc import ABC, abstractmethod -from typing import Any, Dict, List, Optional import urllib.parse +from abc import ( + ABC, + abstractmethod, +) +from typing import ( + Any, + Dict, + List, + Optional, +) class AbstractClient(ABC): diff --git a/src/python/gem5/resources/client_api/atlasclient.py b/src/python/gem5/resources/client_api/atlasclient.py index 7b1d263936..75adcf764d 100644 --- a/src/python/gem5/resources/client_api/atlasclient.py +++ b/src/python/gem5/resources/client_api/atlasclient.py @@ -24,14 +24,27 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from urllib import request, parse -from typing import Optional, Dict, Union, Type, Tuple, List, Any +import itertools import json import time -import itertools -from .abstract_client import AbstractClient +from typing import ( + Any, + Dict, + List, + Optional, + Tuple, + Type, + Union, +) +from urllib import ( + parse, + request, +) + from m5.util import warn +from .abstract_client import AbstractClient + class AtlasClientHttpJsonRequestError(Exception): def __init__( diff --git a/src/python/gem5/resources/client_api/client_wrapper.py b/src/python/gem5/resources/client_api/client_wrapper.py index 9ddd69e2df..0777535ca2 100644 --- a/src/python/gem5/resources/client_api/client_wrapper.py +++ b/src/python/gem5/resources/client_api/client_wrapper.py @@ -24,13 +24,21 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from .jsonclient import JSONClient -from .atlasclient import AtlasClient -from _m5 import core -from typing import Optional, Dict, List, Tuple import itertools -from m5.util import warn import sys +from typing import ( + Dict, + List, + Optional, + Tuple, +) + +from m5.util import warn + +from _m5 import core + +from .atlasclient import AtlasClient +from .jsonclient import JSONClient class ClientWrapper: diff --git a/src/python/gem5/resources/client_api/jsonclient.py b/src/python/gem5/resources/client_api/jsonclient.py index 9e837131b0..7ed15ccbe1 100644 --- a/src/python/gem5/resources/client_api/jsonclient.py +++ b/src/python/gem5/resources/client_api/jsonclient.py @@ -26,12 +26,22 @@ import json from pathlib import Path +from typing import ( + Any, + Dict, + List, + Optional, + Tuple, + Type, + Union, +) from urllib import request -from typing import Optional, Dict, Union, Type, Tuple, List, Any -from .abstract_client import AbstractClient from urllib.error import URLError + from m5.util import warn +from .abstract_client import AbstractClient + class JSONClient(AbstractClient): def __init__(self, path: str): diff --git a/src/python/gem5/resources/downloader.py b/src/python/gem5/resources/downloader.py index e9b4980b53..632980ef4d 100644 --- a/src/python/gem5/resources/downloader.py +++ b/src/python/gem5/resources/downloader.py @@ -24,29 +24,36 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -import urllib.request -import urllib.parse -import os -import shutil import gzip -import time +import os import random -from pathlib import Path +import shutil import tarfile +import time +import urllib.parse +import urllib.request +from pathlib import Path +from typing import ( + Dict, + List, + Optional, +) from urllib.error import HTTPError from urllib.parse import urlparse -from typing import List, Optional, Dict from _m5 import core -from .client import ( - get_resource_json_obj, - list_resources as client_list_resources, -) -from .md5_utils import md5_file, md5_dir -from ..utils.progress_bar import tqdm, progress_hook - from ..utils.filelock import FileLock +from ..utils.progress_bar import ( + progress_hook, + tqdm, +) +from .client import get_resource_json_obj +from .client import list_resources as client_list_resources +from .md5_utils import ( + md5_dir, + md5_file, +) """ This Python module contains functions used to download, list, and obtain @@ -86,10 +93,11 @@ def _download(url: str, download_to: str, max_attempts: int = 6) -> None: # If the "use_proxy" variable is specified we setup a socks5 # connection. - import socks import socket import ssl + import socks + IP_ADDR, host_port = use_proxy.split(":") PORT = int(host_port) socks.set_default_proxy(socks.SOCKS5, IP_ADDR, PORT) diff --git a/src/python/gem5/resources/elfie.py b/src/python/gem5/resources/elfie.py index ae51388d62..15afd718c1 100644 --- a/src/python/gem5/resources/elfie.py +++ b/src/python/gem5/resources/elfie.py @@ -24,11 +24,11 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from m5.params import PcCountPair -from m5.objects import PcCountTrackerManager - from typing import List +from m5.objects import PcCountTrackerManager +from m5.params import PcCountPair + class ELFieInfo: """Stores information to load/run ELFies diff --git a/src/python/gem5/resources/looppoint.py b/src/python/gem5/resources/looppoint.py index 6e26efefdc..80ae43ce9f 100644 --- a/src/python/gem5/resources/looppoint.py +++ b/src/python/gem5/resources/looppoint.py @@ -24,15 +24,20 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from m5.params import PcCountPair -from m5.objects import PcCountTrackerManager -import m5 - -import os import csv import json +import os from pathlib import Path -from typing import List, Optional, Dict, Union +from typing import ( + Dict, + List, + Optional, + Union, +) + +import m5 +from m5.objects import PcCountTrackerManager +from m5.params import PcCountPair class LooppointRegionPC: diff --git a/src/python/gem5/resources/md5_utils.py b/src/python/gem5/resources/md5_utils.py index a371274fef..a3d4e886f9 100644 --- a/src/python/gem5/resources/md5_utils.py +++ b/src/python/gem5/resources/md5_utils.py @@ -25,9 +25,9 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +import hashlib from pathlib import Path from typing import Type -import hashlib def _md5_update_from_file( diff --git a/src/python/gem5/resources/resource.py b/src/python/gem5/resources/resource.py index 98c58cf832..89741f0566 100644 --- a/src/python/gem5/resources/resource.py +++ b/src/python/gem5/resources/resource.py @@ -24,31 +24,39 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from abc import ABCMeta import json import os +from abc import ABCMeta from pathlib import Path -from m5.util import warn, fatal -from _m5 import core - -from .downloader import get_resource - -from .looppoint import LooppointCsvLoader, LooppointJsonLoader -from ..isas import ISA, get_isa_from_str - from typing import ( - Optional, - Dict, - Union, - Type, - Tuple, - List, Any, - Set, + Dict, Generator, + List, + Optional, + Set, + Tuple, + Type, + Union, ) +from m5.util import ( + fatal, + warn, +) + +from _m5 import core + +from ..isas import ( + ISA, + get_isa_from_str, +) from .client import get_resource_json_obj +from .downloader import get_resource +from .looppoint import ( + LooppointCsvLoader, + LooppointJsonLoader, +) """ Resources are items needed to run a simulation, such as a disk image, kernel, diff --git a/src/python/gem5/resources/workload.py b/src/python/gem5/resources/workload.py index bdb596921f..ef1ffbbb8c 100644 --- a/src/python/gem5/resources/workload.py +++ b/src/python/gem5/resources/workload.py @@ -24,13 +24,22 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from .resource import obtain_resource, WorkloadResource -from .client import get_resource_json_obj +from typing import ( + Any, + Dict, + List, + Optional, +) -from _m5 import core from m5.util import warn -from typing import Dict, Any, List, Optional +from _m5 import core + +from .client import get_resource_json_obj +from .resource import ( + WorkloadResource, + obtain_resource, +) def CustomWorkload(function: str, parameters: Dict[str, Any]): diff --git a/src/python/gem5/runtime.py b/src/python/gem5/runtime.py index 9118237f37..717e4a8c2b 100644 --- a/src/python/gem5/runtime.py +++ b/src/python/gem5/runtime.py @@ -28,12 +28,17 @@ This file contains functions to extract gem5 runtime information. """ +from typing import Set + from m5.defines import buildEnv from m5.util import warn -from .isas import ISA, get_isa_from_str, get_isas_str_set from .coherence_protocol import CoherenceProtocol -from typing import Set +from .isas import ( + ISA, + get_isa_from_str, + get_isas_str_set, +) def get_supported_isas() -> Set[ISA]: diff --git a/src/python/gem5/simulate/exit_event_generators.py b/src/python/gem5/simulate/exit_event_generators.py index 6f0e0a1eac..a8a5940746 100644 --- a/src/python/gem5/simulate/exit_event_generators.py +++ b/src/python/gem5/simulate/exit_event_generators.py @@ -24,14 +24,20 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from typing import Generator, Optional +from pathlib import Path +from typing import ( + Generator, + Optional, +) + import m5.stats +from m5.util import warn + +from gem5.resources.looppoint import Looppoint + from ..components.processors.abstract_processor import AbstractProcessor from ..components.processors.switchable_processor import SwitchableProcessor from ..resources.resource import SimpointResource -from gem5.resources.looppoint import Looppoint -from m5.util import warn -from pathlib import Path """ In this package we store generators for simulation exit events. diff --git a/src/python/gem5/simulate/simulator.py b/src/python/gem5/simulate/simulator.py index 5470202830..dcab20ebd4 100644 --- a/src/python/gem5/simulate/simulator.py +++ b/src/python/gem5/simulate/simulator.py @@ -24,29 +24,37 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -import m5 -import m5.ticks -from m5.stats import addStatVisitor -from m5.ext.pystats.simstat import SimStat -from m5.objects import Root -from m5.util import warn - import os import sys from pathlib import Path -from typing import Optional, List, Tuple, Dict, Generator, Union, Callable - -from .exit_event_generators import ( - warn_default_decorator, - exit_generator, - switch_generator, - save_checkpoint_generator, - reset_stats_generator, - dump_stats_generator, +from typing import ( + Callable, + Dict, + Generator, + List, + Optional, + Tuple, + Union, ) -from .exit_event import ExitEvent + +import m5 +import m5.ticks +from m5.ext.pystats.simstat import SimStat +from m5.objects import Root +from m5.stats import addStatVisitor +from m5.util import warn + from ..components.boards.abstract_board import AbstractBoard from ..components.processors.switchable_processor import SwitchableProcessor +from .exit_event import ExitEvent +from .exit_event_generators import ( + dump_stats_generator, + exit_generator, + reset_stats_generator, + save_checkpoint_generator, + switch_generator, + warn_default_decorator, +) class Simulator: diff --git a/src/python/gem5/utils/filelock.py b/src/python/gem5/utils/filelock.py index 309a9f868b..215b340ebb 100644 --- a/src/python/gem5/utils/filelock.py +++ b/src/python/gem5/utils/filelock.py @@ -23,9 +23,9 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF # THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +import errno import os import time -import errno class FileLockException(Exception): diff --git a/src/python/gem5/utils/multiprocessing/__init__.py b/src/python/gem5/utils/multiprocessing/__init__.py index 680aeac314..07a55250fa 100644 --- a/src/python/gem5/utils/multiprocessing/__init__.py +++ b/src/python/gem5/utils/multiprocessing/__init__.py @@ -24,9 +24,10 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from .context import Process - -from .context import gem5Context +from .context import ( + Process, + gem5Context, +) Pool = gem5Context().Pool diff --git a/src/python/gem5/utils/multiprocessing/_command_line.py b/src/python/gem5/utils/multiprocessing/_command_line.py index f68277540d..0baf198506 100644 --- a/src/python/gem5/utils/multiprocessing/_command_line.py +++ b/src/python/gem5/utils/multiprocessing/_command_line.py @@ -32,7 +32,10 @@ multiprocessing module (i.e., cpython/Lib/multiprocessing/). """ import sys -from multiprocessing import spawn, util +from multiprocessing import ( + spawn, + util, +) def _gem5_args_for_multiprocessing(name): diff --git a/src/python/gem5/utils/multiprocessing/context.py b/src/python/gem5/utils/multiprocessing/context.py index 0fc48e2789..03b554548d 100644 --- a/src/python/gem5/utils/multiprocessing/context.py +++ b/src/python/gem5/utils/multiprocessing/context.py @@ -30,7 +30,10 @@ Some code inspired by the Python standard library implementation of the multiprocessing module (i.e., cpython/Lib/multiprocessing/). """ -from multiprocessing import context, process +from multiprocessing import ( + context, + process, +) from multiprocessing.context import DefaultContext diff --git a/src/python/gem5/utils/multiprocessing/popen_spawn_gem5.py b/src/python/gem5/utils/multiprocessing/popen_spawn_gem5.py index 13fb3362fc..b40b8b4eeb 100644 --- a/src/python/gem5/utils/multiprocessing/popen_spawn_gem5.py +++ b/src/python/gem5/utils/multiprocessing/popen_spawn_gem5.py @@ -33,11 +33,15 @@ multiprocessing module (i.e., cpython/Lib/multiprocessing/). import io import os - -from multiprocessing.context import reduction, set_spawning_popen -from multiprocessing import popen_spawn_posix -from multiprocessing import spawn -from multiprocessing import util +from multiprocessing import ( + popen_spawn_posix, + spawn, + util, +) +from multiprocessing.context import ( + reduction, + set_spawning_popen, +) from ._command_line import get_command_line diff --git a/src/python/gem5/utils/requires.py b/src/python/gem5/utils/requires.py index 9d271aafa2..461a60ddd8 100644 --- a/src/python/gem5/utils/requires.py +++ b/src/python/gem5/utils/requires.py @@ -24,12 +24,16 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from ..runtime import get_runtime_coherence_protocol, get_supported_isas -from ..isas import ISA -from ..coherence_protocol import CoherenceProtocol -from typing import Optional -import os import inspect +import os +from typing import Optional + +from ..coherence_protocol import CoherenceProtocol +from ..isas import ISA +from ..runtime import ( + get_runtime_coherence_protocol, + get_supported_isas, +) def _get_exception_str(msg: str): diff --git a/src/python/gem5/utils/simpoint.py b/src/python/gem5/utils/simpoint.py index 0d1af4b1cf..b8c31d309c 100644 --- a/src/python/gem5/utils/simpoint.py +++ b/src/python/gem5/utils/simpoint.py @@ -24,9 +24,17 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from m5.util import fatal, warn from pathlib import Path -from typing import List, Tuple +from typing import ( + List, + Tuple, +) + +from m5.util import ( + fatal, + warn, +) + from gem5.resources.resource import SimpointResource diff --git a/src/python/m5/SimObject.py b/src/python/m5/SimObject.py index 31b0f5d180..3b80a09507 100644 --- a/src/python/m5/SimObject.py +++ b/src/python/m5/SimObject.py @@ -38,38 +38,39 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -import sys -from types import FunctionType, MethodType, ModuleType -from functools import wraps import inspect +import sys +from functools import wraps +from types import ( + FunctionType, + MethodType, + ModuleType, +) import m5 -from m5.util import * -from m5.util.pybind import * - from m5.citations import gem5_citations # Use the pyfdt and not the helper class, because the fdthelper # relies on the SimObject definition from m5.ext.pyfdt import pyfdt +# There are a few things we need that aren't in params.__all__ since +# normal users don't need them # Have to import params up top since Param is referenced on initial # load (when SimObject class references Param to create a class # variable, the 'name' param)... from m5.params import * - -# There are a few things we need that aren't in params.__all__ since -# normal users don't need them from m5.params import ( ParamDesc, + Port, + SimObjectVector, VectorParamDesc, isNullPointer, - SimObjectVector, - Port, ) - from m5.proxy import * from m5.proxy import isproxy +from m5.util import * +from m5.util.pybind import * ##################################################################### # diff --git a/src/python/m5/__init__.py b/src/python/m5/__init__.py index f029adffdc..a7bcf7a833 100644 --- a/src/python/m5/__init__.py +++ b/src/python/m5/__init__.py @@ -40,18 +40,19 @@ except ImportError: in_gem5 = False if in_gem5: - from . import SimObject - from . import core - from . import defines - from . import objects - from . import params - from . import stats + from . import ( + SimObject, + core, + defines, + objects, + params, + stats, + ) if defines.buildEnv["USE_SYSTEMC"]: from . import systemc from . import tlm from . import util - from .event import * from .main import main from .simulate import * diff --git a/src/python/m5/debug.py b/src/python/m5/debug.py index 09a032aa50..c4ae167989 100644 --- a/src/python/m5/debug.py +++ b/src/python/m5/debug.py @@ -26,11 +26,15 @@ from collections.abc import Mapping -import _m5.debug -from _m5.debug import SimpleFlag, CompoundFlag -from _m5.debug import schedBreak from m5.util import printList +import _m5.debug +from _m5.debug import ( + CompoundFlag, + SimpleFlag, + schedBreak, +) + def help(): sorted_flags = sorted(flags.items(), key=lambda kv: kv[0]) diff --git a/src/python/m5/event.py b/src/python/m5/event.py index 7c3f9a7c42..0f4cb8d947 100644 --- a/src/python/m5/event.py +++ b/src/python/m5/event.py @@ -39,11 +39,14 @@ # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. import m5 -import _m5.event +import _m5.event from _m5.event import GlobalSimLoopExitEvent as SimExit from _m5.event import PyEvent as Event -from _m5.event import getEventQueue, setEventQueue +from _m5.event import ( + getEventQueue, + setEventQueue, +) mainq = None diff --git a/src/python/m5/ext/pystats/__init__.py b/src/python/m5/ext/pystats/__init__.py index 32cee43296..0d15ee1ad1 100644 --- a/src/python/m5/ext/pystats/__init__.py +++ b/src/python/m5/ext/pystats/__init__.py @@ -25,13 +25,13 @@ # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. from .abstract_stat import AbstractStat -from .serializable_stat import SerializableStat from .group import Group +from .jsonloader import JsonLoader +from .serializable_stat import SerializableStat from .simstat import SimStat from .statistic import Statistic from .storagetype import StorageType from .timeconversion import TimeConversion -from .jsonloader import JsonLoader __all__ = [ "AbstractStat", diff --git a/src/python/m5/ext/pystats/abstract_stat.py b/src/python/m5/ext/pystats/abstract_stat.py index f2a75fca1e..d5b99b259e 100644 --- a/src/python/m5/ext/pystats/abstract_stat.py +++ b/src/python/m5/ext/pystats/abstract_stat.py @@ -24,8 +24,6 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from .serializable_stat import SerializableStat - import re from typing import ( Callable, @@ -35,6 +33,8 @@ from typing import ( Union, ) +from .serializable_stat import SerializableStat + class AbstractStat(SerializableStat): """ diff --git a/src/python/m5/ext/pystats/group.py b/src/python/m5/ext/pystats/group.py index 0b71663565..bc292c9d0b 100644 --- a/src/python/m5/ext/pystats/group.py +++ b/src/python/m5/ext/pystats/group.py @@ -33,7 +33,10 @@ from typing import ( ) from .abstract_stat import AbstractStat -from .statistic import Scalar, Statistic +from .statistic import ( + Scalar, + Statistic, +) from .timeconversion import TimeConversion diff --git a/src/python/m5/ext/pystats/jsonloader.py b/src/python/m5/ext/pystats/jsonloader.py index 7461f8d7a8..f83c2caa68 100644 --- a/src/python/m5/ext/pystats/jsonloader.py +++ b/src/python/m5/ext/pystats/jsonloader.py @@ -24,12 +24,24 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from json.decoder import JSONDecodeError -from .simstat import SimStat -from .statistic import Scalar, Distribution, Accumulator, Statistic -from .group import Group, Vector import json -from typing import IO, Union +from json.decoder import JSONDecodeError +from typing import ( + IO, + Union, +) + +from .group import ( + Group, + Vector, +) +from .simstat import SimStat +from .statistic import ( + Accumulator, + Distribution, + Scalar, + Statistic, +) class JsonLoader(json.JSONDecoder): diff --git a/src/python/m5/ext/pystats/serializable_stat.py b/src/python/m5/ext/pystats/serializable_stat.py index c4de181e70..bb63b2a044 100644 --- a/src/python/m5/ext/pystats/serializable_stat.py +++ b/src/python/m5/ext/pystats/serializable_stat.py @@ -24,9 +24,15 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from datetime import datetime import json -from typing import Dict, List, Union, Any, IO +from datetime import datetime +from typing import ( + IO, + Any, + Dict, + List, + Union, +) from .storagetype import StorageType diff --git a/src/python/m5/ext/pystats/simstat.py b/src/python/m5/ext/pystats/simstat.py index c7c28f419a..06858bb9ad 100644 --- a/src/python/m5/ext/pystats/simstat.py +++ b/src/python/m5/ext/pystats/simstat.py @@ -25,7 +25,12 @@ # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. from datetime import datetime -from typing import Dict, List, Optional, Union +from typing import ( + Dict, + List, + Optional, + Union, +) from .abstract_stat import AbstractStat from .group import Group diff --git a/src/python/m5/ext/pystats/statistic.py b/src/python/m5/ext/pystats/statistic.py index 4111bde23e..019ec8a042 100644 --- a/src/python/m5/ext/pystats/statistic.py +++ b/src/python/m5/ext/pystats/statistic.py @@ -25,7 +25,13 @@ # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. from abc import ABC -from typing import Any, Iterable, Optional, Union, List +from typing import ( + Any, + Iterable, + List, + Optional, + Union, +) from .abstract_stat import AbstractStat from .storagetype import StorageType diff --git a/src/python/m5/main.py b/src/python/m5/main.py index 31eaf83690..e346b16a5c 100644 --- a/src/python/m5/main.py +++ b/src/python/m5/main.py @@ -379,18 +379,24 @@ def _check_tracing(): def main(): import m5 + from m5.util.terminal_formatter import TerminalFormatter + import _m5.core - from . import core - from . import debug - from . import defines - from . import event - from . import info - from . import stats - from . import trace - - from .util import inform, panic, isInteractive - from m5.util.terminal_formatter import TerminalFormatter + from . import ( + core, + debug, + defines, + event, + info, + stats, + trace, + ) + from .util import ( + inform, + isInteractive, + panic, + ) options, arguments = parse_options() diff --git a/src/python/m5/objects/SimObject.py b/src/python/m5/objects/SimObject.py index 6cf44d07c2..af6b0998b9 100644 --- a/src/python/m5/objects/SimObject.py +++ b/src/python/m5/objects/SimObject.py @@ -23,8 +23,7 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from m5.SimObject import * - # The ByteOrder enum is defined in params. Expose it here so we can declare it # to SCons, since there's no normal SimObject file to make it a part of. from m5.params import ByteOrder +from m5.SimObject import * diff --git a/src/python/m5/options.py b/src/python/m5/options.py index aac7d1ac74..a4928960cc 100644 --- a/src/python/m5/options.py +++ b/src/python/m5/options.py @@ -26,7 +26,6 @@ import optparse import sys - from optparse import * diff --git a/src/python/m5/params.py b/src/python/m5/params.py index 86a33c739d..32723a7860 100644 --- a/src/python/m5/params.py +++ b/src/python/m5/params.py @@ -56,13 +56,15 @@ import copy import datetime +import math import re import sys import time -import math -from . import proxy -from . import ticks +from . import ( + proxy, + ticks, +) from .util import * @@ -1099,10 +1101,12 @@ class HostSocket(ParamValue): self.value = value def getValue(self): - from _m5.socket import listenSocketEmptyConfig - from _m5.socket import listenSocketInetConfig - from _m5.socket import listenSocketUnixFileConfig - from _m5.socket import listenSocketUnixAbstractConfig + from _m5.socket import ( + listenSocketEmptyConfig, + listenSocketInetConfig, + listenSocketUnixAbstractConfig, + listenSocketUnixFileConfig, + ) if isinstance(self.value, str): if self.value[0] == "@": @@ -1443,8 +1447,16 @@ time_formats = [ def parse_time(value): - from time import gmtime, strptime, struct_time, time - from datetime import datetime, date + from datetime import ( + date, + datetime, + ) + from time import ( + gmtime, + strptime, + struct_time, + time, + ) if isinstance(value, struct_time): return value @@ -1483,9 +1495,10 @@ class Time(ParamValue): return value def getValue(self): - from _m5.core import tm import calendar + from _m5.core import tm + return tm.gmtime(calendar.timegm(self.value)) def __str__(self): diff --git a/src/python/m5/simulate.py b/src/python/m5/simulate.py index d619697247..c2a0eebb22 100644 --- a/src/python/m5/simulate.py +++ b/src/python/m5/simulate.py @@ -41,22 +41,31 @@ import atexit import os import sys -# import the wrapped C++ functions -import _m5.drain -import _m5.core -from _m5.stats import updateEvents as updateStatEvents - -from . import stats -from . import SimObject -from . import ticks -from . import objects -from . import params -from .citations import gather_citations -from m5.util.dot_writer import do_dot, do_dvfs_dot +from m5.util.dot_writer import ( + do_dot, + do_dvfs_dot, +) from m5.util.dot_writer_ruby import do_ruby_dot -from .util import fatal, warn -from .util import attrdict +import _m5.core + +# import the wrapped C++ functions +import _m5.drain +from _m5.stats import updateEvents as updateStatEvents + +from . import ( + SimObject, + objects, + params, + stats, + ticks, +) +from .citations import gather_citations +from .util import ( + attrdict, + fatal, + warn, +) # define a MaxTick parameter, unsigned 64 bit MaxTick = 2**64 - 1 @@ -482,6 +491,9 @@ def fork(simout="%(parent)s.f%(fork_seq)i"): return pid -from _m5.core import disableAllListeners, listenersDisabled -from _m5.core import listenersLoopbackOnly -from _m5.core import curTick +from _m5.core import ( + curTick, + disableAllListeners, + listenersDisabled, + listenersLoopbackOnly, +) diff --git a/src/python/m5/stats/__init__.py b/src/python/m5/stats/__init__.py index ce7a2d267d..de129c1817 100644 --- a/src/python/m5/stats/__init__.py +++ b/src/python/m5/stats/__init__.py @@ -38,16 +38,20 @@ # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. import m5 - -import _m5.stats from m5.objects import Root from m5.params import isNullPointer -from .gem5stats import JsonOutputVistor -from m5.util import attrdict, fatal +from m5.util import ( + attrdict, + fatal, +) + +import _m5.stats # Stat exports -from _m5.stats import schedStatEvent as schedEvent from _m5.stats import periodicStatDump +from _m5.stats import schedStatEvent as schedEvent + +from .gem5stats import JsonOutputVistor outputList = [] diff --git a/src/python/m5/stats/gem5stats.py b/src/python/m5/stats/gem5stats.py index 07636e3e3f..2d79015627 100644 --- a/src/python/m5/stats/gem5stats.py +++ b/src/python/m5/stats/gem5stats.py @@ -30,14 +30,19 @@ the Python Stats model. """ from datetime import datetime -from typing import IO, List, Union +from typing import ( + IO, + List, + Union, +) -import _m5.stats -from m5.objects import * from m5.ext.pystats.group import * from m5.ext.pystats.simstat import * from m5.ext.pystats.statistic import * from m5.ext.pystats.storagetype import * +from m5.objects import * + +import _m5.stats class JsonOutputVistor: diff --git a/src/python/m5/ticks.py b/src/python/m5/ticks.py index 7ec84c3709..c44ac7a13f 100644 --- a/src/python/m5/ticks.py +++ b/src/python/m5/ticks.py @@ -25,8 +25,8 @@ # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. import decimal - import sys + from m5.util import warn @@ -39,6 +39,7 @@ def fixGlobalFrequency(): def setGlobalFrequency(ticksPerSecond): from m5.util import convert + import _m5.core if isinstance(ticksPerSecond, int): diff --git a/src/python/m5/trace.py b/src/python/m5/trace.py index 759f96e5bf..6aa88e7644 100644 --- a/src/python/m5/trace.py +++ b/src/python/m5/trace.py @@ -25,4 +25,10 @@ # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. # Export native methods to Python -from _m5.trace import output, activate, ignore, disable, enable +from _m5.trace import ( + activate, + disable, + enable, + ignore, + output, +) diff --git a/src/python/m5/util/__init__.py b/src/python/m5/util/__init__.py index e1c9bd226a..3fab2d8931 100644 --- a/src/python/m5/util/__init__.py +++ b/src/python/m5/util/__init__.py @@ -40,12 +40,14 @@ import os import re import sys - from functools import wraps from . import convert - -from .attrdict import attrdict, multiattrdict, optiondict +from .attrdict import ( + attrdict, + multiattrdict, + optiondict, +) from .multidict import multidict diff --git a/src/python/m5/util/dot_writer.py b/src/python/m5/util/dot_writer.py index 59886480a5..1257470306 100644 --- a/src/python/m5/util/dot_writer.py +++ b/src/python/m5/util/dot_writer.py @@ -53,9 +53,18 @@ # ##################################################################### -import m5, os, re -from m5.SimObject import isRoot, isSimObjectVector -from m5.params import PortRef, isNullPointer +import os +import re + +import m5 +from m5.params import ( + PortRef, + isNullPointer, +) +from m5.SimObject import ( + isRoot, + isSimObjectVector, +) from m5.util import warn try: diff --git a/src/python/m5/util/dot_writer_ruby.py b/src/python/m5/util/dot_writer_ruby.py index fa21ae1a01..be5d406278 100644 --- a/src/python/m5/util/dot_writer_ruby.py +++ b/src/python/m5/util/dot_writer_ruby.py @@ -36,6 +36,7 @@ # Creates a visual representation of a Ruby network topology import os + import m5 from m5.util import warn diff --git a/src/python/m5/util/fdthelper.py b/src/python/m5/util/fdthelper.py index 1f565df270..8a265d1d4e 100644 --- a/src/python/m5/util/fdthelper.py +++ b/src/python/m5/util/fdthelper.py @@ -35,9 +35,10 @@ # # Author: Glenn Bergmans -from m5.ext.pyfdt import pyfdt -import re import os +import re + +from m5.ext.pyfdt import pyfdt from m5.SimObject import SimObject from m5.util import fatal diff --git a/src/python/m5/util/terminal_formatter.py b/src/python/m5/util/terminal_formatter.py index da441b1188..a8a8e21914 100644 --- a/src/python/m5/util/terminal_formatter.py +++ b/src/python/m5/util/terminal_formatter.py @@ -34,7 +34,9 @@ class TerminalFormatter: self.__text_width = min(max_width, self.__terminal_size()[0]) def __terminal_size(self): - import fcntl, termios, struct + import fcntl + import struct + import termios h, w, hp, wp = struct.unpack( "HHHH", diff --git a/src/sim/ClockDomain.py b/src/sim/ClockDomain.py index 34380f916b..4c4c6e765f 100644 --- a/src/sim/ClockDomain.py +++ b/src/sim/ClockDomain.py @@ -34,8 +34,8 @@ # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. from m5.params import * -from m5.SimObject import SimObject from m5.proxy import * +from m5.SimObject import SimObject # Abstract clock domain diff --git a/src/sim/ClockedObject.py b/src/sim/ClockedObject.py index 5d1656e520..75a9fae597 100644 --- a/src/sim/ClockedObject.py +++ b/src/sim/ClockedObject.py @@ -34,9 +34,9 @@ # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. from m5.objects.PowerState import PowerState -from m5.SimObject import SimObject from m5.params import * from m5.proxy import * +from m5.SimObject import SimObject class ClockedObject(SimObject): diff --git a/src/sim/DVFSHandler.py b/src/sim/DVFSHandler.py index 13c649dbb0..41aaffc897 100644 --- a/src/sim/DVFSHandler.py +++ b/src/sim/DVFSHandler.py @@ -34,8 +34,8 @@ # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. from m5.params import * -from m5.SimObject import SimObject from m5.proxy import * +from m5.SimObject import SimObject # The handler in its current form is design to be centeralized, one per system diff --git a/src/sim/InstTracer.py b/src/sim/InstTracer.py index c8b3673d47..4470cd1125 100644 --- a/src/sim/InstTracer.py +++ b/src/sim/InstTracer.py @@ -36,8 +36,8 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from m5.SimObject import SimObject from m5.params import * +from m5.SimObject import SimObject class InstDisassembler(SimObject): diff --git a/src/sim/PowerDomain.py b/src/sim/PowerDomain.py index 64018e6d15..cda7a300ee 100644 --- a/src/sim/PowerDomain.py +++ b/src/sim/PowerDomain.py @@ -36,8 +36,8 @@ import sys -from m5.params import * from m5.objects.PowerState import PowerState +from m5.params import * # A power domain groups multiple ClockedObjects and creates a diff --git a/src/sim/PowerState.py b/src/sim/PowerState.py index 9c9fe03a5a..5e6d900710 100644 --- a/src/sim/PowerState.py +++ b/src/sim/PowerState.py @@ -34,9 +34,9 @@ # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. # -from m5.SimObject import SimObject from m5.params import * from m5.proxy import * +from m5.SimObject import SimObject # Enumerate set of allowed power states that can be used by a clocked object. diff --git a/src/sim/Process.py b/src/sim/Process.py index 0b87b09485..0f911f9f65 100644 --- a/src/sim/Process.py +++ b/src/sim/Process.py @@ -24,10 +24,11 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from m5.SimObject import * +from os import getcwd + from m5.params import * from m5.proxy import * -from os import getcwd +from m5.SimObject import * class Process(SimObject): diff --git a/src/sim/RedirectPath.py b/src/sim/RedirectPath.py index c6c63e2558..91ed5891da 100644 --- a/src/sim/RedirectPath.py +++ b/src/sim/RedirectPath.py @@ -24,9 +24,9 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from m5.SimObject import SimObject from m5.params import * from m5.proxy import * +from m5.SimObject import SimObject class RedirectPath(SimObject): diff --git a/src/sim/Root.py b/src/sim/Root.py index 5ad42da668..fae560491f 100644 --- a/src/sim/Root.py +++ b/src/sim/Root.py @@ -26,8 +26,8 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from m5.SimObject import SimObject from m5.params import * +from m5.SimObject import SimObject from m5.util import fatal diff --git a/src/sim/SignalPort.py b/src/sim/SignalPort.py index fc529a8b45..bdb6d5eae1 100644 --- a/src/sim/SignalPort.py +++ b/src/sim/SignalPort.py @@ -23,7 +23,10 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from m5.params import Port, VectorPort +from m5.params import ( + Port, + VectorPort, +) SIGNAL_SOURCE_ROLE_TEMPLATE = "Signal source <%s>" SIGNAL_SINK_ROLE_TEMPLATE = "Signal sink <%s>" diff --git a/src/sim/SubSystem.py b/src/sim/SubSystem.py index 49f70d5b8a..19df9d2b83 100644 --- a/src/sim/SubSystem.py +++ b/src/sim/SubSystem.py @@ -33,8 +33,8 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from m5.SimObject import SimObject from m5.params import * +from m5.SimObject import SimObject # An empty simobject. Used for organizing simobjects diff --git a/src/sim/System.py b/src/sim/System.py index eb1280f248..fb6ff8622c 100644 --- a/src/sim/System.py +++ b/src/sim/System.py @@ -37,13 +37,12 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from m5.SimObject import * -from m5.params import * -from m5.proxy import * - from m5.objects.DVFSHandler import * from m5.objects.SimpleMemory import * from m5.objects.Workload import StubWorkload +from m5.params import * +from m5.proxy import * +from m5.SimObject import * class MemoryMode(Enum): diff --git a/src/sim/VoltageDomain.py b/src/sim/VoltageDomain.py index 79116edfd3..9d2c503a81 100644 --- a/src/sim/VoltageDomain.py +++ b/src/sim/VoltageDomain.py @@ -33,8 +33,8 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from m5.SimObject import SimObject from m5.params import * +from m5.SimObject import SimObject class VoltageDomain(SimObject): diff --git a/src/sim/Workload.py b/src/sim/Workload.py index 31ea7382dd..998c6c13d6 100644 --- a/src/sim/Workload.py +++ b/src/sim/Workload.py @@ -23,10 +23,12 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from m5.params import * -from m5.SimObject import SimObject, cxxMethod - from m5.objects.SimpleMemory import * +from m5.params import * +from m5.SimObject import ( + SimObject, + cxxMethod, +) class Workload(SimObject): diff --git a/src/sim/power/MathExprPowerModel.py b/src/sim/power/MathExprPowerModel.py index 6f335980a4..baa5b0dae6 100644 --- a/src/sim/power/MathExprPowerModel.py +++ b/src/sim/power/MathExprPowerModel.py @@ -33,9 +33,9 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from m5.SimObject import SimObject -from m5.params import * from m5.objects.PowerModelState import PowerModelState +from m5.params import * +from m5.SimObject import SimObject # Represents a power model for a simobj diff --git a/src/sim/power/PowerModel.py b/src/sim/power/PowerModel.py index f45f24a3cc..df09672966 100644 --- a/src/sim/power/PowerModel.py +++ b/src/sim/power/PowerModel.py @@ -33,9 +33,9 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from m5.SimObject import * from m5.params import * from m5.proxy import Parent +from m5.SimObject import * # Enum for a type of power model diff --git a/src/sim/power/PowerModelState.py b/src/sim/power/PowerModelState.py index ba7bd44915..2a427242fa 100644 --- a/src/sim/power/PowerModelState.py +++ b/src/sim/power/PowerModelState.py @@ -33,8 +33,8 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from m5.SimObject import * from m5.params import * +from m5.SimObject import * # Represents a power model for a simobj diff --git a/src/sim/power/ThermalDomain.py b/src/sim/power/ThermalDomain.py index ff5fdaff3f..eace9c101d 100644 --- a/src/sim/power/ThermalDomain.py +++ b/src/sim/power/ThermalDomain.py @@ -33,8 +33,8 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from m5.SimObject import * from m5.params import * +from m5.SimObject import * # Represents a group of simobj which produce heat diff --git a/src/sim/power/ThermalModel.py b/src/sim/power/ThermalModel.py index 0d45a384c6..823a72ea4f 100644 --- a/src/sim/power/ThermalModel.py +++ b/src/sim/power/ThermalModel.py @@ -33,11 +33,10 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from m5.SimObject import * -from m5.objects.ClockedObject import ClockedObject - -from m5.params import * from m5.objects import ThermalDomain +from m5.objects.ClockedObject import ClockedObject +from m5.params import * +from m5.SimObject import * # Represents a thermal node diff --git a/src/sim/probe/Probe.py b/src/sim/probe/Probe.py index 006149a0b9..38664213fb 100644 --- a/src/sim/probe/Probe.py +++ b/src/sim/probe/Probe.py @@ -35,9 +35,9 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from m5.SimObject import SimObject from m5.params import * from m5.proxy import * +from m5.SimObject import SimObject class ProbeListenerObject(SimObject): diff --git a/src/systemc/Tlm.py b/src/systemc/Tlm.py index 5b43a3b557..da4e4763b4 100644 --- a/src/systemc/Tlm.py +++ b/src/systemc/Tlm.py @@ -23,7 +23,10 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from m5.params import Port, VectorPort +from m5.params import ( + Port, + VectorPort, +) def TLM_TARGET_ROLE(width): diff --git a/src/systemc/core/SystemC.py b/src/systemc/core/SystemC.py index a51c33f86f..75f59db597 100644 --- a/src/systemc/core/SystemC.py +++ b/src/systemc/core/SystemC.py @@ -23,7 +23,10 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from m5.SimObject import SimObject, cxxMethod +from m5.SimObject import ( + SimObject, + cxxMethod, +) # This class represents the systemc kernel. There should be exactly one in the diff --git a/src/systemc/python/systemc.py b/src/systemc/python/systemc.py index f5a364a006..d6c90534dc 100644 --- a/src/systemc/python/systemc.py +++ b/src/systemc/python/systemc.py @@ -24,10 +24,12 @@ # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. import _m5.systemc - -from _m5.systemc import sc_main -from _m5.systemc import sc_time -from _m5.systemc import sc_main_result_code, sc_main_result_str +from _m5.systemc import ( + sc_main, + sc_main_result_code, + sc_main_result_str, + sc_time, +) class ScMainResult: diff --git a/src/systemc/python/tlm.py b/src/systemc/python/tlm.py index 7b342811f6..e5ec7426f0 100644 --- a/src/systemc/python/tlm.py +++ b/src/systemc/python/tlm.py @@ -24,7 +24,6 @@ # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. import _m5.systemc - from _m5.systemc import tlm_global_quantum diff --git a/src/systemc/tests/config.py b/src/systemc/tests/config.py index 1c2e021830..0be50d12c9 100755 --- a/src/systemc/tests/config.py +++ b/src/systemc/tests/config.py @@ -24,12 +24,15 @@ # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. import argparse -import m5 import os import re import sys -from m5.objects import SystemC_Kernel, Root +import m5 +from m5.objects import ( + Root, + SystemC_Kernel, +) # pylint:disable=unused-variable diff --git a/src/systemc/tlm_bridge/TlmBridge.py b/src/systemc/tlm_bridge/TlmBridge.py index 546b4c0790..bc0491132e 100644 --- a/src/systemc/tlm_bridge/TlmBridge.py +++ b/src/systemc/tlm_bridge/TlmBridge.py @@ -24,11 +24,13 @@ # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. from m5.objects.SystemC import SystemC_ScModule +from m5.objects.Tlm import ( + TlmInitiatorSocket, + TlmTargetSocket, +) from m5.params import * from m5.proxy import * -from m5.objects.Tlm import TlmTargetSocket, TlmInitiatorSocket - class Gem5ToTlmBridgeBase(SystemC_ScModule): type = "Gem5ToTlmBridgeBase" diff --git a/tests/gem5/__init__.py b/tests/gem5/__init__.py index 0955469d08..0526afd962 100644 --- a/tests/gem5/__init__.py +++ b/tests/gem5/__init__.py @@ -24,8 +24,8 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -import testlib.suite import testlib.fixture +import testlib.suite -from .suite import * from .fixture import * +from .suite import * diff --git a/tests/gem5/arm_boot_tests/configs/arm_boot_exit_run.py b/tests/gem5/arm_boot_tests/configs/arm_boot_exit_run.py index ffb41459f5..61931d1a7e 100644 --- a/tests/gem5/arm_boot_tests/configs/arm_boot_exit_run.py +++ b/tests/gem5/arm_boot_tests/configs/arm_boot_exit_run.py @@ -33,24 +33,27 @@ Characteristics * Runs exclusively on the ARM ISA with the classic caches """ -from gem5.isas import ISA -from m5.objects import ArmDefaultRelease -from gem5.utils.requires import requires -from gem5.resources.resource import obtain_resource -from gem5.simulate.simulator import Simulator -from m5.objects import VExpress_GEM5_Foundation -from gem5.coherence_protocol import CoherenceProtocol -from gem5.components.boards.arm_board import ArmBoard -from gem5.components.processors.simple_processor import SimpleProcessor -from gem5.components.processors.cpu_types import ( - get_cpu_types_str_set, - get_cpu_type_from_str, - CPUTypes, -) - import argparse import importlib +from m5.objects import ( + ArmDefaultRelease, + VExpress_GEM5_Foundation, +) + +from gem5.coherence_protocol import CoherenceProtocol +from gem5.components.boards.arm_board import ArmBoard +from gem5.components.processors.cpu_types import ( + CPUTypes, + get_cpu_type_from_str, + get_cpu_types_str_set, +) +from gem5.components.processors.simple_processor import SimpleProcessor +from gem5.isas import ISA +from gem5.resources.resource import obtain_resource +from gem5.simulate.simulator import Simulator +from gem5.utils.requires import requires + parser = argparse.ArgumentParser( description="A script to run the ARM boot exit tests." ) diff --git a/tests/gem5/arm_boot_tests/test_linux_boot.py b/tests/gem5/arm_boot_tests/test_linux_boot.py index 23921ef403..074f3364b5 100644 --- a/tests/gem5/arm_boot_tests/test_linux_boot.py +++ b/tests/gem5/arm_boot_tests/test_linux_boot.py @@ -25,7 +25,6 @@ # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. import re - from typing import Optional from testlib import * diff --git a/tests/gem5/asmtest/configs/riscv_asmtest.py b/tests/gem5/asmtest/configs/riscv_asmtest.py index e98ec1bd49..d6582e4698 100644 --- a/tests/gem5/asmtest/configs/riscv_asmtest.py +++ b/tests/gem5/asmtest/configs/riscv_asmtest.py @@ -31,19 +31,19 @@ The system has no cache heirarchy and is as "bare-bones" as you can get in gem5 while still being functinal. """ -from gem5.resources.resource import obtain_resource -from gem5.components.processors.cpu_types import ( - get_cpu_types_str_set, - get_cpu_type_from_str, -) -from gem5.components.memory import SingleChannelDDR3_1600 +import argparse + from gem5.components.boards.simple_board import SimpleBoard from gem5.components.cachehierarchies.classic.no_cache import NoCache +from gem5.components.memory import SingleChannelDDR3_1600 +from gem5.components.processors.cpu_types import ( + get_cpu_type_from_str, + get_cpu_types_str_set, +) from gem5.components.processors.simple_processor import SimpleProcessor -from gem5.simulate.simulator import Simulator from gem5.isas import ISA - -import argparse +from gem5.resources.resource import obtain_resource +from gem5.simulate.simulator import Simulator parser = argparse.ArgumentParser( description="A gem5 script for testing RISC-V instructions" diff --git a/tests/gem5/checkpoint_tests/configs/arm-hello-restore-checkpoint.py b/tests/gem5/checkpoint_tests/configs/arm-hello-restore-checkpoint.py index 0ce9a7606a..f5dfe4cfc8 100644 --- a/tests/gem5/checkpoint_tests/configs/arm-hello-restore-checkpoint.py +++ b/tests/gem5/checkpoint_tests/configs/arm-hello-restore-checkpoint.py @@ -34,19 +34,20 @@ runs the rest of "arm-hello64-static" binary simulation. This configuration serves as a test of restoring a checkpoint with ARM ISA. """ -from gem5.isas import ISA -from gem5.utils.requires import requires -from gem5.resources.resource import obtain_resource, CheckpointResource - +from gem5.components.boards.simple_board import SimpleBoard from gem5.components.cachehierarchies.classic.private_l1_private_l2_cache_hierarchy import ( PrivateL1PrivateL2CacheHierarchy, ) -from gem5.components.boards.simple_board import SimpleBoard -from gem5.components.processors.simple_processor import SimpleProcessor -from gem5.simulate.simulator import Simulator from gem5.components.memory import SingleChannelDDR3_1600 from gem5.components.processors.cpu_types import CPUTypes - +from gem5.components.processors.simple_processor import SimpleProcessor +from gem5.isas import ISA +from gem5.resources.resource import ( + CheckpointResource, + obtain_resource, +) +from gem5.simulate.simulator import Simulator +from gem5.utils.requires import requires requires(isa_required=ISA.ARM) diff --git a/tests/gem5/checkpoint_tests/configs/arm-hello-save-checkpoint.py b/tests/gem5/checkpoint_tests/configs/arm-hello-save-checkpoint.py index a731b38a58..16fc2a00f0 100644 --- a/tests/gem5/checkpoint_tests/configs/arm-hello-save-checkpoint.py +++ b/tests/gem5/checkpoint_tests/configs/arm-hello-save-checkpoint.py @@ -25,17 +25,18 @@ # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. import argparse -from gem5.isas import ISA -from gem5.utils.requires import requires -from gem5.resources.resource import obtain_resource + +from gem5.components.boards.simple_board import SimpleBoard from gem5.components.cachehierarchies.classic.private_l1_private_l2_cache_hierarchy import ( PrivateL1PrivateL2CacheHierarchy, ) -from gem5.components.boards.simple_board import SimpleBoard -from gem5.components.processors.simple_processor import SimpleProcessor -from gem5.simulate.simulator import Simulator from gem5.components.memory import SingleChannelDDR3_1600 from gem5.components.processors.cpu_types import CPUTypes +from gem5.components.processors.simple_processor import SimpleProcessor +from gem5.isas import ISA +from gem5.resources.resource import obtain_resource +from gem5.simulate.simulator import Simulator +from gem5.utils.requires import requires parser = argparse.ArgumentParser() diff --git a/tests/gem5/checkpoint_tests/configs/power-hello-restore-checkpoint.py b/tests/gem5/checkpoint_tests/configs/power-hello-restore-checkpoint.py index 05479bcca7..bd717f3c62 100644 --- a/tests/gem5/checkpoint_tests/configs/power-hello-restore-checkpoint.py +++ b/tests/gem5/checkpoint_tests/configs/power-hello-restore-checkpoint.py @@ -33,16 +33,18 @@ runs the rest of "power-hello" binary simulation. This configuration serves as a test of restoring a checkpoint with POWER ISA. """ -from gem5.isas import ISA -from gem5.utils.requires import requires -from gem5.resources.resource import obtain_resource, CheckpointResource -from gem5.components.cachehierarchies.classic.no_cache import NoCache from gem5.components.boards.simple_board import SimpleBoard -from gem5.components.processors.simple_processor import SimpleProcessor -from gem5.simulate.simulator import Simulator +from gem5.components.cachehierarchies.classic.no_cache import NoCache from gem5.components.memory import SingleChannelDDR3_1600 from gem5.components.processors.cpu_types import CPUTypes - +from gem5.components.processors.simple_processor import SimpleProcessor +from gem5.isas import ISA +from gem5.resources.resource import ( + CheckpointResource, + obtain_resource, +) +from gem5.simulate.simulator import Simulator +from gem5.utils.requires import requires requires(isa_required=ISA.POWER) diff --git a/tests/gem5/checkpoint_tests/configs/power-hello-save-checkpoint.py b/tests/gem5/checkpoint_tests/configs/power-hello-save-checkpoint.py index 6fb99a2534..594d6610e0 100644 --- a/tests/gem5/checkpoint_tests/configs/power-hello-save-checkpoint.py +++ b/tests/gem5/checkpoint_tests/configs/power-hello-save-checkpoint.py @@ -32,15 +32,16 @@ with POWER ISA. """ import argparse -from gem5.isas import ISA -from gem5.utils.requires import requires -from gem5.resources.resource import obtain_resource -from gem5.components.cachehierarchies.classic.no_cache import NoCache + from gem5.components.boards.simple_board import SimpleBoard -from gem5.components.processors.simple_processor import SimpleProcessor -from gem5.simulate.simulator import Simulator +from gem5.components.cachehierarchies.classic.no_cache import NoCache from gem5.components.memory import SingleChannelDDR3_1600 from gem5.components.processors.cpu_types import CPUTypes +from gem5.components.processors.simple_processor import SimpleProcessor +from gem5.isas import ISA +from gem5.resources.resource import obtain_resource +from gem5.simulate.simulator import Simulator +from gem5.utils.requires import requires parser = argparse.ArgumentParser() diff --git a/tests/gem5/checkpoint_tests/configs/sparc-hello-restore-checkpoint.py b/tests/gem5/checkpoint_tests/configs/sparc-hello-restore-checkpoint.py index 0bc2e122cd..447c6bd325 100644 --- a/tests/gem5/checkpoint_tests/configs/sparc-hello-restore-checkpoint.py +++ b/tests/gem5/checkpoint_tests/configs/sparc-hello-restore-checkpoint.py @@ -33,16 +33,18 @@ runs the rest of "sparc-hello" binary simulation. This configuration serves as a test of restoring a checkpoint with SPARC ISA. """ -from gem5.isas import ISA -from gem5.utils.requires import requires -from gem5.resources.resource import obtain_resource, CheckpointResource -from gem5.components.cachehierarchies.classic.no_cache import NoCache from gem5.components.boards.simple_board import SimpleBoard -from gem5.components.processors.simple_processor import SimpleProcessor -from gem5.simulate.simulator import Simulator +from gem5.components.cachehierarchies.classic.no_cache import NoCache from gem5.components.memory import SingleChannelDDR3_1600 from gem5.components.processors.cpu_types import CPUTypes - +from gem5.components.processors.simple_processor import SimpleProcessor +from gem5.isas import ISA +from gem5.resources.resource import ( + CheckpointResource, + obtain_resource, +) +from gem5.simulate.simulator import Simulator +from gem5.utils.requires import requires requires(isa_required=ISA.SPARC) diff --git a/tests/gem5/checkpoint_tests/configs/sparc-hello-save-checkpoint.py b/tests/gem5/checkpoint_tests/configs/sparc-hello-save-checkpoint.py index ab216588aa..f85ff41dbc 100644 --- a/tests/gem5/checkpoint_tests/configs/sparc-hello-save-checkpoint.py +++ b/tests/gem5/checkpoint_tests/configs/sparc-hello-save-checkpoint.py @@ -32,15 +32,16 @@ with SPARC ISA. """ import argparse -from gem5.isas import ISA -from gem5.utils.requires import requires -from gem5.resources.resource import obtain_resource -from gem5.components.cachehierarchies.classic.no_cache import NoCache + from gem5.components.boards.simple_board import SimpleBoard -from gem5.components.processors.simple_processor import SimpleProcessor -from gem5.simulate.simulator import Simulator +from gem5.components.cachehierarchies.classic.no_cache import NoCache from gem5.components.memory import SingleChannelDDR3_1600 from gem5.components.processors.cpu_types import CPUTypes +from gem5.components.processors.simple_processor import SimpleProcessor +from gem5.isas import ISA +from gem5.resources.resource import obtain_resource +from gem5.simulate.simulator import Simulator +from gem5.utils.requires import requires parser = argparse.ArgumentParser() diff --git a/tests/gem5/checkpoint_tests/configs/x86-fs-restore-checkpoint.py b/tests/gem5/checkpoint_tests/configs/x86-fs-restore-checkpoint.py index 0a3264d576..f2909b36f6 100644 --- a/tests/gem5/checkpoint_tests/configs/x86-fs-restore-checkpoint.py +++ b/tests/gem5/checkpoint_tests/configs/x86-fs-restore-checkpoint.py @@ -34,16 +34,19 @@ This configuration serves as a test of restoring a checkpoint with X86 ISA in fs """ from gem5.components.boards.x86_board import X86Board -from gem5.components.memory import SingleChannelDDR3_1600 -from gem5.components.processors.simple_processor import SimpleProcessor from gem5.components.cachehierarchies.classic.private_l1_private_l2_cache_hierarchy import ( PrivateL1PrivateL2CacheHierarchy, ) +from gem5.components.memory import SingleChannelDDR3_1600 from gem5.components.processors.cpu_types import CPUTypes +from gem5.components.processors.simple_processor import SimpleProcessor from gem5.isas import ISA -from gem5.utils.requires import requires -from gem5.resources.resource import obtain_resource, CheckpointResource +from gem5.resources.resource import ( + CheckpointResource, + obtain_resource, +) from gem5.simulate.simulator import Simulator +from gem5.utils.requires import requires # Run a check to ensure the right version of gem5 is being used. requires(isa_required=ISA.X86) diff --git a/tests/gem5/checkpoint_tests/configs/x86-fs-save-checkpoint.py b/tests/gem5/checkpoint_tests/configs/x86-fs-save-checkpoint.py index 891130af2b..fb800209e0 100644 --- a/tests/gem5/checkpoint_tests/configs/x86-fs-save-checkpoint.py +++ b/tests/gem5/checkpoint_tests/configs/x86-fs-save-checkpoint.py @@ -32,17 +32,18 @@ with X86 ISA in fs mode. """ import argparse + from gem5.components.boards.x86_board import X86Board -from gem5.components.memory import SingleChannelDDR3_1600 -from gem5.components.processors.simple_processor import SimpleProcessor from gem5.components.cachehierarchies.classic.private_l1_private_l2_cache_hierarchy import ( PrivateL1PrivateL2CacheHierarchy, ) +from gem5.components.memory import SingleChannelDDR3_1600 from gem5.components.processors.cpu_types import CPUTypes +from gem5.components.processors.simple_processor import SimpleProcessor from gem5.isas import ISA -from gem5.utils.requires import requires from gem5.resources.resource import obtain_resource from gem5.simulate.simulator import Simulator +from gem5.utils.requires import requires parser = argparse.ArgumentParser() diff --git a/tests/gem5/checkpoint_tests/configs/x86-hello-restore-checkpoint.py b/tests/gem5/checkpoint_tests/configs/x86-hello-restore-checkpoint.py index c60675eb24..5a36a01e35 100644 --- a/tests/gem5/checkpoint_tests/configs/x86-hello-restore-checkpoint.py +++ b/tests/gem5/checkpoint_tests/configs/x86-hello-restore-checkpoint.py @@ -33,18 +33,20 @@ runs the rest of "x86-hello64-static" binary simulation. This configuration serves as a test of restoring a checkpoint with X86 ISA. """ -from gem5.isas import ISA -from gem5.utils.requires import requires -from gem5.resources.resource import obtain_resource, CheckpointResource +from gem5.components.boards.simple_board import SimpleBoard from gem5.components.cachehierarchies.classic.private_l1_cache_hierarchy import ( PrivateL1CacheHierarchy, ) -from gem5.components.boards.simple_board import SimpleBoard -from gem5.components.processors.simple_processor import SimpleProcessor -from gem5.simulate.simulator import Simulator from gem5.components.memory import SingleChannelDDR3_1600 from gem5.components.processors.cpu_types import CPUTypes - +from gem5.components.processors.simple_processor import SimpleProcessor +from gem5.isas import ISA +from gem5.resources.resource import ( + CheckpointResource, + obtain_resource, +) +from gem5.simulate.simulator import Simulator +from gem5.utils.requires import requires requires(isa_required=ISA.X86) diff --git a/tests/gem5/checkpoint_tests/configs/x86-hello-save-checkpoint.py b/tests/gem5/checkpoint_tests/configs/x86-hello-save-checkpoint.py index 5611e795d4..bc35e581df 100644 --- a/tests/gem5/checkpoint_tests/configs/x86-hello-save-checkpoint.py +++ b/tests/gem5/checkpoint_tests/configs/x86-hello-save-checkpoint.py @@ -32,17 +32,18 @@ with X86 ISA. """ import argparse -from gem5.isas import ISA -from gem5.utils.requires import requires -from gem5.resources.resource import obtain_resource + +from gem5.components.boards.simple_board import SimpleBoard from gem5.components.cachehierarchies.classic.private_l1_cache_hierarchy import ( PrivateL1CacheHierarchy, ) -from gem5.components.boards.simple_board import SimpleBoard -from gem5.components.processors.simple_processor import SimpleProcessor -from gem5.simulate.simulator import Simulator from gem5.components.memory import SingleChannelDDR3_1600 from gem5.components.processors.cpu_types import CPUTypes +from gem5.components.processors.simple_processor import SimpleProcessor +from gem5.isas import ISA +from gem5.resources.resource import obtain_resource +from gem5.simulate.simulator import Simulator +from gem5.utils.requires import requires parser = argparse.ArgumentParser() diff --git a/tests/gem5/checkpoint_tests/test-checkpoints.py b/tests/gem5/checkpoint_tests/test-checkpoints.py index 7a6c18d626..f18cf29289 100644 --- a/tests/gem5/checkpoint_tests/test-checkpoints.py +++ b/tests/gem5/checkpoint_tests/test-checkpoints.py @@ -28,9 +28,10 @@ This runs simple tests to ensure the examples in `configs/example/gem5_library` still function. They simply check the simulation completed. """ -from testlib import * -import re import os +import re + +from testlib import * if config.bin_path: resource_path = config.bin_path diff --git a/tests/gem5/cpu_tests/run.py b/tests/gem5/cpu_tests/run.py index 06790c7ea1..2feddb0a51 100644 --- a/tests/gem5/cpu_tests/run.py +++ b/tests/gem5/cpu_tests/run.py @@ -24,8 +24,8 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -import os import argparse +import os import m5 from m5.objects import * diff --git a/tests/gem5/fixture.py b/tests/gem5/fixture.py index 94596f4f5c..f1fcc38dcc 100644 --- a/tests/gem5/fixture.py +++ b/tests/gem5/fixture.py @@ -36,25 +36,34 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -import os -import tempfile -import shutil -import sys -import socket -import threading import gzip - +import os +import shutil +import socket +import sys +import tempfile +import threading import urllib.error import urllib.request +from typing import ( + List, + Optional, +) -from testlib.fixture import Fixture -from testlib.configuration import config, constants -from testlib.helper import log_call, cacheresult, joinpath, absdirpath import testlib.log as log +from testlib.configuration import ( + config, + constants, +) +from testlib.fixture import Fixture +from testlib.helper import ( + absdirpath, + cacheresult, + joinpath, + log_call, +) from testlib.state import Result -from typing import Optional, List - class VariableFixture(Fixture): def __init__(self, value=None, name=None): @@ -342,7 +351,9 @@ class DownloadedProgram(UniqueFixture): urllib.request.urlretrieve(self.url, self.filename) def _getremotetime(self): - import datetime, time + import datetime + import time + import _strptime # Needed for python threading bug u = urllib.request.urlopen(self.url, timeout=10) diff --git a/tests/gem5/fs/linux/arm/configs/arm_generic.py b/tests/gem5/fs/linux/arm/configs/arm_generic.py index ad2ea58597..d5c9b8c501 100644 --- a/tests/gem5/fs/linux/arm/configs/arm_generic.py +++ b/tests/gem5/fs/linux/arm/configs/arm_generic.py @@ -33,19 +33,24 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from abc import ABCMeta, abstractmethod +from abc import ( + ABCMeta, + abstractmethod, +) + import m5 from m5.objects import * from m5.proxy import * m5.util.addToPath("../configs/") -from common import FSConfig from base_caches import * from base_config import * -from common.cores.arm.O3_ARM_v7a import * +from common import ( + FSConfig, + SysPaths, +) from common.Benchmarks import SysConfig - -from common import SysPaths +from common.cores.arm.O3_ARM_v7a import * class ArmSESystemUniprocessor(BaseSESystemUniprocessor): diff --git a/tests/gem5/fs/linux/arm/configs/base_config.py b/tests/gem5/fs/linux/arm/configs/base_config.py index 4bf374b01c..8f7cffb255 100644 --- a/tests/gem5/fs/linux/arm/configs/base_config.py +++ b/tests/gem5/fs/linux/arm/configs/base_config.py @@ -33,15 +33,22 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from abc import ABCMeta, abstractmethod import argparse +from abc import ( + ABCMeta, + abstractmethod, +) + +from base_caches import * +from common import ( + FSConfig, + Options, +) +from ruby import Ruby + import m5 from m5.objects import * from m5.proxy import * -from common import FSConfig -from common import Options -from base_caches import * -from ruby import Ruby _have_kvm_support = "BaseKvmCPU" in globals() diff --git a/tests/gem5/fs/linux/arm/configs/checkpoint.py b/tests/gem5/fs/linux/arm/configs/checkpoint.py index f1b8a1bf72..6f57e3dc91 100644 --- a/tests/gem5/fs/linux/arm/configs/checkpoint.py +++ b/tests/gem5/fs/linux/arm/configs/checkpoint.py @@ -33,9 +33,9 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from multiprocessing import Process -import sys import os +import sys +from multiprocessing import Process import m5 diff --git a/tests/gem5/fs/linux/arm/configs/realview-minor-dual.py b/tests/gem5/fs/linux/arm/configs/realview-minor-dual.py index c6b4e45e9d..08f2be87dc 100644 --- a/tests/gem5/fs/linux/arm/configs/realview-minor-dual.py +++ b/tests/gem5/fs/linux/arm/configs/realview-minor-dual.py @@ -33,9 +33,10 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from m5.objects import * from arm_generic import * +from m5.objects import * + root = LinuxArmFSSystem( aarch64_kernel=False, machine_type="VExpress_GEM5_V1", diff --git a/tests/gem5/fs/linux/arm/configs/realview-minor.py b/tests/gem5/fs/linux/arm/configs/realview-minor.py index a6351628fd..108b5ac500 100644 --- a/tests/gem5/fs/linux/arm/configs/realview-minor.py +++ b/tests/gem5/fs/linux/arm/configs/realview-minor.py @@ -33,9 +33,10 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from m5.objects import * from arm_generic import * +from m5.objects import * + root = LinuxArmFSSystemUniprocessor( aarch64_kernel=False, machine_type="VExpress_GEM5_V1", diff --git a/tests/gem5/fs/linux/arm/configs/realview-o3-checker.py b/tests/gem5/fs/linux/arm/configs/realview-o3-checker.py index 89e5c66fd3..5f0ab44f9f 100644 --- a/tests/gem5/fs/linux/arm/configs/realview-o3-checker.py +++ b/tests/gem5/fs/linux/arm/configs/realview-o3-checker.py @@ -33,10 +33,11 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from m5.objects import * from arm_generic import * from common.cores.arm.O3_ARM_v7a import O3_ARM_v7a_3 +from m5.objects import * + root = LinuxArmFSSystemUniprocessor( aarch64_kernel=False, machine_type="VExpress_GEM5_V1", diff --git a/tests/gem5/fs/linux/arm/configs/realview-o3-dual.py b/tests/gem5/fs/linux/arm/configs/realview-o3-dual.py index f4326dbda1..cebd29e998 100644 --- a/tests/gem5/fs/linux/arm/configs/realview-o3-dual.py +++ b/tests/gem5/fs/linux/arm/configs/realview-o3-dual.py @@ -33,10 +33,11 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from m5.objects import * from arm_generic import * from common.cores.arm.O3_ARM_v7a import O3_ARM_v7a_3 +from m5.objects import * + root = LinuxArmFSSystem( aarch64_kernel=False, machine_type="VExpress_GEM5_V1", diff --git a/tests/gem5/fs/linux/arm/configs/realview-o3.py b/tests/gem5/fs/linux/arm/configs/realview-o3.py index 6a1b757300..9b6494e04a 100644 --- a/tests/gem5/fs/linux/arm/configs/realview-o3.py +++ b/tests/gem5/fs/linux/arm/configs/realview-o3.py @@ -33,10 +33,11 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from m5.objects import * from arm_generic import * from common.cores.arm.O3_ARM_v7a import O3_ARM_v7a_3 +from m5.objects import * + root = LinuxArmFSSystemUniprocessor( aarch64_kernel=False, machine_type="VExpress_GEM5_V1", diff --git a/tests/gem5/fs/linux/arm/configs/realview-simple-atomic-checkpoint.py b/tests/gem5/fs/linux/arm/configs/realview-simple-atomic-checkpoint.py index a60fd96b27..b437ba21cc 100644 --- a/tests/gem5/fs/linux/arm/configs/realview-simple-atomic-checkpoint.py +++ b/tests/gem5/fs/linux/arm/configs/realview-simple-atomic-checkpoint.py @@ -35,9 +35,10 @@ import functools -from m5.objects import * -from arm_generic import * import checkpoint +from arm_generic import * + +from m5.objects import * root = LinuxArmFSSystemUniprocessor( aarch64_kernel=False, diff --git a/tests/gem5/fs/linux/arm/configs/realview-simple-atomic-dual.py b/tests/gem5/fs/linux/arm/configs/realview-simple-atomic-dual.py index c02f8727ea..0f588bb003 100644 --- a/tests/gem5/fs/linux/arm/configs/realview-simple-atomic-dual.py +++ b/tests/gem5/fs/linux/arm/configs/realview-simple-atomic-dual.py @@ -33,9 +33,10 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from m5.objects import * from arm_generic import * +from m5.objects import * + root = LinuxArmFSSystem( aarch64_kernel=False, machine_type="VExpress_GEM5_V1", diff --git a/tests/gem5/fs/linux/arm/configs/realview-simple-atomic.py b/tests/gem5/fs/linux/arm/configs/realview-simple-atomic.py index 9c782ad97a..1e079e3c56 100644 --- a/tests/gem5/fs/linux/arm/configs/realview-simple-atomic.py +++ b/tests/gem5/fs/linux/arm/configs/realview-simple-atomic.py @@ -33,9 +33,10 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from m5.objects import * from arm_generic import * +from m5.objects import * + root = LinuxArmFSSystemUniprocessor( aarch64_kernel=False, machine_type="VExpress_GEM5_V1", diff --git a/tests/gem5/fs/linux/arm/configs/realview-simple-timing-dual-ruby.py b/tests/gem5/fs/linux/arm/configs/realview-simple-timing-dual-ruby.py index 741ededdff..8afbc1a63d 100644 --- a/tests/gem5/fs/linux/arm/configs/realview-simple-timing-dual-ruby.py +++ b/tests/gem5/fs/linux/arm/configs/realview-simple-timing-dual-ruby.py @@ -33,9 +33,10 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from m5.objects import * from arm_generic import * +from m5.objects import * + root = LinuxArmFSSystem( aarch64_kernel=False, machine_type="VExpress_GEM5_V1", diff --git a/tests/gem5/fs/linux/arm/configs/realview-simple-timing-dual.py b/tests/gem5/fs/linux/arm/configs/realview-simple-timing-dual.py index aaea9deb83..c3a76ebe8e 100644 --- a/tests/gem5/fs/linux/arm/configs/realview-simple-timing-dual.py +++ b/tests/gem5/fs/linux/arm/configs/realview-simple-timing-dual.py @@ -33,9 +33,10 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from m5.objects import * from arm_generic import * +from m5.objects import * + root = LinuxArmFSSystem( aarch64_kernel=False, machine_type="VExpress_GEM5_V1", diff --git a/tests/gem5/fs/linux/arm/configs/realview-simple-timing-ruby.py b/tests/gem5/fs/linux/arm/configs/realview-simple-timing-ruby.py index fcca94361e..a99cec184b 100644 --- a/tests/gem5/fs/linux/arm/configs/realview-simple-timing-ruby.py +++ b/tests/gem5/fs/linux/arm/configs/realview-simple-timing-ruby.py @@ -33,9 +33,10 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from m5.objects import * from arm_generic import * +from m5.objects import * + root = LinuxArmFSSystemUniprocessor( aarch64_kernel=False, machine_type="VExpress_GEM5_V1", diff --git a/tests/gem5/fs/linux/arm/configs/realview-simple-timing.py b/tests/gem5/fs/linux/arm/configs/realview-simple-timing.py index 2afbdd0a0e..9f40606292 100644 --- a/tests/gem5/fs/linux/arm/configs/realview-simple-timing.py +++ b/tests/gem5/fs/linux/arm/configs/realview-simple-timing.py @@ -33,9 +33,10 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from m5.objects import * from arm_generic import * +from m5.objects import * + root = LinuxArmFSSystemUniprocessor( aarch64_kernel=False, machine_type="VExpress_GEM5_V1", diff --git a/tests/gem5/fs/linux/arm/configs/realview-switcheroo-atomic.py b/tests/gem5/fs/linux/arm/configs/realview-switcheroo-atomic.py index d2f2100f52..c7b8044246 100644 --- a/tests/gem5/fs/linux/arm/configs/realview-switcheroo-atomic.py +++ b/tests/gem5/fs/linux/arm/configs/realview-switcheroo-atomic.py @@ -33,9 +33,10 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from m5.objects import * -from arm_generic import * import switcheroo +from arm_generic import * + +from m5.objects import * root = LinuxArmFSSwitcheroo( mem_class=SimpleMemory, diff --git a/tests/gem5/fs/linux/arm/configs/realview-switcheroo-full.py b/tests/gem5/fs/linux/arm/configs/realview-switcheroo-full.py index 6ed99a3772..2a468e63b6 100644 --- a/tests/gem5/fs/linux/arm/configs/realview-switcheroo-full.py +++ b/tests/gem5/fs/linux/arm/configs/realview-switcheroo-full.py @@ -33,9 +33,10 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from m5.objects import * -from arm_generic import * import switcheroo +from arm_generic import * + +from m5.objects import * root = LinuxArmFSSwitcheroo( machine_type="VExpress_GEM5_V1", diff --git a/tests/gem5/fs/linux/arm/configs/realview-switcheroo-noncaching-timing.py b/tests/gem5/fs/linux/arm/configs/realview-switcheroo-noncaching-timing.py index cc77f440ab..8afda7b49a 100644 --- a/tests/gem5/fs/linux/arm/configs/realview-switcheroo-noncaching-timing.py +++ b/tests/gem5/fs/linux/arm/configs/realview-switcheroo-noncaching-timing.py @@ -33,9 +33,10 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from m5.objects import * -from arm_generic import * import switcheroo +from arm_generic import * + +from m5.objects import * root = LinuxArmFSSwitcheroo( cpu_classes=(ArmNonCachingSimpleCPU, ArmTimingSimpleCPU) diff --git a/tests/gem5/fs/linux/arm/configs/realview-switcheroo-o3.py b/tests/gem5/fs/linux/arm/configs/realview-switcheroo-o3.py index 4fca57ea1e..e0b1a30c43 100644 --- a/tests/gem5/fs/linux/arm/configs/realview-switcheroo-o3.py +++ b/tests/gem5/fs/linux/arm/configs/realview-switcheroo-o3.py @@ -33,9 +33,10 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from m5.objects import * -from arm_generic import * import switcheroo +from arm_generic import * + +from m5.objects import * root = LinuxArmFSSwitcheroo( aarch64_kernel=False, diff --git a/tests/gem5/fs/linux/arm/configs/realview-switcheroo-timing.py b/tests/gem5/fs/linux/arm/configs/realview-switcheroo-timing.py index 5157da6dac..a160e809a1 100644 --- a/tests/gem5/fs/linux/arm/configs/realview-switcheroo-timing.py +++ b/tests/gem5/fs/linux/arm/configs/realview-switcheroo-timing.py @@ -33,9 +33,10 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from m5.objects import * -from arm_generic import * import switcheroo +from arm_generic import * + +from m5.objects import * root = LinuxArmFSSwitcheroo( mem_class=DDR3_1600_8x8, diff --git a/tests/gem5/fs/linux/arm/configs/realview64-kvm-dual.py b/tests/gem5/fs/linux/arm/configs/realview64-kvm-dual.py index e64ba2fbf5..91c0ebb0a2 100644 --- a/tests/gem5/fs/linux/arm/configs/realview64-kvm-dual.py +++ b/tests/gem5/fs/linux/arm/configs/realview64-kvm-dual.py @@ -33,9 +33,13 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from m5.objects import * from arm_generic import * -from m5.ticks import fixGlobalFrequency, fromSeconds + +from m5.objects import * +from m5.ticks import ( + fixGlobalFrequency, + fromSeconds, +) root = LinuxArmFSSystem( mem_mode="atomic_noncaching", diff --git a/tests/gem5/fs/linux/arm/configs/realview64-kvm.py b/tests/gem5/fs/linux/arm/configs/realview64-kvm.py index 8fa6997da8..ac7f7134fa 100644 --- a/tests/gem5/fs/linux/arm/configs/realview64-kvm.py +++ b/tests/gem5/fs/linux/arm/configs/realview64-kvm.py @@ -33,9 +33,10 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from m5.objects import * from arm_generic import * +from m5.objects import * + root = LinuxArmFSSystemUniprocessor( mem_mode="atomic_noncaching", machine_type="VExpress_GEM5_V1", diff --git a/tests/gem5/fs/linux/arm/configs/realview64-minor-dual.py b/tests/gem5/fs/linux/arm/configs/realview64-minor-dual.py index aed5d83c71..772ad986cf 100644 --- a/tests/gem5/fs/linux/arm/configs/realview64-minor-dual.py +++ b/tests/gem5/fs/linux/arm/configs/realview64-minor-dual.py @@ -33,9 +33,10 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from m5.objects import * from arm_generic import * +from m5.objects import * + root = LinuxArmFSSystem( mem_mode="timing", mem_class=DDR3_1600_8x8, diff --git a/tests/gem5/fs/linux/arm/configs/realview64-minor.py b/tests/gem5/fs/linux/arm/configs/realview64-minor.py index 7bad3c52ed..630a94bab0 100644 --- a/tests/gem5/fs/linux/arm/configs/realview64-minor.py +++ b/tests/gem5/fs/linux/arm/configs/realview64-minor.py @@ -33,9 +33,10 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from m5.objects import * from arm_generic import * +from m5.objects import * + root = LinuxArmFSSystemUniprocessor( mem_mode="timing", mem_class=DDR3_1600_8x8, cpu_class=ArmMinorCPU ).create_root() diff --git a/tests/gem5/fs/linux/arm/configs/realview64-o3-checker.py b/tests/gem5/fs/linux/arm/configs/realview64-o3-checker.py index 00d9a5773a..0c32aa6915 100644 --- a/tests/gem5/fs/linux/arm/configs/realview64-o3-checker.py +++ b/tests/gem5/fs/linux/arm/configs/realview64-o3-checker.py @@ -33,10 +33,11 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from m5.objects import * from arm_generic import * from common.cores.arm.O3_ARM_v7a import O3_ARM_v7a_3 +from m5.objects import * + root = LinuxArmFSSystemUniprocessor( mem_mode="timing", machine_type="VExpress_GEM5_V1", diff --git a/tests/gem5/fs/linux/arm/configs/realview64-o3-dual-ruby.py b/tests/gem5/fs/linux/arm/configs/realview64-o3-dual-ruby.py index a4bffe902e..db8edf3c4f 100644 --- a/tests/gem5/fs/linux/arm/configs/realview64-o3-dual-ruby.py +++ b/tests/gem5/fs/linux/arm/configs/realview64-o3-dual-ruby.py @@ -33,9 +33,10 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from m5.objects import * from arm_generic import * +from m5.objects import * + root = LinuxArmFSSystem( mem_mode="timing", mem_class=DDR3_1600_8x8, diff --git a/tests/gem5/fs/linux/arm/configs/realview64-o3-dual.py b/tests/gem5/fs/linux/arm/configs/realview64-o3-dual.py index 75fe10e316..1263035764 100644 --- a/tests/gem5/fs/linux/arm/configs/realview64-o3-dual.py +++ b/tests/gem5/fs/linux/arm/configs/realview64-o3-dual.py @@ -33,10 +33,11 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from m5.objects import * from arm_generic import * from common.cores.arm.O3_ARM_v7a import O3_ARM_v7a_3 +from m5.objects import * + root = LinuxArmFSSystem( mem_mode="timing", mem_class=DDR3_1600_8x8, diff --git a/tests/gem5/fs/linux/arm/configs/realview64-o3.py b/tests/gem5/fs/linux/arm/configs/realview64-o3.py index c8ae8ec5af..1c7c3b09fc 100644 --- a/tests/gem5/fs/linux/arm/configs/realview64-o3.py +++ b/tests/gem5/fs/linux/arm/configs/realview64-o3.py @@ -33,10 +33,11 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from m5.objects import * from arm_generic import * from common.cores.arm.O3_ARM_v7a import O3_ARM_v7a_3 +from m5.objects import * + root = LinuxArmFSSystemUniprocessor( mem_mode="timing", mem_class=DDR3_1600_8x8, cpu_class=O3_ARM_v7a_3 ).create_root() diff --git a/tests/gem5/fs/linux/arm/configs/realview64-simple-atomic-checkpoint.py b/tests/gem5/fs/linux/arm/configs/realview64-simple-atomic-checkpoint.py index fa73a0ee6e..ebf9ad7879 100644 --- a/tests/gem5/fs/linux/arm/configs/realview64-simple-atomic-checkpoint.py +++ b/tests/gem5/fs/linux/arm/configs/realview64-simple-atomic-checkpoint.py @@ -35,9 +35,10 @@ import functools -from m5.objects import * -from arm_generic import * import checkpoint +from arm_generic import * + +from m5.objects import * root = LinuxArmFSSystemUniprocessor( mem_mode="atomic", mem_class=SimpleMemory, cpu_class=ArmAtomicSimpleCPU diff --git a/tests/gem5/fs/linux/arm/configs/realview64-simple-atomic-dual.py b/tests/gem5/fs/linux/arm/configs/realview64-simple-atomic-dual.py index 19cf751603..c208816dea 100644 --- a/tests/gem5/fs/linux/arm/configs/realview64-simple-atomic-dual.py +++ b/tests/gem5/fs/linux/arm/configs/realview64-simple-atomic-dual.py @@ -33,9 +33,10 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from m5.objects import * from arm_generic import * +from m5.objects import * + root = LinuxArmFSSystem( mem_mode="atomic", mem_class=SimpleMemory, diff --git a/tests/gem5/fs/linux/arm/configs/realview64-simple-atomic.py b/tests/gem5/fs/linux/arm/configs/realview64-simple-atomic.py index 299dd7b0a7..2595e88311 100644 --- a/tests/gem5/fs/linux/arm/configs/realview64-simple-atomic.py +++ b/tests/gem5/fs/linux/arm/configs/realview64-simple-atomic.py @@ -33,9 +33,10 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from m5.objects import * from arm_generic import * +from m5.objects import * + root = LinuxArmFSSystemUniprocessor( mem_mode="atomic", mem_class=SimpleMemory, cpu_class=ArmAtomicSimpleCPU ).create_root() diff --git a/tests/gem5/fs/linux/arm/configs/realview64-simple-timing-dual-ruby.py b/tests/gem5/fs/linux/arm/configs/realview64-simple-timing-dual-ruby.py index 96ad96355c..8b37b1a2a2 100644 --- a/tests/gem5/fs/linux/arm/configs/realview64-simple-timing-dual-ruby.py +++ b/tests/gem5/fs/linux/arm/configs/realview64-simple-timing-dual-ruby.py @@ -33,9 +33,10 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from m5.objects import * from arm_generic import * +from m5.objects import * + root = LinuxArmFSSystem( mem_mode="timing", mem_class=DDR3_1600_8x8, diff --git a/tests/gem5/fs/linux/arm/configs/realview64-simple-timing-dual.py b/tests/gem5/fs/linux/arm/configs/realview64-simple-timing-dual.py index 8b62cd3414..e6f1043b84 100644 --- a/tests/gem5/fs/linux/arm/configs/realview64-simple-timing-dual.py +++ b/tests/gem5/fs/linux/arm/configs/realview64-simple-timing-dual.py @@ -33,9 +33,10 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from m5.objects import * from arm_generic import * +from m5.objects import * + root = LinuxArmFSSystem( mem_mode="timing", mem_class=DDR3_1600_8x8, diff --git a/tests/gem5/fs/linux/arm/configs/realview64-simple-timing-ruby.py b/tests/gem5/fs/linux/arm/configs/realview64-simple-timing-ruby.py index f6024537a2..aa8fe14b4c 100644 --- a/tests/gem5/fs/linux/arm/configs/realview64-simple-timing-ruby.py +++ b/tests/gem5/fs/linux/arm/configs/realview64-simple-timing-ruby.py @@ -33,9 +33,10 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from m5.objects import * from arm_generic import * +from m5.objects import * + root = LinuxArmFSSystemUniprocessor( mem_mode="timing", mem_class=DDR3_1600_8x8, diff --git a/tests/gem5/fs/linux/arm/configs/realview64-simple-timing.py b/tests/gem5/fs/linux/arm/configs/realview64-simple-timing.py index 6897f3b1ad..7b0e7ce137 100644 --- a/tests/gem5/fs/linux/arm/configs/realview64-simple-timing.py +++ b/tests/gem5/fs/linux/arm/configs/realview64-simple-timing.py @@ -33,9 +33,10 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from m5.objects import * from arm_generic import * +from m5.objects import * + root = LinuxArmFSSystemUniprocessor( mem_mode="timing", mem_class=DDR3_1600_8x8, cpu_class=ArmTimingSimpleCPU ).create_root() diff --git a/tests/gem5/fs/linux/arm/configs/realview64-switcheroo-atomic.py b/tests/gem5/fs/linux/arm/configs/realview64-switcheroo-atomic.py index c2f67f0553..37c8d1e77d 100644 --- a/tests/gem5/fs/linux/arm/configs/realview64-switcheroo-atomic.py +++ b/tests/gem5/fs/linux/arm/configs/realview64-switcheroo-atomic.py @@ -33,9 +33,10 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from m5.objects import * -from arm_generic import * import switcheroo +from arm_generic import * + +from m5.objects import * root = LinuxArmFSSwitcheroo( mem_class=SimpleMemory, diff --git a/tests/gem5/fs/linux/arm/configs/realview64-switcheroo-full.py b/tests/gem5/fs/linux/arm/configs/realview64-switcheroo-full.py index 020957875d..0cb96586dc 100644 --- a/tests/gem5/fs/linux/arm/configs/realview64-switcheroo-full.py +++ b/tests/gem5/fs/linux/arm/configs/realview64-switcheroo-full.py @@ -33,9 +33,10 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from m5.objects import * -from arm_generic import * import switcheroo +from arm_generic import * + +from m5.objects import * root = LinuxArmFSSwitcheroo( mem_class=DDR3_1600_8x8, diff --git a/tests/gem5/fs/linux/arm/configs/realview64-switcheroo-o3.py b/tests/gem5/fs/linux/arm/configs/realview64-switcheroo-o3.py index f899337a8f..6da3b59eda 100644 --- a/tests/gem5/fs/linux/arm/configs/realview64-switcheroo-o3.py +++ b/tests/gem5/fs/linux/arm/configs/realview64-switcheroo-o3.py @@ -33,9 +33,10 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from m5.objects import * -from arm_generic import * import switcheroo +from arm_generic import * + +from m5.objects import * root = LinuxArmFSSwitcheroo( mem_class=DDR3_1600_8x8, cpu_classes=(ArmO3CPU, ArmO3CPU) diff --git a/tests/gem5/fs/linux/arm/configs/realview64-switcheroo-timing.py b/tests/gem5/fs/linux/arm/configs/realview64-switcheroo-timing.py index 4ccce5d953..8ac0a78335 100644 --- a/tests/gem5/fs/linux/arm/configs/realview64-switcheroo-timing.py +++ b/tests/gem5/fs/linux/arm/configs/realview64-switcheroo-timing.py @@ -33,9 +33,10 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from m5.objects import * -from arm_generic import * import switcheroo +from arm_generic import * + +from m5.objects import * root = LinuxArmFSSwitcheroo( mem_class=DDR3_1600_8x8, diff --git a/tests/gem5/fs/linux/arm/configs/switcheroo.py b/tests/gem5/fs/linux/arm/configs/switcheroo.py index 3c39fbf96a..87ab6f4b2b 100644 --- a/tests/gem5/fs/linux/arm/configs/switcheroo.py +++ b/tests/gem5/fs/linux/arm/configs/switcheroo.py @@ -34,9 +34,10 @@ # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. import m5 -import _m5 from m5.objects import * +import _m5 + m5.util.addToPath("../configs/") from base_caches import * diff --git a/tests/gem5/fs/linux/arm/run.py b/tests/gem5/fs/linux/arm/run.py index e677297cad..90349b33cd 100644 --- a/tests/gem5/fs/linux/arm/run.py +++ b/tests/gem5/fs/linux/arm/run.py @@ -36,9 +36,9 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -import sys import os import os.path +import sys from os.path import join as joinpath import m5 diff --git a/tests/gem5/fs/linux/arm/test.py b/tests/gem5/fs/linux/arm/test.py index f503f7ae02..aa5961bcb4 100644 --- a/tests/gem5/fs/linux/arm/test.py +++ b/tests/gem5/fs/linux/arm/test.py @@ -37,12 +37,11 @@ Arm FS simulation tests """ +import re from os.path import join as joinpath from testlib import * -import re - arm_fs_kvm_tests = ["realview64-kvm", "realview64-kvm-dual"] arm_fs_quick_tests = [ diff --git a/tests/gem5/gem5_library_example_tests/test_gem5_library_examples.py b/tests/gem5/gem5_library_example_tests/test_gem5_library_examples.py index 512e2c7cc2..5ffb62873d 100644 --- a/tests/gem5/gem5_library_example_tests/test_gem5_library_examples.py +++ b/tests/gem5/gem5_library_example_tests/test_gem5_library_examples.py @@ -28,10 +28,11 @@ This runs simple tests to ensure the examples in `configs/example/gem5_library` still function. They simply check the simulation completed. """ +import os +import re + from testlib import * from testlib.log import * -import re -import os if config.bin_path: resource_path = config.bin_path diff --git a/tests/gem5/gem5_resources/configs/download_check.py b/tests/gem5/gem5_resources/configs/download_check.py index 4d5f9ac69c..f051638000 100644 --- a/tests/gem5/gem5_resources/configs/download_check.py +++ b/tests/gem5/gem5_resources/configs/download_check.py @@ -24,20 +24,18 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from gem5.resources.downloader import ( - list_resources, - get_resource, -) - -from gem5.resources.client import get_resource_json_obj - -from gem5.resources.md5_utils import md5 - +import argparse import os import shutil -import argparse from pathlib import Path +from gem5.resources.client import get_resource_json_obj +from gem5.resources.downloader import ( + get_resource, + list_resources, +) +from gem5.resources.md5_utils import md5 + parser = argparse.ArgumentParser( description="A script that will checks that input resource IDs will " "download a resource and that resources md5 value is correct. " diff --git a/tests/gem5/insttest_se/configs/simple_binary_run.py b/tests/gem5/insttest_se/configs/simple_binary_run.py index 1a0f819a8f..d48fdfc7ea 100644 --- a/tests/gem5/insttest_se/configs/simple_binary_run.py +++ b/tests/gem5/insttest_se/configs/simple_binary_run.py @@ -31,27 +31,31 @@ The system has no cache heirarchy and is as "bare-bones" as you can get in gem5 while still being functinal. """ -from gem5.resources.resource import Resource -from gem5.components.processors.cpu_types import ( - get_cpu_types_str_set, - get_cpu_type_from_str, -) -from gem5.components.memory import SingleChannelDDR3_1600 -from gem5.components.boards.simple_board import SimpleBoard -from gem5.components.cachehierarchies.classic.no_cache import NoCache -from gem5.components.processors.simple_processor import SimpleProcessor -from gem5.components.processors.base_cpu_core import BaseCPUCore -from gem5.components.processors.base_cpu_processor import BaseCPUProcessor -from gem5.components.processors.simple_core import SimpleCore -from gem5.components.boards.mem_mode import MemMode -from gem5.components.processors.cpu_types import CPUTypes -from gem5.simulate.simulator import Simulator -from gem5.isas import get_isa_from_str, get_isas_str_set, ISA +import argparse +import importlib from m5.util import fatal -import argparse -import importlib +from gem5.components.boards.mem_mode import MemMode +from gem5.components.boards.simple_board import SimpleBoard +from gem5.components.cachehierarchies.classic.no_cache import NoCache +from gem5.components.memory import SingleChannelDDR3_1600 +from gem5.components.processors.base_cpu_core import BaseCPUCore +from gem5.components.processors.base_cpu_processor import BaseCPUProcessor +from gem5.components.processors.cpu_types import ( + CPUTypes, + get_cpu_type_from_str, + get_cpu_types_str_set, +) +from gem5.components.processors.simple_core import SimpleCore +from gem5.components.processors.simple_processor import SimpleProcessor +from gem5.isas import ( + ISA, + get_isa_from_str, + get_isas_str_set, +) +from gem5.resources.resource import Resource +from gem5.simulate.simulator import Simulator cpu_types_string_map = { CPUTypes.ATOMIC: "AtomicSimpleCPU", diff --git a/tests/gem5/kvm_fork_tests/configs/boot_kvm_fork_run.py b/tests/gem5/kvm_fork_tests/configs/boot_kvm_fork_run.py index cb6d1b44e1..3dc6119454 100644 --- a/tests/gem5/kvm_fork_tests/configs/boot_kvm_fork_run.py +++ b/tests/gem5/kvm_fork_tests/configs/boot_kvm_fork_run.py @@ -43,18 +43,18 @@ from textwrap import dedent import m5 from m5.objects import Root -from gem5.components.boards.x86_board import X86Board from gem5.coherence_protocol import CoherenceProtocol -from gem5.isas import ISA +from gem5.components.boards.x86_board import X86Board from gem5.components.memory import SingleChannelDDR3_1600 from gem5.components.processors.cpu_types import ( CPUTypes, - get_cpu_types_str_set, get_cpu_type_from_str, + get_cpu_types_str_set, ) from gem5.components.processors.simple_switchable_processor import ( SimpleSwitchableProcessor, ) +from gem5.isas import ISA from gem5.resources.resource import obtain_resource from gem5.runtime import get_runtime_coherence_protocol from gem5.utils.requires import requires diff --git a/tests/gem5/kvm_switch_tests/configs/boot_kvm_switch_exit.py b/tests/gem5/kvm_switch_tests/configs/boot_kvm_switch_exit.py index 2d21261161..c5b59b7f4e 100644 --- a/tests/gem5/kvm_switch_tests/configs/boot_kvm_switch_exit.py +++ b/tests/gem5/kvm_switch_tests/configs/boot_kvm_switch_exit.py @@ -33,22 +33,22 @@ import argparse import m5 from m5.objects import Root -from gem5.isas import ISA -from gem5.components.boards.x86_board import X86Board from gem5.coherence_protocol import CoherenceProtocol +from gem5.components.boards.x86_board import X86Board from gem5.components.memory import SingleChannelDDR3_1600 from gem5.components.processors.cpu_types import ( CPUTypes, - get_cpu_types_str_set, get_cpu_type_from_str, + get_cpu_types_str_set, ) from gem5.components.processors.simple_switchable_processor import ( SimpleSwitchableProcessor, ) +from gem5.isas import ISA from gem5.resources.resource import obtain_resource from gem5.runtime import get_runtime_coherence_protocol -from gem5.simulate.simulator import Simulator from gem5.simulate.exit_event import ExitEvent +from gem5.simulate.simulator import Simulator from gem5.utils.requires import requires parser = argparse.ArgumentParser( diff --git a/tests/gem5/m5_util/configs/simple_binary_run.py b/tests/gem5/m5_util/configs/simple_binary_run.py index ab12156ae2..b6f52bcd34 100644 --- a/tests/gem5/m5_util/configs/simple_binary_run.py +++ b/tests/gem5/m5_util/configs/simple_binary_run.py @@ -31,28 +31,31 @@ The system has no cache heirarchy and is as "bare-bones" as you can get in gem5 while still being functinal. """ -from gem5.resources.resource import Resource -from gem5.components.processors.cpu_types import ( - get_cpu_types_str_set, - get_cpu_type_from_str, -) -from gem5.components.memory import SingleChannelDDR3_1600 -from gem5.components.boards.simple_board import SimpleBoard -from gem5.components.cachehierarchies.classic.no_cache import NoCache -from gem5.components.processors.simple_processor import SimpleProcessor -from gem5.components.processors.base_cpu_core import BaseCPUCore -from gem5.components.processors.base_cpu_processor import BaseCPUProcessor -from gem5.components.processors.simple_core import SimpleCore -from gem5.components.boards.mem_mode import MemMode -from gem5.components.processors.cpu_types import CPUTypes -from gem5.simulate.simulator import Simulator -from gem5.isas import get_isa_from_str, get_isas_str_set, ISA - -from m5.util import fatal - import argparse import importlib +from m5.util import fatal + +from gem5.components.boards.mem_mode import MemMode +from gem5.components.boards.simple_board import SimpleBoard +from gem5.components.cachehierarchies.classic.no_cache import NoCache +from gem5.components.memory import SingleChannelDDR3_1600 +from gem5.components.processors.base_cpu_core import BaseCPUCore +from gem5.components.processors.base_cpu_processor import BaseCPUProcessor +from gem5.components.processors.cpu_types import ( + CPUTypes, + get_cpu_type_from_str, + get_cpu_types_str_set, +) +from gem5.components.processors.simple_core import SimpleCore +from gem5.components.processors.simple_processor import SimpleProcessor +from gem5.isas import ( + ISA, + get_isa_from_str, + get_isas_str_set, +) +from gem5.resources.resource import Resource +from gem5.simulate.simulator import Simulator parser = argparse.ArgumentParser( description="A gem5 script for running simple binaries in SE mode." diff --git a/tests/gem5/m5_util/test_exit.py b/tests/gem5/m5_util/test_exit.py index 214a20ada9..9bb4238a57 100644 --- a/tests/gem5/m5_util/test_exit.py +++ b/tests/gem5/m5_util/test_exit.py @@ -40,6 +40,7 @@ Test file for the util m5 exit assembly instruction. """ import re + from testlib import * m5_exit_regex = re.compile( diff --git a/tests/gem5/m5threads_test_atomic/atomic_system.py b/tests/gem5/m5threads_test_atomic/atomic_system.py index b7bd67db10..62a698a025 100644 --- a/tests/gem5/m5threads_test_atomic/atomic_system.py +++ b/tests/gem5/m5threads_test_atomic/atomic_system.py @@ -24,11 +24,13 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +import argparse +import sys + +from caches import * + import m5 from m5.objects import * -from caches import * -import sys -import argparse parser = argparse.ArgumentParser(description="m5threads atomic tester") parser.add_argument("--cpu-type", default="DerivO3CPU") diff --git a/tests/gem5/m5threads_test_atomic/caches.py b/tests/gem5/m5threads_test_atomic/caches.py index 29de48b065..e9f112013b 100755 --- a/tests/gem5/m5threads_test_atomic/caches.py +++ b/tests/gem5/m5threads_test_atomic/caches.py @@ -31,8 +31,17 @@ gem5 configuration script. """ import m5 -from m5.objects import Cache, L2XBar, StridePrefetcher, SubSystem -from m5.params import AddrRange, AllMemory, MemorySize +from m5.objects import ( + Cache, + L2XBar, + StridePrefetcher, + SubSystem, +) +from m5.params import ( + AddrRange, + AllMemory, + MemorySize, +) from m5.util.convert import toMemorySize # Some specific options for caches diff --git a/tests/gem5/memory/simple-run.py b/tests/gem5/memory/simple-run.py index ec5b2d3385..910b632b11 100644 --- a/tests/gem5/memory/simple-run.py +++ b/tests/gem5/memory/simple-run.py @@ -33,11 +33,11 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +import argparse + import m5 from m5.objects import * -import argparse - parser = argparse.ArgumentParser(description="Simple memory tester") parser.add_argument("--bandwidth", default=None) parser.add_argument("--latency", default=None) diff --git a/tests/gem5/multi_isa/configs/runtime_isa_check.py b/tests/gem5/multi_isa/configs/runtime_isa_check.py index 1076e99335..ffc50ee927 100644 --- a/tests/gem5/multi_isa/configs/runtime_isa_check.py +++ b/tests/gem5/multi_isa/configs/runtime_isa_check.py @@ -29,11 +29,15 @@ This is a very simple script to test the output given by `gem5.runtime.get_runtime_isa` """ -from gem5.runtime import get_runtime_isa -from gem5.isas import ISA, get_isas_str_set, get_isa_from_str - import argparse +from gem5.isas import ( + ISA, + get_isa_from_str, + get_isas_str_set, +) +from gem5.runtime import get_runtime_isa + parser = argparse.ArgumentParser( description="A simple script used to check the output of " "`gem5.runtime.get_runtime_isa`" diff --git a/tests/gem5/multi_isa/configs/supported_isa_check.py b/tests/gem5/multi_isa/configs/supported_isa_check.py index 5f535e76a7..5b6dfc7c8a 100644 --- a/tests/gem5/multi_isa/configs/supported_isa_check.py +++ b/tests/gem5/multi_isa/configs/supported_isa_check.py @@ -29,11 +29,14 @@ This is a very simple script to test the output given by `gem5.runtime.get_supported_isas` """ -from gem5.runtime import get_supported_isas -from gem5.isas import get_isas_str_set, get_isa_from_str - -import os import argparse +import os + +from gem5.isas import ( + get_isa_from_str, + get_isas_str_set, +) +from gem5.runtime import get_supported_isas parser = argparse.ArgumentParser( description="A simple script used to check the output of " diff --git a/tests/gem5/parsec_benchmarks/configs/parsec_disk_run.py b/tests/gem5/parsec_benchmarks/configs/parsec_disk_run.py index 341548729b..92786bb001 100644 --- a/tests/gem5/parsec_benchmarks/configs/parsec_disk_run.py +++ b/tests/gem5/parsec_benchmarks/configs/parsec_disk_run.py @@ -35,27 +35,30 @@ Notes * This will only function for the X86 ISA. """ +import argparse +import time + import m5.stats -from gem5.resources.resource import obtain_resource from gem5.components.boards.x86_board import X86Board from gem5.components.memory import SingleChannelDDR3_1600 +from gem5.components.processors.cpu_types import ( + get_cpu_type_from_str, + get_cpu_types_str_set, +) from gem5.components.processors.simple_switchable_processor import ( SimpleSwitchableProcessor, ) -from gem5.components.processors.cpu_types import ( - get_cpu_types_str_set, - get_cpu_type_from_str, -) from gem5.isas import ISA -from gem5.runtime import get_runtime_isa, get_runtime_coherence_protocol -from gem5.simulate.simulator import Simulator +from gem5.resources.resource import obtain_resource +from gem5.runtime import ( + get_runtime_coherence_protocol, + get_runtime_isa, +) from gem5.simulate.exit_event import ExitEvent +from gem5.simulate.simulator import Simulator from gem5.utils.requires import requires -import time -import argparse - requires(isa_required=ISA.X86) diff --git a/tests/gem5/replacement_policies/configs/cache_hierarchies.py b/tests/gem5/replacement_policies/configs/cache_hierarchies.py index 6177dd4ac9..e6eab320a3 100644 --- a/tests/gem5/replacement_policies/configs/cache_hierarchies.py +++ b/tests/gem5/replacement_policies/configs/cache_hierarchies.py @@ -27,12 +27,13 @@ from typing import Type -from gem5.utils.override import overrides +from m5.objects.ReplacementPolicies import BaseReplacementPolicy + +from gem5.components.boards.abstract_board import AbstractBoard from gem5.components.cachehierarchies.ruby.mi_example_cache_hierarchy import ( MIExampleCacheHierarchy, ) -from gem5.components.boards.abstract_board import AbstractBoard -from m5.objects.ReplacementPolicies import BaseReplacementPolicy +from gem5.utils.override import overrides class ModMIExampleCacheHierarchy(MIExampleCacheHierarchy): diff --git a/tests/gem5/replacement_policies/configs/run_replacement_policy.py b/tests/gem5/replacement_policies/configs/run_replacement_policy.py index ec38bf382f..8f52a061f6 100644 --- a/tests/gem5/replacement_policies/configs/run_replacement_policy.py +++ b/tests/gem5/replacement_policies/configs/run_replacement_policy.py @@ -30,9 +30,9 @@ from importlib.machinery import SourceFileLoader from cache_hierarchies import ModMIExampleCacheHierarchy import m5 - from m5.debug import flags from m5.objects import Root + from gem5.components.boards.test_board import TestBoard from gem5.components.memory.simple import SingleChannelSimpleMemory from gem5.components.processors.complex_generator import ComplexGenerator diff --git a/tests/gem5/replacement_policies/run_replacement_policy.py b/tests/gem5/replacement_policies/run_replacement_policy.py index ec38bf382f..8f52a061f6 100644 --- a/tests/gem5/replacement_policies/run_replacement_policy.py +++ b/tests/gem5/replacement_policies/run_replacement_policy.py @@ -30,9 +30,9 @@ from importlib.machinery import SourceFileLoader from cache_hierarchies import ModMIExampleCacheHierarchy import m5 - from m5.debug import flags from m5.objects import Root + from gem5.components.boards.test_board import TestBoard from gem5.components.memory.simple import SingleChannelSimpleMemory from gem5.components.processors.complex_generator import ComplexGenerator diff --git a/tests/gem5/riscv_boot_tests/configs/riscv_boot_exit_run.py b/tests/gem5/riscv_boot_tests/configs/riscv_boot_exit_run.py index 3726d7de46..0192d3dbff 100644 --- a/tests/gem5/riscv_boot_tests/configs/riscv_boot_exit_run.py +++ b/tests/gem5/riscv_boot_tests/configs/riscv_boot_exit_run.py @@ -33,18 +33,20 @@ Characteristics * Runs exclusively on the RISC-V ISA with the classic caches """ -from gem5.isas import ISA -from gem5.utils.requires import requires -from gem5.resources.resource import Resource -from gem5.components.processors.cpu_types import CPUTypes -from gem5.components.boards.riscv_board import RiscvBoard -from gem5.components.processors.simple_processor import SimpleProcessor -from gem5.simulate.simulator import Simulator -from gem5.resources.resource import obtain_resource - import argparse import importlib +from gem5.components.boards.riscv_board import RiscvBoard +from gem5.components.processors.cpu_types import CPUTypes +from gem5.components.processors.simple_processor import SimpleProcessor +from gem5.isas import ISA +from gem5.resources.resource import ( + Resource, + obtain_resource, +) +from gem5.simulate.simulator import Simulator +from gem5.utils.requires import requires + parser = argparse.ArgumentParser( description="A script to run the RISCV boot exit tests." ) diff --git a/tests/gem5/riscv_boot_tests/test_linux_boot.py b/tests/gem5/riscv_boot_tests/test_linux_boot.py index 43d1c6d69f..bb2c3a4b04 100644 --- a/tests/gem5/riscv_boot_tests/test_linux_boot.py +++ b/tests/gem5/riscv_boot_tests/test_linux_boot.py @@ -25,7 +25,6 @@ # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. import re - from typing import Optional from testlib import * diff --git a/tests/gem5/se_mode/hello_se/configs/simple_binary_run.py b/tests/gem5/se_mode/hello_se/configs/simple_binary_run.py index 19fd0e6b8c..08569f05a0 100644 --- a/tests/gem5/se_mode/hello_se/configs/simple_binary_run.py +++ b/tests/gem5/se_mode/hello_se/configs/simple_binary_run.py @@ -31,27 +31,31 @@ The system has no cache heirarchy and is as "bare-bones" as you can get in gem5 while still being functinal. """ -from gem5.resources.resource import obtain_resource -from gem5.components.processors.cpu_types import ( - get_cpu_types_str_set, - get_cpu_type_from_str, -) -from gem5.components.memory import SingleChannelDDR3_1600 -from gem5.components.boards.simple_board import SimpleBoard -from gem5.components.cachehierarchies.classic.no_cache import NoCache -from gem5.components.processors.simple_processor import SimpleProcessor -from gem5.components.processors.base_cpu_core import BaseCPUCore -from gem5.components.processors.base_cpu_processor import BaseCPUProcessor -from gem5.components.processors.simple_core import SimpleCore -from gem5.components.boards.mem_mode import MemMode -from gem5.components.processors.cpu_types import CPUTypes -from gem5.simulate.simulator import Simulator -from gem5.isas import get_isa_from_str, get_isas_str_set, ISA +import argparse +import importlib from m5.util import fatal -import argparse -import importlib +from gem5.components.boards.mem_mode import MemMode +from gem5.components.boards.simple_board import SimpleBoard +from gem5.components.cachehierarchies.classic.no_cache import NoCache +from gem5.components.memory import SingleChannelDDR3_1600 +from gem5.components.processors.base_cpu_core import BaseCPUCore +from gem5.components.processors.base_cpu_processor import BaseCPUProcessor +from gem5.components.processors.cpu_types import ( + CPUTypes, + get_cpu_type_from_str, + get_cpu_types_str_set, +) +from gem5.components.processors.simple_core import SimpleCore +from gem5.components.processors.simple_processor import SimpleProcessor +from gem5.isas import ( + ISA, + get_isa_from_str, + get_isas_str_set, +) +from gem5.resources.resource import obtain_resource +from gem5.simulate.simulator import Simulator cpu_types_string_map = { CPUTypes.ATOMIC: "AtomicSimpleCPU", diff --git a/tests/gem5/se_mode/hello_se/test_hello_se.py b/tests/gem5/se_mode/hello_se/test_hello_se.py index ebcef719a8..3520f3c7cf 100644 --- a/tests/gem5/se_mode/hello_se/test_hello_se.py +++ b/tests/gem5/se_mode/hello_se/test_hello_se.py @@ -43,10 +43,10 @@ Tests which run simple binaries in gem5's SE mode. The stdlib's SimpleBoard is used to run these tests. """ -from testlib import * - import re +from testlib import * + isa_str_map = { constants.gcn3_x86_tag: "x86", constants.arm_tag: "arm", diff --git a/tests/gem5/stats/configs/simple_binary_run.py b/tests/gem5/stats/configs/simple_binary_run.py index b4d9d76d8d..4729202ae2 100644 --- a/tests/gem5/stats/configs/simple_binary_run.py +++ b/tests/gem5/stats/configs/simple_binary_run.py @@ -31,27 +31,31 @@ The system has no cache heirarchy and is as "bare-bones" as you can get in gem5 while still being functinal. """ -from gem5.resources.resource import Resource -from gem5.components.processors.cpu_types import ( - get_cpu_types_str_set, - get_cpu_type_from_str, -) -from gem5.components.memory import SingleChannelDDR3_1600 -from gem5.components.boards.simple_board import SimpleBoard -from gem5.components.cachehierarchies.classic.no_cache import NoCache -from gem5.components.processors.simple_processor import SimpleProcessor -from gem5.components.processors.base_cpu_core import BaseCPUCore -from gem5.components.processors.base_cpu_processor import BaseCPUProcessor -from gem5.components.processors.simple_core import SimpleCore -from gem5.components.boards.mem_mode import MemMode -from gem5.components.processors.cpu_types import CPUTypes -from gem5.simulate.simulator import Simulator -from gem5.isas import get_isa_from_str, get_isas_str_set, ISA +import argparse +import importlib from m5.util import fatal -import argparse -import importlib +from gem5.components.boards.mem_mode import MemMode +from gem5.components.boards.simple_board import SimpleBoard +from gem5.components.cachehierarchies.classic.no_cache import NoCache +from gem5.components.memory import SingleChannelDDR3_1600 +from gem5.components.processors.base_cpu_core import BaseCPUCore +from gem5.components.processors.base_cpu_processor import BaseCPUProcessor +from gem5.components.processors.cpu_types import ( + CPUTypes, + get_cpu_type_from_str, + get_cpu_types_str_set, +) +from gem5.components.processors.simple_core import SimpleCore +from gem5.components.processors.simple_processor import SimpleProcessor +from gem5.isas import ( + ISA, + get_isa_from_str, + get_isas_str_set, +) +from gem5.resources.resource import Resource +from gem5.simulate.simulator import Simulator parser = argparse.ArgumentParser( description="A gem5 script for running simple binaries in SE mode." diff --git a/tests/gem5/stats/test_hdf5.py b/tests/gem5/stats/test_hdf5.py index c226d717de..a92c43e1b8 100644 --- a/tests/gem5/stats/test_hdf5.py +++ b/tests/gem5/stats/test_hdf5.py @@ -46,8 +46,9 @@ It will not run if the build/ARM/gem5.opt has not been built. As this is not built prior to this test being processed during the Weekly run, this test is not run. """ -import re import os +import re + from testlib import * if config.bin_path: diff --git a/tests/gem5/stdlib/configs/requires_check.py b/tests/gem5/stdlib/configs/requires_check.py index eb29f32aa3..76845174eb 100644 --- a/tests/gem5/stdlib/configs/requires_check.py +++ b/tests/gem5/stdlib/configs/requires_check.py @@ -28,12 +28,15 @@ This is a very simple script to test the behavior of 'gem5.utils.requires'` """ -from gem5.utils.requires import requires -from gem5.isas import ISA, get_isas_str_set, get_isa_from_str - - import argparse +from gem5.isas import ( + ISA, + get_isa_from_str, + get_isas_str_set, +) +from gem5.utils.requires import requires + parser = argparse.ArgumentParser( description="A simple script used to check the behavior of " "`gem5.utils.requires`." diff --git a/tests/gem5/stdlib/configs/simple_binary_run.py b/tests/gem5/stdlib/configs/simple_binary_run.py index a0e4c7f62a..d02fac4533 100644 --- a/tests/gem5/stdlib/configs/simple_binary_run.py +++ b/tests/gem5/stdlib/configs/simple_binary_run.py @@ -31,27 +31,31 @@ The system has no cache heirarchy and is as "bare-bones" as you can get in gem5 while still being functinal. """ -from gem5.resources.resource import Resource -from gem5.components.processors.cpu_types import ( - get_cpu_types_str_set, - get_cpu_type_from_str, -) -from gem5.components.memory import SingleChannelDDR3_1600 -from gem5.components.boards.simple_board import SimpleBoard -from gem5.components.cachehierarchies.classic.no_cache import NoCache -from gem5.components.processors.simple_processor import SimpleProcessor -from gem5.components.processors.base_cpu_core import BaseCPUCore -from gem5.components.processors.base_cpu_processor import BaseCPUProcessor -from gem5.components.processors.simple_core import SimpleCore -from gem5.components.boards.mem_mode import MemMode -from gem5.components.processors.cpu_types import CPUTypes -from gem5.simulate.simulator import Simulator -from gem5.isas import get_isa_from_str, get_isas_str_set, ISA +import argparse +import importlib from m5.util import fatal -import argparse -import importlib +from gem5.components.boards.mem_mode import MemMode +from gem5.components.boards.simple_board import SimpleBoard +from gem5.components.cachehierarchies.classic.no_cache import NoCache +from gem5.components.memory import SingleChannelDDR3_1600 +from gem5.components.processors.base_cpu_core import BaseCPUCore +from gem5.components.processors.base_cpu_processor import BaseCPUProcessor +from gem5.components.processors.cpu_types import ( + CPUTypes, + get_cpu_type_from_str, + get_cpu_types_str_set, +) +from gem5.components.processors.simple_core import SimpleCore +from gem5.components.processors.simple_processor import SimpleProcessor +from gem5.isas import ( + ISA, + get_isa_from_str, + get_isas_str_set, +) +from gem5.resources.resource import Resource +from gem5.simulate.simulator import Simulator cpu_types_string_map = { CPUTypes.ATOMIC: "AtomicSimpleCPU", diff --git a/tests/gem5/stdlib/configs/simulator_exit_event_run.py b/tests/gem5/stdlib/configs/simulator_exit_event_run.py index 56c99359f2..6b5e06890f 100644 --- a/tests/gem5/stdlib/configs/simulator_exit_event_run.py +++ b/tests/gem5/stdlib/configs/simulator_exit_event_run.py @@ -46,18 +46,17 @@ functions or a lone function can also be passed. This can be specified by the `--exit-event-type` parameter. """ -from gem5.resources.resource import obtain_resource -from gem5.components.memory import SingleChannelDDR3_1600 +import argparse + from gem5.components.boards.simple_board import SimpleBoard from gem5.components.cachehierarchies.classic.no_cache import NoCache +from gem5.components.memory import SingleChannelDDR3_1600 from gem5.components.processors.cpu_types import CPUTypes from gem5.components.processors.simple_processor import SimpleProcessor -from gem5.components.boards.simple_board import SimpleBoard -from gem5.simulate.simulator import Simulator -from gem5.simulate.exit_event import ExitEvent from gem5.isas import ISA - -import argparse +from gem5.resources.resource import obtain_resource +from gem5.simulate.exit_event import ExitEvent +from gem5.simulate.simulator import Simulator parser = argparse.ArgumentParser( description="A gem5 script for running simple binaries in SE mode." diff --git a/tests/gem5/suite.py b/tests/gem5/suite.py index 939ecdd8fa..7b01366c23 100644 --- a/tests/gem5/suite.py +++ b/tests/gem5/suite.py @@ -36,18 +36,25 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -import os import copy +import os import subprocess import sys -from testlib.test_util import TestFunction -from testlib.suite import TestSuite +from testlib.configuration import ( + config, + constants, +) from testlib.helper import log_call -from testlib.configuration import constants, config -from .fixture import TempdirFixture, Gem5Fixture, VariableFixture +from testlib.suite import TestSuite +from testlib.test_util import TestFunction from . import verifier +from .fixture import ( + Gem5Fixture, + TempdirFixture, + VariableFixture, +) def gem5_verify_config( diff --git a/tests/gem5/to_tick/configs/tick-exit.py b/tests/gem5/to_tick/configs/tick-exit.py index 4f13d723fa..b1da983abd 100644 --- a/tests/gem5/to_tick/configs/tick-exit.py +++ b/tests/gem5/to_tick/configs/tick-exit.py @@ -28,19 +28,19 @@ """ -from gem5.resources.resource import obtain_resource -from gem5.isas import ISA -from gem5.components.memory import SingleChannelDDR3_1600 -from gem5.components.boards.simple_board import SimpleBoard -from gem5.components.cachehierarchies.classic.no_cache import NoCache -from gem5.components.processors.simple_processor import SimpleProcessor -from gem5.components.processors.cpu_types import CPUTypes -from gem5.simulate.simulator import Simulator -from gem5.simulate.exit_event import ExitEvent +import argparse import m5 -import argparse +from gem5.components.boards.simple_board import SimpleBoard +from gem5.components.cachehierarchies.classic.no_cache import NoCache +from gem5.components.memory import SingleChannelDDR3_1600 +from gem5.components.processors.cpu_types import CPUTypes +from gem5.components.processors.simple_processor import SimpleProcessor +from gem5.isas import ISA +from gem5.resources.resource import obtain_resource +from gem5.simulate.exit_event import ExitEvent +from gem5.simulate.simulator import Simulator parser = argparse.ArgumentParser() diff --git a/tests/gem5/to_tick/configs/tick-to-max.py b/tests/gem5/to_tick/configs/tick-to-max.py index 89396915cf..25e0014211 100644 --- a/tests/gem5/to_tick/configs/tick-to-max.py +++ b/tests/gem5/to_tick/configs/tick-to-max.py @@ -33,18 +33,18 @@ run before, at, or after the running of `simulator.run`. time. """ -from gem5.resources.resource import obtain_resource -from gem5.isas import ISA -from gem5.components.memory import SingleChannelDDR3_1600 -from gem5.components.boards.simple_board import SimpleBoard -from gem5.components.cachehierarchies.classic.no_cache import NoCache -from gem5.components.processors.simple_processor import SimpleProcessor -from gem5.components.processors.cpu_types import CPUTypes -from gem5.simulate.simulator import Simulator +import argparse import m5 -import argparse +from gem5.components.boards.simple_board import SimpleBoard +from gem5.components.cachehierarchies.classic.no_cache import NoCache +from gem5.components.memory import SingleChannelDDR3_1600 +from gem5.components.processors.cpu_types import CPUTypes +from gem5.components.processors.simple_processor import SimpleProcessor +from gem5.isas import ISA +from gem5.resources.resource import obtain_resource +from gem5.simulate.simulator import Simulator parser = argparse.ArgumentParser() diff --git a/tests/gem5/traffic_gen/configs/simple_traffic_run.py b/tests/gem5/traffic_gen/configs/simple_traffic_run.py index 3766d7314f..193b59e2d6 100644 --- a/tests/gem5/traffic_gen/configs/simple_traffic_run.py +++ b/tests/gem5/traffic_gen/configs/simple_traffic_run.py @@ -31,14 +31,17 @@ subsystem. The reported values could be used to compare against a validated set of statistics. """ -import m5 - import argparse import importlib from pathlib import Path -from m5.objects import Root, MemorySize +import m5 +from m5.objects import ( + MemorySize, + Root, +) from m5.stats.gem5stats import get_simstat + from gem5.components.boards.test_board import TestBoard diff --git a/tests/gem5/verifier.py b/tests/gem5/verifier.py index eed9499848..f77c15dded 100644 --- a/tests/gem5/verifier.py +++ b/tests/gem5/verifier.py @@ -40,13 +40,16 @@ """ Built in test cases that verify particular details about a gem5 run. """ -import re -import os import json +import os +import re from testlib import test_util from testlib.configuration import constants -from testlib.helper import joinpath, diff_out_file +from testlib.helper import ( + diff_out_file, + joinpath, +) class Verifier: diff --git a/tests/gem5/x86_boot_tests/configs/x86_boot_exit_run.py b/tests/gem5/x86_boot_tests/configs/x86_boot_exit_run.py index 63b6625479..3a91c4d253 100644 --- a/tests/gem5/x86_boot_tests/configs/x86_boot_exit_run.py +++ b/tests/gem5/x86_boot_tests/configs/x86_boot_exit_run.py @@ -28,24 +28,23 @@ This script will run a simple boot exit test. """ -import m5 - -from gem5.runtime import get_runtime_coherence_protocol -from gem5.isas import ISA -from gem5.utils.requires import requires -from gem5.coherence_protocol import CoherenceProtocol -from gem5.components.boards.x86_board import X86Board -from gem5.components.processors.cpu_types import ( - get_cpu_types_str_set, - get_cpu_type_from_str, -) -from gem5.components.processors.simple_processor import SimpleProcessor -from gem5.simulate.simulator import Simulator -from gem5.resources.resource import obtain_resource - import argparse import importlib +import m5 + +from gem5.coherence_protocol import CoherenceProtocol +from gem5.components.boards.x86_board import X86Board +from gem5.components.processors.cpu_types import ( + get_cpu_type_from_str, + get_cpu_types_str_set, +) +from gem5.components.processors.simple_processor import SimpleProcessor +from gem5.isas import ISA +from gem5.resources.resource import obtain_resource +from gem5.runtime import get_runtime_coherence_protocol +from gem5.simulate.simulator import Simulator +from gem5.utils.requires import requires parser = argparse.ArgumentParser( description="A script to run the gem5 boot test. This test boots the " diff --git a/tests/gem5/x86_boot_tests/test_linux_boot.py b/tests/gem5/x86_boot_tests/test_linux_boot.py index d4b744a0b1..fb16896bf8 100644 --- a/tests/gem5/x86_boot_tests/test_linux_boot.py +++ b/tests/gem5/x86_boot_tests/test_linux_boot.py @@ -24,8 +24,8 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from typing import Optional import re +from typing import Optional from testlib import * diff --git a/tests/main.py b/tests/main.py index 77ab73d3c0..063042d43d 100755 --- a/tests/main.py +++ b/tests/main.py @@ -6,8 +6,8 @@ loaders. Discovers and runs all tests from a given root directory. """ -import sys import os +import sys os.environ["PYTHONUNBUFFERED"] = "1" @@ -17,9 +17,9 @@ ext_path = os.path.join(base_dir, os.pardir, "ext") sys.path.insert(0, base_dir) sys.path.insert(0, ext_path) -import testlib.main as testlib import testlib.configuration as config import testlib.helper as helper +import testlib.main as testlib config.basedir = helper.absdirpath(__file__) sys.exit(testlib()) diff --git a/tests/pyunit/pyunit_jsonserializable_check.py b/tests/pyunit/pyunit_jsonserializable_check.py index 9979d3f9d6..3695374b8e 100644 --- a/tests/pyunit/pyunit_jsonserializable_check.py +++ b/tests/pyunit/pyunit_jsonserializable_check.py @@ -25,6 +25,7 @@ # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. import unittest + from m5.ext.pystats.serializable_stat import SerializableStat diff --git a/tests/pyunit/stdlib/pyunit_looppoint.py b/tests/pyunit/stdlib/pyunit_looppoint.py index f838aa9ff5..398e771df6 100644 --- a/tests/pyunit/stdlib/pyunit_looppoint.py +++ b/tests/pyunit/stdlib/pyunit_looppoint.py @@ -24,22 +24,21 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +import os import unittest from m5.params import PcCountPair from gem5.resources.looppoint import ( Looppoint, + LooppointCsvLoader, + LooppointJsonLoader, + LooppointRegion, LooppointRegionPC, LooppointRegionWarmup, LooppointSimulation, - LooppointRegion, - LooppointCsvLoader, - LooppointJsonLoader, ) -import os - class LooppointRegionPCTestSuite(unittest.TestCase): """Tests the resources.looppoint.LooppointRegionPC class.""" diff --git a/tests/pyunit/stdlib/resources/pyunit_client_wrapper_checks.py b/tests/pyunit/stdlib/resources/pyunit_client_wrapper_checks.py index bc0d00c0f4..f98005e546 100644 --- a/tests/pyunit/stdlib/resources/pyunit_client_wrapper_checks.py +++ b/tests/pyunit/stdlib/resources/pyunit_client_wrapper_checks.py @@ -24,19 +24,19 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -import unittest -from gem5.resources.client import get_resource_json_obj -from gem5.resources.client_api.client_wrapper import ClientWrapper -from unittest.mock import patch -import json -from urllib.error import HTTPError -import io import contextlib +import io +import json +import unittest from pathlib import Path +from unittest.mock import patch +from urllib.error import HTTPError +from gem5.resources.client import get_resource_json_obj from gem5.resources.client_api.atlasclient import ( AtlasClientHttpJsonRequestError, ) +from gem5.resources.client_api.client_wrapper import ClientWrapper mock_json_path = Path(__file__).parent / "refs/resources.json" mock_config_json = { diff --git a/tests/pyunit/stdlib/resources/pyunit_json_client_checks.py b/tests/pyunit/stdlib/resources/pyunit_json_client_checks.py index 82fc775975..be2c6d7810 100644 --- a/tests/pyunit/stdlib/resources/pyunit_json_client_checks.py +++ b/tests/pyunit/stdlib/resources/pyunit_json_client_checks.py @@ -24,11 +24,11 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -import unittest -import tempfile -import os -from typing import Dict import json +import os +import tempfile +import unittest +from typing import Dict from gem5.resources.client_api.jsonclient import JSONClient diff --git a/tests/pyunit/stdlib/resources/pyunit_local_file_path_check.py b/tests/pyunit/stdlib/resources/pyunit_local_file_path_check.py index b1d0ea1bc3..03a7cb95f7 100644 --- a/tests/pyunit/stdlib/resources/pyunit_local_file_path_check.py +++ b/tests/pyunit/stdlib/resources/pyunit_local_file_path_check.py @@ -24,9 +24,10 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from gem5.resources.downloader import _file_uri_to_path -from pathlib import Path import unittest +from pathlib import Path + +from gem5.resources.downloader import _file_uri_to_path class LocalPathTestSuite(unittest.TestCase): diff --git a/tests/pyunit/stdlib/resources/pyunit_md5_utils_check.py b/tests/pyunit/stdlib/resources/pyunit_md5_utils_check.py index 7d6e1f42de..4570f74426 100644 --- a/tests/pyunit/stdlib/resources/pyunit_md5_utils_check.py +++ b/tests/pyunit/stdlib/resources/pyunit_md5_utils_check.py @@ -24,13 +24,16 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -import unittest -import tempfile import os import shutil +import tempfile +import unittest from pathlib import Path -from gem5.resources.md5_utils import md5_file, md5_dir +from gem5.resources.md5_utils import ( + md5_dir, + md5_file, +) class MD5FileTestSuite(unittest.TestCase): diff --git a/tests/pyunit/stdlib/resources/pyunit_obtain_resources_check.py b/tests/pyunit/stdlib/resources/pyunit_obtain_resources_check.py index bab91f2fb7..b4bc5dba94 100644 --- a/tests/pyunit/stdlib/resources/pyunit_obtain_resources_check.py +++ b/tests/pyunit/stdlib/resources/pyunit_obtain_resources_check.py @@ -24,20 +24,21 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -import unittest -import os -import io import contextlib +import io +import os +import unittest from pathlib import Path - -from gem5.resources.resource import obtain_resource, BinaryResource - -from gem5.isas import ISA +from unittest.mock import patch from _m5 import core +from gem5.isas import ISA from gem5.resources.client_api.client_wrapper import ClientWrapper -from unittest.mock import patch +from gem5.resources.resource import ( + BinaryResource, + obtain_resource, +) mock_json_path = Path(__file__).parent / "refs/obtain-resource.json" diff --git a/tests/pyunit/stdlib/resources/pyunit_resource_specialization.py b/tests/pyunit/stdlib/resources/pyunit_resource_specialization.py index 1bf02fd691..2401edbc3e 100644 --- a/tests/pyunit/stdlib/resources/pyunit_resource_specialization.py +++ b/tests/pyunit/stdlib/resources/pyunit_resource_specialization.py @@ -27,18 +27,15 @@ import os import unittest from pathlib import Path +from unittest.mock import patch -from gem5.resources.resource import * - +from gem5.isas import ISA +from gem5.resources.client_api.client_wrapper import ClientWrapper from gem5.resources.looppoint import ( LooppointCsvLoader, LooppointJsonLoader, ) - -from gem5.isas import ISA - -from gem5.resources.client_api.client_wrapper import ClientWrapper -from unittest.mock import patch +from gem5.resources.resource import * mock_json_path = Path(__file__).parent / "refs/resource-specialization.json" diff --git a/tests/pyunit/stdlib/resources/pyunit_suite_checks.py b/tests/pyunit/stdlib/resources/pyunit_suite_checks.py index 419dbaed9f..79944a59fd 100644 --- a/tests/pyunit/stdlib/resources/pyunit_suite_checks.py +++ b/tests/pyunit/stdlib/resources/pyunit_suite_checks.py @@ -26,18 +26,19 @@ import contextlib import io -import unittest -import tempfile import os import shutil +import tempfile +import unittest from pathlib import Path +from unittest.mock import patch + +from gem5.resources.client_api.client_wrapper import ClientWrapper from gem5.resources.resource import ( - obtain_resource, SuiteResource, WorkloadResource, + obtain_resource, ) -from gem5.resources.client_api.client_wrapper import ClientWrapper -from unittest.mock import patch mock_config_json = { "sources": { diff --git a/tests/pyunit/stdlib/resources/pyunit_workload_checks.py b/tests/pyunit/stdlib/resources/pyunit_workload_checks.py index c38fc8e3b8..f5917208d5 100644 --- a/tests/pyunit/stdlib/resources/pyunit_workload_checks.py +++ b/tests/pyunit/stdlib/resources/pyunit_workload_checks.py @@ -24,22 +24,23 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -import unittest import os +import unittest +from pathlib import Path +from typing import Dict +from unittest.mock import patch -from gem5.resources.workload import Workload, CustomWorkload +from gem5.resources.client_api.client_wrapper import ClientWrapper from gem5.resources.resource import ( BinaryResource, DiskImageResource, - obtain_resource, WorkloadResource, + obtain_resource, +) +from gem5.resources.workload import ( + CustomWorkload, + Workload, ) - -from typing import Dict - -from gem5.resources.client_api.client_wrapper import ClientWrapper -from unittest.mock import patch -from pathlib import Path mock_config_json = { "sources": { diff --git a/tests/pyunit/test_run.py b/tests/pyunit/test_run.py index 76cd5f70cc..fd24f753bb 100644 --- a/tests/pyunit/test_run.py +++ b/tests/pyunit/test_run.py @@ -27,6 +27,7 @@ import os from testlib.configuration import constants + from gem5.suite import * """ diff --git a/tests/run.py b/tests/run.py index f95418523e..cb0d42b996 100644 --- a/tests/run.py +++ b/tests/run.py @@ -37,13 +37,11 @@ # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. import os -import sys +import os.path import re import string - +import sys from os.path import join as joinpath -import os.path -import os import m5 diff --git a/util/checkpoint-tester.py b/util/checkpoint-tester.py index 9c638dd736..7fffa4bdf5 100755 --- a/util/checkpoint-tester.py +++ b/util/checkpoint-tester.py @@ -64,9 +64,11 @@ # -import os, sys, re -import subprocess import argparse +import os +import re +import subprocess +import sys parser = argparse.ArgumentParser() diff --git a/util/checkpoint_aggregator.py b/util/checkpoint_aggregator.py index 069557a2ef..8621330853 100755 --- a/util/checkpoint_aggregator.py +++ b/util/checkpoint_aggregator.py @@ -26,10 +26,11 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from configparser import ConfigParser import gzip - -import sys, re, os +import os +import re +import sys +from configparser import ConfigParser class myCP(ConfigParser): diff --git a/util/cpt_upgrader.py b/util/cpt_upgrader.py index 44928bcd2d..92e104fd25 100755 --- a/util/cpt_upgrader.py +++ b/util/cpt_upgrader.py @@ -70,8 +70,11 @@ import configparser -import glob, types, sys, os +import glob +import os import os.path as osp +import sys +import types verbose_print = False @@ -277,7 +280,10 @@ def process_file(path, **kwargs): if __name__ == "__main__": - from argparse import ArgumentParser, SUPPRESS + from argparse import ( + SUPPRESS, + ArgumentParser, + ) parser = ArgumentParser(usage="%(prog)s [args] ") parser.add_argument( diff --git a/util/decode_inst_dep_trace.py b/util/decode_inst_dep_trace.py index 9cd50a6819..0ae8e9e71b 100755 --- a/util/decode_inst_dep_trace.py +++ b/util/decode_inst_dep_trace.py @@ -86,9 +86,10 @@ # 8,35670,1,STORE,1748748,4,74,0:,6,3:,7 # 9,35670,1,COMP,500::,7 -import protolib import sys +import protolib + # Import the packet proto definitions. If they are not found, attempt # to generate them automatically. This assumes that the script is # executed from the gem5 root. diff --git a/util/decode_inst_trace.py b/util/decode_inst_trace.py index 5e77138689..6aeb5ee3b7 100755 --- a/util/decode_inst_trace.py +++ b/util/decode_inst_trace.py @@ -42,9 +42,10 @@ # protoc --python_out=. inst.proto # The ASCII trace format uses one line per request. -import protolib import sys +import protolib + # Import the packet proto definitions try: import inst_pb2 diff --git a/util/decode_packet_trace.py b/util/decode_packet_trace.py index 5111ea4618..67febce411 100755 --- a/util/decode_packet_trace.py +++ b/util/decode_packet_trace.py @@ -39,10 +39,11 @@ # format. import os -import protolib import subprocess import sys +import protolib + util_dir = os.path.dirname(os.path.realpath(__file__)) # Make sure the proto definitions are up to date. subprocess.check_call(["make", "--quiet", "-C", util_dir, "packet_pb2.py"]) diff --git a/util/encode_inst_dep_trace.py b/util/encode_inst_dep_trace.py index 5ca3cda79b..29aee2b473 100755 --- a/util/encode_inst_dep_trace.py +++ b/util/encode_inst_dep_trace.py @@ -86,9 +86,10 @@ # 8,35670,1,STORE,1748748,4,74,0:,6,3:,7 # 9,35670,1,COMP,500::,7 -import protolib import sys +import protolib + # Import the packet proto definitions. If they are not found, attempt # to generate them automatically. This assumes that the script is # executed from the gem5 root. diff --git a/util/encode_packet_trace.py b/util/encode_packet_trace.py index 5df3b21c7c..48d8b58a40 100755 --- a/util/encode_packet_trace.py +++ b/util/encode_packet_trace.py @@ -51,9 +51,10 @@ # This script can of course also be used as a template to convert # other trace formats into the gem5 protobuf format -import protolib import sys +import protolib + # Import the packet proto definitions. If they are not found, attempt # to generate them automatically. This assumes that the script is # executed from the gem5 root. diff --git a/util/find_copyrights.py b/util/find_copyrights.py index 28e3b4c66b..fa1d47dd45 100644 --- a/util/find_copyrights.py +++ b/util/find_copyrights.py @@ -4,7 +4,10 @@ import os import re import sys -from file_types import lang_type, find_files +from file_types import ( + find_files, + lang_type, +) mode_line = re.compile(r"(-\*- *mode:.* *-\*-)") shell_comment = re.compile(r"^\s*#") diff --git a/util/gem5-resources-manager/api/client.py b/util/gem5-resources-manager/api/client.py index 20a91b50d2..f8d5599e03 100644 --- a/util/gem5-resources-manager/api/client.py +++ b/util/gem5-resources-manager/api/client.py @@ -24,8 +24,14 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from abc import ABC, abstractmethod -from typing import Dict, List +from abc import ( + ABC, + abstractmethod, +) +from typing import ( + Dict, + List, +) class Client(ABC): diff --git a/util/gem5-resources-manager/api/create_resources_json.py b/util/gem5-resources-manager/api/create_resources_json.py index 3179142939..02ec96af8d 100644 --- a/util/gem5-resources-manager/api/create_resources_json.py +++ b/util/gem5-resources-manager/api/create_resources_json.py @@ -24,10 +24,11 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -import json -import requests import base64 +import json import os + +import requests from jsonschema import validate diff --git a/util/gem5-resources-manager/api/json_client.py b/util/gem5-resources-manager/api/json_client.py index 24cfaee88c..09c652d748 100644 --- a/util/gem5-resources-manager/api/json_client.py +++ b/util/gem5-resources-manager/api/json_client.py @@ -24,10 +24,14 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from pathlib import Path import json +from pathlib import Path +from typing import ( + Dict, + List, +) + from api.client import Client -from typing import Dict, List class JSONClient(Client): diff --git a/util/gem5-resources-manager/api/mongo_client.py b/util/gem5-resources-manager/api/mongo_client.py index 845524b886..6a60549b9a 100644 --- a/util/gem5-resources-manager/api/mongo_client.py +++ b/util/gem5-resources-manager/api/mongo_client.py @@ -25,12 +25,19 @@ # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. import json -from bson import json_util -from api.client import Client -from pymongo.errors import ConnectionFailure, ConfigurationError -from pymongo import MongoClient -from typing import Dict, List +from typing import ( + Dict, + List, +) + import pymongo +from api.client import Client +from bson import json_util +from pymongo import MongoClient +from pymongo.errors import ( + ConfigurationError, + ConnectionFailure, +) class DatabaseConnectionError(Exception): diff --git a/util/gem5-resources-manager/gem5_resource_cli.py b/util/gem5-resources-manager/gem5_resource_cli.py index 28528bec92..27f10aebe1 100644 --- a/util/gem5-resources-manager/gem5_resource_cli.py +++ b/util/gem5-resources-manager/gem5_resource_cli.py @@ -25,17 +25,18 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -import json -from pymongo import MongoClient -from api.create_resources_json import ResourceJsonCreator -import os -from dotenv import load_dotenv import argparse +import json +import os from itertools import cycle from shutil import get_terminal_size from threading import Thread from time import sleep +from api.create_resources_json import ResourceJsonCreator +from dotenv import load_dotenv +from pymongo import MongoClient + load_dotenv() # read MONGO_URI from environment variable diff --git a/util/gem5-resources-manager/server.py b/util/gem5-resources-manager/server.py index ec298d6c70..f0357a4a27 100644 --- a/util/gem5-resources-manager/server.py +++ b/util/gem5-resources-manager/server.py @@ -24,28 +24,32 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from flask import ( - render_template, - Flask, - request, - redirect, - url_for, - make_response, -) -from bson import json_util -import json -import jsonschema -import requests -import markdown import base64 +import json import secrets from pathlib import Path -from werkzeug.utils import secure_filename -from cryptography.fernet import Fernet, InvalidToken -from cryptography.hazmat.primitives.kdf.scrypt import Scrypt -from cryptography.exceptions import InvalidSignature + +import jsonschema +import markdown +import requests from api.json_client import JSONClient from api.mongo_client import MongoDBClient +from bson import json_util +from cryptography.exceptions import InvalidSignature +from cryptography.fernet import ( + Fernet, + InvalidToken, +) +from cryptography.hazmat.primitives.kdf.scrypt import Scrypt +from flask import ( + Flask, + make_response, + redirect, + render_template, + request, + url_for, +) +from werkzeug.utils import secure_filename databases = {} diff --git a/util/gem5-resources-manager/test/api_test.py b/util/gem5-resources-manager/test/api_test.py index 0ff439cd2e..e6918831ea 100644 --- a/util/gem5-resources-manager/test/api_test.py +++ b/util/gem5-resources-manager/test/api_test.py @@ -24,17 +24,18 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -import flask import contextlib -import unittest -from server import app -import server import json -from bson import json_util +import unittest from unittest.mock import patch + +import flask import mongomock -from api.mongo_client import MongoDBClient import requests +import server +from api.mongo_client import MongoDBClient +from bson import json_util +from server import app @contextlib.contextmanager diff --git a/util/gem5-resources-manager/test/comprehensive_test.py b/util/gem5-resources-manager/test/comprehensive_test.py index 4c32087324..f878b0c347 100644 --- a/util/gem5-resources-manager/test/comprehensive_test.py +++ b/util/gem5-resources-manager/test/comprehensive_test.py @@ -24,14 +24,15 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -import unittest -from server import app -import json -from bson import json_util import copy -import mongomock +import json +import unittest from unittest.mock import patch + +import mongomock from api.mongo_client import MongoDBClient +from bson import json_util +from server import app class TestComprehensive(unittest.TestCase): diff --git a/util/gem5-resources-manager/test/json_client_test.py b/util/gem5-resources-manager/test/json_client_test.py index 0168d475ac..963743c4ac 100644 --- a/util/gem5-resources-manager/test/json_client_test.py +++ b/util/gem5-resources-manager/test/json_client_test.py @@ -24,14 +24,14 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -import unittest -from api.json_client import JSONClient -from server import app import json -from bson import json_util -from unittest.mock import patch +import unittest from pathlib import Path +from unittest.mock import patch + from api.json_client import JSONClient +from bson import json_util +from server import app def get_json(): diff --git a/util/gem5-resources-manager/test/mongo_client_test.py b/util/gem5-resources-manager/test/mongo_client_test.py index 761475ead8..8322fe7507 100644 --- a/util/gem5-resources-manager/test/mongo_client_test.py +++ b/util/gem5-resources-manager/test/mongo_client_test.py @@ -24,13 +24,17 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -import unittest -from server import app, databases import json -from bson import json_util -import mongomock +import unittest from unittest.mock import patch + +import mongomock from api.mongo_client import MongoDBClient +from bson import json_util +from server import ( + app, + databases, +) class TestApi(unittest.TestCase): diff --git a/util/gem5-stubgen.py b/util/gem5-stubgen.py index d003e2212e..70d7c3ac64 100644 --- a/util/gem5-stubgen.py +++ b/util/gem5-stubgen.py @@ -24,7 +24,10 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from mypy.stubgen import generate_stubs, parse_options +from mypy.stubgen import ( + generate_stubs, + parse_options, +) """ This allows us to generate stubs for the modules in gem5. The output will be diff --git a/util/gem5art/artifact/gem5art/artifact/__init__.py b/util/gem5art/artifact/gem5art/artifact/__init__.py index 7e026d5761..c15c4008e8 100644 --- a/util/gem5art/artifact/gem5art/artifact/__init__.py +++ b/util/gem5art/artifact/gem5art/artifact/__init__.py @@ -26,14 +26,14 @@ """This is the gem5 artifact package""" +from ._artifactdb import getDBConnection from .artifact import Artifact from .common_queries import ( getByName, getDiskImages, - getLinuxBinaries, getgem5Binaries, + getLinuxBinaries, ) -from ._artifactdb import getDBConnection __all__ = [ "Artifact", diff --git a/util/gem5art/artifact/gem5art/artifact/_artifactdb.py b/util/gem5art/artifact/gem5art/artifact/_artifactdb.py index a18f47d7d0..428936075c 100644 --- a/util/gem5art/artifact/gem5art/artifact/_artifactdb.py +++ b/util/gem5art/artifact/gem5art/artifact/_artifactdb.py @@ -34,14 +34,24 @@ artifacts stored in the database. Some common queries can be found in common_queries.py """ -from abc import ABC, abstractmethod - import copy import json import os -from pathlib import Path import shutil -from typing import Any, Dict, Iterable, Union, Type, List, Tuple +from abc import ( + ABC, + abstractmethod, +) +from pathlib import Path +from typing import ( + Any, + Dict, + Iterable, + List, + Tuple, + Type, + Union, +) from urllib.parse import urlparse from uuid import UUID diff --git a/util/gem5art/artifact/gem5art/artifact/artifact.py b/util/gem5art/artifact/gem5art/artifact/artifact.py index d178b218dd..177842f591 100644 --- a/util/gem5art/artifact/gem5art/artifact/artifact.py +++ b/util/gem5art/artifact/gem5art/artifact/artifact.py @@ -28,14 +28,22 @@ """ import hashlib -from inspect import cleandoc import json -from pathlib import Path import subprocess import time -from typing import Any, Dict, List, Union, Optional -from uuid import UUID, uuid4 -import json +from inspect import cleandoc +from pathlib import Path +from typing import ( + Any, + Dict, + List, + Optional, + Union, +) +from uuid import ( + UUID, + uuid4, +) from ._artifactdb import getDBConnection diff --git a/util/gem5art/artifact/setup.py b/util/gem5art/artifact/setup.py index 78247eb16d..7c1a1d8851 100755 --- a/util/gem5art/artifact/setup.py +++ b/util/gem5art/artifact/setup.py @@ -28,8 +28,11 @@ from os.path import join from pathlib import Path -from setuptools import setup, find_namespace_packages +from setuptools import ( + find_namespace_packages, + setup, +) with open(Path(__file__).parent / "README.md", encoding="utf-8") as f: long_description = f.read() diff --git a/util/gem5art/artifact/tests/test_artifact.py b/util/gem5art/artifact/tests/test_artifact.py index a12cc8f028..c1578bda68 100644 --- a/util/gem5art/artifact/tests/test_artifact.py +++ b/util/gem5art/artifact/tests/test_artifact.py @@ -27,14 +27,20 @@ """Tests for the Artifact object and associated functions""" import hashlib -from pathlib import Path -import unittest -from uuid import uuid4, UUID -import sys import io +import sys +import unittest +from pathlib import Path +from uuid import ( + UUID, + uuid4, +) from gem5art import artifact -from gem5art.artifact._artifactdb import ArtifactDB, getDBConnection +from gem5art.artifact._artifactdb import ( + ArtifactDB, + getDBConnection, +) class MockDB(ArtifactDB): diff --git a/util/gem5art/artifact/tests/test_filedb.py b/util/gem5art/artifact/tests/test_filedb.py index b7144ffcf3..bd87e59dbd 100644 --- a/util/gem5art/artifact/tests/test_filedb.py +++ b/util/gem5art/artifact/tests/test_filedb.py @@ -29,8 +29,8 @@ import json import os -from pathlib import Path import unittest +from pathlib import Path from uuid import UUID from gem5art.artifact import Artifact diff --git a/util/gem5art/run/bin/gem5art-getruns b/util/gem5art/run/bin/gem5art-getruns index da8d2f0835..fe6046c1c0 100755 --- a/util/gem5art/run/bin/gem5art-getruns +++ b/util/gem5art/run/bin/gem5art-getruns @@ -35,7 +35,10 @@ from json import dump import gem5art.artifact from gem5art.artifact import getDBConnection -from gem5art.run import getRunsByNameLike, getRuns +from gem5art.run import ( + getRuns, + getRunsByNameLike, +) def parseArgs(): diff --git a/util/gem5art/run/gem5art/run.py b/util/gem5art/run/gem5art/run.py index 7b7b823200..4918fa870c 100644 --- a/util/gem5art/run/gem5art/run.py +++ b/util/gem5art/run/gem5art/run.py @@ -35,13 +35,25 @@ experiment is reproducible and the output is saved to the database. import hashlib import json import os -from pathlib import Path import signal import subprocess import time -from typing import Any, Callable, Dict, Iterable, List, Optional, Tuple, Union -from uuid import UUID, uuid4 import zipfile +from pathlib import Path +from typing import ( + Any, + Callable, + Dict, + Iterable, + List, + Optional, + Tuple, + Union, +) +from uuid import ( + UUID, + uuid4, +) from gem5art import artifact from gem5art.artifact import Artifact diff --git a/util/gem5art/run/setup.py b/util/gem5art/run/setup.py index 1ab51b5c2d..70d62117d2 100755 --- a/util/gem5art/run/setup.py +++ b/util/gem5art/run/setup.py @@ -28,8 +28,11 @@ from os.path import join from pathlib import Path -from setuptools import setup, find_namespace_packages +from setuptools import ( + find_namespace_packages, + setup, +) with open(Path(__file__).parent / "README.md", encoding="utf-8") as f: long_description = f.read() diff --git a/util/gem5art/run/tests/test_run.py b/util/gem5art/run/tests/test_run.py index 0bdd561220..58fe8571b5 100644 --- a/util/gem5art/run/tests/test_run.py +++ b/util/gem5art/run/tests/test_run.py @@ -27,9 +27,9 @@ """Tests for gem5Run object""" import hashlib -from pathlib import Path import os import unittest +from pathlib import Path from uuid import uuid4 from gem5art.artifact import artifact diff --git a/util/gem5art/tasks/gem5art/tasks/tasks.py b/util/gem5art/tasks/gem5art/tasks/tasks.py index 3d92956341..6e1a6030f7 100755 --- a/util/gem5art/tasks/gem5art/tasks/tasks.py +++ b/util/gem5art/tasks/gem5art/tasks/tasks.py @@ -24,10 +24,11 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from .celery import gem5app import multiprocessing as mp import time +from .celery import gem5app + @gem5app.task(bind=True, serializer="pickle") def run_gem5_instance(self, gem5_run, cwd="."): diff --git a/util/gem5art/tasks/setup.py b/util/gem5art/tasks/setup.py index 290c68a17a..1cfe4c770d 100755 --- a/util/gem5art/tasks/setup.py +++ b/util/gem5art/tasks/setup.py @@ -28,8 +28,11 @@ from os.path import join from pathlib import Path -from setuptools import setup, find_namespace_packages +from setuptools import ( + find_namespace_packages, + setup, +) with open(Path(__file__).parent / "README.md", encoding="utf-8") as f: long_description = f.read() diff --git a/util/gem5img.py b/util/gem5img.py index dcb66e0bc9..4a8c0916fe 100755 --- a/util/gem5img.py +++ b/util/gem5img.py @@ -42,13 +42,21 @@ # Script for managing a gem5 disk image. # -from argparse import ArgumentParser import os -from os import environ as env -import string -from subprocess import CalledProcessError, Popen, PIPE, STDOUT -from sys import exit, argv import re +import string +from argparse import ArgumentParser +from os import environ as env +from subprocess import ( + PIPE, + STDOUT, + CalledProcessError, + Popen, +) +from sys import ( + argv, + exit, +) # Some constants. MaxLBACylinders = 16383 diff --git a/util/gen_arm_fs_files.py b/util/gen_arm_fs_files.py index 6446d79bfb..3a6605be6f 100755 --- a/util/gen_arm_fs_files.py +++ b/util/gen_arm_fs_files.py @@ -38,14 +38,16 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from argparse import ArgumentParser, ArgumentDefaultsHelpFormatter -from subprocess import call -from platform import machine +import os +import sys +from argparse import ( + ArgumentDefaultsHelpFormatter, + ArgumentParser, +) from distutils import spawn from glob import glob - -import sys -import os +from platform import machine +from subprocess import call def run_cmd(explanation, working_dir, cmd, stdout=None): diff --git a/util/gerrit-bot/bot.py b/util/gerrit-bot/bot.py index 5ef4151a48..5f6afdaf99 100755 --- a/util/gerrit-bot/bot.py +++ b/util/gerrit-bot/bot.py @@ -26,14 +26,17 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from gerrit import GerritResponseParser as Parser -from gerrit import GerritRestAPI -from util import add_maintainers_to_change, convert_time_in_seconds - import json +import sys import time -import sys +from gerrit import GerritResponseParser as Parser +from gerrit import GerritRestAPI + +from util import ( + add_maintainers_to_change, + convert_time_in_seconds, +) sys.path.append("..") import maint.lib.maintainers diff --git a/util/gerrit-bot/gerrit.py b/util/gerrit-bot/gerrit.py index 2e68a70645..b75434b4b3 100644 --- a/util/gerrit-bot/gerrit.py +++ b/util/gerrit-bot/gerrit.py @@ -26,10 +26,11 @@ import copy import json -import requests from types import SimpleNamespace from urllib.parse import urljoin +import requests + class GerritResponseParser: @staticmethod diff --git a/util/git-commit-msg.py b/util/git-commit-msg.py index f0a60110c7..d40aa68e1c 100755 --- a/util/git-commit-msg.py +++ b/util/git-commit-msg.py @@ -32,8 +32,8 @@ import os import re import sys -from maint.lib import maintainers +from maint.lib import maintainers from style.repo import GitRepo diff --git a/util/git-pre-commit.py b/util/git-pre-commit.py index c6f3b3c033..0a51ba0478 100755 --- a/util/git-pre-commit.py +++ b/util/git-pre-commit.py @@ -36,16 +36,21 @@ # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from tempfile import TemporaryFile +import argparse import os import subprocess import sys +from tempfile import TemporaryFile from style.repo import GitRepo -from style.verifiers import all_verifiers, all_regions -from style.style import StdioUI, check_ignores - -import argparse +from style.style import ( + StdioUI, + check_ignores, +) +from style.verifiers import ( + all_regions, + all_verifiers, +) parser = argparse.ArgumentParser(description="gem5 git style checker hook") diff --git a/util/maint/list_changes.py b/util/maint/list_changes.py index 1dcb70def2..805d7676b6 100755 --- a/util/maint/list_changes.py +++ b/util/maint/list_changes.py @@ -36,8 +36,8 @@ # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -import subprocess import re +import subprocess from functools import wraps diff --git a/util/maint/show_changes_by_file.py b/util/maint/show_changes_by_file.py index 8da3ee64bd..600f1e8f1a 100755 --- a/util/maint/show_changes_by_file.py +++ b/util/maint/show_changes_by_file.py @@ -33,7 +33,10 @@ import subprocess -from collections import OrderedDict, defaultdict +from collections import ( + OrderedDict, + defaultdict, +) class OrderedDefaultDict(OrderedDict, defaultdict): diff --git a/util/md5.py b/util/md5.py index 333f714109..0c55f92e0d 100644 --- a/util/md5.py +++ b/util/md5.py @@ -26,7 +26,11 @@ import argparse from pathlib import Path -from gem5.resources.md5_utils import md5_file, md5_dir + +from gem5.resources.md5_utils import ( + md5_dir, + md5_file, +) parser = argparse.ArgumentParser( description="A utility to determine the md5 hash of files and " diff --git a/util/minorview.py b/util/minorview.py index f7a53b1d26..eb4e0bd617 100755 --- a/util/minorview.py +++ b/util/minorview.py @@ -38,18 +38,23 @@ # minorview.py: Minorview visuliser for MinorCPU model MinorTrace output # -import gtk +import argparse import os import sys -import argparse + +import gtk # Find MinorView modules even if not called from minorview directory minorviewDir = os.path.dirname(os.path.realpath(__file__)) sys.path.append(minorviewDir) from minorview.model import BlobModel -from minorview.view import BlobView, BlobController, BlobWindow from minorview.point import Point +from minorview.view import ( + BlobController, + BlobView, + BlobWindow, +) if __name__ == "__main__": parser = argparse.ArgumentParser(description="Minor visualiser") diff --git a/util/minorview/blobs.py b/util/minorview/blobs.py index 8d379f0cb8..1f6753e76a 100644 --- a/util/minorview/blobs.py +++ b/util/minorview/blobs.py @@ -41,17 +41,23 @@ import pygtk pygtk.require("2.0") -import gtk -import gobject -import cairo -import re import math +import re +import cairo +import gobject +import gtk + +from . import ( + colours, + model, + parse, +) +from .colours import ( + backgroundColour, + black, +) from .point import Point -from . import parse -from . import colours -from .colours import backgroundColour, black -from . import model def centre_size_to_sides(centre, size): diff --git a/util/minorview/model.py b/util/minorview/model.py index cf8c04bc04..91979825c3 100644 --- a/util/minorview/model.py +++ b/util/minorview/model.py @@ -33,14 +33,17 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from . import parse -from . import colours +import os +import re +from time import time as wall_time + +from . import ( + blobs, + colours, + parse, +) from .colours import unknownColour from .point import Point -import re -from . import blobs -from time import time as wall_time -import os id_parts = "TSPLFE" diff --git a/util/minorview/view.py b/util/minorview/view.py index 37564996eb..671a80869c 100644 --- a/util/minorview/view.py +++ b/util/minorview/view.py @@ -36,17 +36,25 @@ import pygtk pygtk.require("2.0") -import gtk -import gobject -import cairo import re +import cairo +import gobject +import gtk + +from . import ( + blobs, + colours, + model, + parse, +) +from .model import ( + BlobDataSelect, + BlobModel, + Id, + special_state_chars, +) from .point import Point -from . import parse -from . import colours -from . import model -from .model import Id, BlobModel, BlobDataSelect, special_state_chars -from . import blobs class BlobView: diff --git a/util/o3-pipeview.py b/util/o3-pipeview.py index 3228832446..a821a13b4f 100755 --- a/util/o3-pipeview.py +++ b/util/o3-pipeview.py @@ -38,9 +38,9 @@ # Pipeline activity viewer for the O3 CPU model. import argparse +import copy import os import sys -import copy # Temporary storage for instructions. The queue is filled in out-of-order # until it reaches 'max_threshold' number of instructions. It is then diff --git a/util/obtain-resource.py b/util/obtain-resource.py index de6a7b90e2..b11ee328de 100644 --- a/util/obtain-resource.py +++ b/util/obtain-resource.py @@ -41,9 +41,10 @@ build/ALL/gem5.opt util/obtain-resource.py [-p ] [-q] """ if __name__ == "__m5_main__": - from gem5.resources.resource import obtain_resource import argparse + from gem5.resources.resource import obtain_resource + parser = argparse.ArgumentParser() parser.add_argument( diff --git a/util/on-chip-network-power-area.py b/util/on-chip-network-power-area.py index 563bf6334d..f5e463b3b9 100644 --- a/util/on-chip-network-power-area.py +++ b/util/on-chip-network-power-area.py @@ -25,8 +25,11 @@ # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +import os +import string +import subprocess +import sys from configparser import ConfigParser -import string, sys, subprocess, os # Compile DSENT to generate the Python module and then import it. # This script assumes it is executed from the gem5 root. diff --git a/util/oprofile-top.py b/util/oprofile-top.py index 2808ea10fe..a694894473 100755 --- a/util/oprofile-top.py +++ b/util/oprofile-top.py @@ -28,9 +28,10 @@ # Parse sampled function profile output (quick hack). -import sys -import re import getopt +import re +import sys + from categories import * diff --git a/util/plot_dram/PlotPowerStates.py b/util/plot_dram/PlotPowerStates.py index 31e831f8b0..d22249aa25 100755 --- a/util/plot_dram/PlotPowerStates.py +++ b/util/plot_dram/PlotPowerStates.py @@ -36,11 +36,12 @@ import matplotlib matplotlib.use("Agg") -import matplotlib.pyplot as plt -from matplotlib.font_manager import FontProperties -import numpy as np import os +import matplotlib.pyplot as plt +import numpy as np +from matplotlib.font_manager import FontProperties + # global results dict results = {} idleResults = {} diff --git a/util/plot_dram/dram_lat_mem_rd_plot.py b/util/plot_dram/dram_lat_mem_rd_plot.py index 798148f714..a8ef288028 100755 --- a/util/plot_dram/dram_lat_mem_rd_plot.py +++ b/util/plot_dram/dram_lat_mem_rd_plot.py @@ -36,15 +36,15 @@ # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. try: - import matplotlib.pyplot as plt import matplotlib as mpl + import matplotlib.pyplot as plt import numpy as np except ImportError: print("Failed to import matplotlib and numpy") exit(-1) -import sys import re +import sys # This script is intended to post process and plot the output from diff --git a/util/plot_dram/dram_sweep_plot.py b/util/plot_dram/dram_sweep_plot.py index 8fbeaf511c..c789ab32a4 100755 --- a/util/plot_dram/dram_sweep_plot.py +++ b/util/plot_dram/dram_sweep_plot.py @@ -36,16 +36,16 @@ # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. try: - from mpl_toolkits.mplot3d import Axes3D - from matplotlib import cm import matplotlib.pyplot as plt import numpy as np + from matplotlib import cm + from mpl_toolkits.mplot3d import Axes3D except ImportError: print("Failed to import matplotlib and numpy") exit(-1) -import sys import re +import sys # Determine the parameters of the sweep from the simout output, and diff --git a/util/plot_dram/lowp_dram_sweep_plot.py b/util/plot_dram/lowp_dram_sweep_plot.py index 0f53a3319b..89b69b5116 100755 --- a/util/plot_dram/lowp_dram_sweep_plot.py +++ b/util/plot_dram/lowp_dram_sweep_plot.py @@ -35,11 +35,12 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -import PlotPowerStates as plotter import argparse import os from subprocess import call +import PlotPowerStates as plotter + parser = argparse.ArgumentParser( formatter_class=argparse.ArgumentDefaultsHelpFormatter ) diff --git a/util/slicc b/util/slicc index d660510b58..14f4c09c54 100755 --- a/util/slicc +++ b/util/slicc @@ -27,7 +27,10 @@ if __name__ == "__main__": import sys - from os.path import dirname, join + from os.path import ( + dirname, + join, + ) base = dirname(__file__) sys.path.insert(1, join(base, "../src/mem")) diff --git a/util/streamline/m5stats2streamline.py b/util/streamline/m5stats2streamline.py index e350806e87..ec2dc0e834 100755 --- a/util/streamline/m5stats2streamline.py +++ b/util/streamline/m5stats2streamline.py @@ -58,15 +58,16 @@ # APC project generation based on Gator v17 (DS-5 v5.17) # Subsequent versions should be backward compatible -import re, sys, os -from configparser import ConfigParser -import gzip -import xml.etree.ElementTree as ET -import xml.dom.minidom as minidom -import shutil -import zlib - import argparse +import gzip +import os +import re +import shutil +import sys +import xml.dom.minidom as minidom +import xml.etree.ElementTree as ET +import zlib +from configparser import ConfigParser parser = argparse.ArgumentParser( formatter_class=argparse.RawDescriptionHelpFormatter, diff --git a/util/style.py b/util/style.py index 1b3ebe1602..fd1882a4d5 100755 --- a/util/style.py +++ b/util/style.py @@ -38,12 +38,11 @@ import os import sys -from style.file_types import lang_type import style.verifiers -from style.region import all_regions - -from style.style import StdioUI from style import repo +from style.file_types import lang_type +from style.region import all_regions +from style.style import StdioUI verifier_names = {c.__name__: c for c in style.verifiers.all_verifiers} diff --git a/util/style/repo.py b/util/style/repo.py index 04db36d15d..758aaa1180 100644 --- a/util/style/repo.py +++ b/util/style/repo.py @@ -35,9 +35,9 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from abc import * import os import subprocess +from abc import * from .region import * from .style import modified_regions diff --git a/util/style/style.py b/util/style/style.py index a40671fb47..add8069bdf 100644 --- a/util/style/style.py +++ b/util/style/style.py @@ -39,10 +39,13 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from abc import ABCMeta, abstractmethod import difflib import re import sys +from abc import ( + ABCMeta, + abstractmethod, +) from .region import * diff --git a/util/style/verifiers.py b/util/style/verifiers.py index 4860cc461e..654ce7a720 100644 --- a/util/style/verifiers.py +++ b/util/style/verifiers.py @@ -40,17 +40,22 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from abc import ABCMeta, abstractmethod -from difflib import SequenceMatcher import inspect import os import re import sys +from abc import ( + ABCMeta, + abstractmethod, +) +from difflib import SequenceMatcher -from . import style -from . import sort_includes -from .region import * +from . import ( + sort_includes, + style, +) from .file_types import lang_type +from .region import * def safefix(fix_func): diff --git a/util/systemc/systemc_within_gem5/systemc_gem5_tlm/SystemC_Example.py b/util/systemc/systemc_within_gem5/systemc_gem5_tlm/SystemC_Example.py index d23b6764c7..1e8269c92a 100644 --- a/util/systemc/systemc_within_gem5/systemc_gem5_tlm/SystemC_Example.py +++ b/util/systemc/systemc_within_gem5/systemc_gem5_tlm/SystemC_Example.py @@ -23,13 +23,11 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from m5.params import * -from m5.SimObject import SimObject -from m5.params import * -from m5.proxy import * - from m5.objects.SystemC import SystemC_ScModule from m5.objects.Tlm import TlmTargetSocket +from m5.params import * +from m5.proxy import * +from m5.SimObject import SimObject # This class is a subclass of sc_module, and all the special magic which makes diff --git a/util/systemc/systemc_within_gem5/systemc_gem5_tlm/config.py b/util/systemc/systemc_within_gem5/systemc_gem5_tlm/config.py index 71529ba879..36686bf89b 100755 --- a/util/systemc/systemc_within_gem5/systemc_gem5_tlm/config.py +++ b/util/systemc/systemc_within_gem5/systemc_gem5_tlm/config.py @@ -28,8 +28,8 @@ # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS # SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. import os -import m5 +import m5 from m5.objects import * # Create a config to be used by the traffic generator diff --git a/util/systemc/systemc_within_gem5/systemc_sc_main/config.py b/util/systemc/systemc_within_gem5/systemc_sc_main/config.py index 454c3b5813..81c9e15f56 100755 --- a/util/systemc/systemc_within_gem5/systemc_sc_main/config.py +++ b/util/systemc/systemc_within_gem5/systemc_sc_main/config.py @@ -24,10 +24,13 @@ # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. import argparse -import m5 import sys -from m5.objects import SystemC_Kernel, Root +import m5 +from m5.objects import ( + Root, + SystemC_Kernel, +) # pylint:disable=unused-variable diff --git a/util/systemc/systemc_within_gem5/systemc_simple_object/SystemC_Example.py b/util/systemc/systemc_within_gem5/systemc_simple_object/SystemC_Example.py index e4535d2c12..7832328c0d 100644 --- a/util/systemc/systemc_within_gem5/systemc_simple_object/SystemC_Example.py +++ b/util/systemc/systemc_within_gem5/systemc_simple_object/SystemC_Example.py @@ -23,11 +23,10 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +from m5.objects.SystemC import SystemC_ScModule from m5.params import * from m5.SimObject import SimObject -from m5.objects.SystemC import SystemC_ScModule - # This class is a subclass of sc_module, and all the special magic which makes # that work is handled in the base classes. diff --git a/util/systemc/systemc_within_gem5/systemc_simple_object/config.py b/util/systemc/systemc_within_gem5/systemc_simple_object/config.py index 8a86e1fb01..c71c5ac3db 100755 --- a/util/systemc/systemc_within_gem5/systemc_simple_object/config.py +++ b/util/systemc/systemc_within_gem5/systemc_simple_object/config.py @@ -25,10 +25,15 @@ import argparse -import m5 import sys -from m5.objects import SystemC_Kernel, Root, SystemC_Printer, Gem5_Feeder +import m5 +from m5.objects import ( + Gem5_Feeder, + Root, + SystemC_Kernel, + SystemC_Printer, +) # pylint:disable=unused-variable diff --git a/util/systemc/systemc_within_gem5/systemc_tlm/config.py b/util/systemc/systemc_within_gem5/systemc_tlm/config.py index 454c3b5813..81c9e15f56 100755 --- a/util/systemc/systemc_within_gem5/systemc_tlm/config.py +++ b/util/systemc/systemc_within_gem5/systemc_tlm/config.py @@ -24,10 +24,13 @@ # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. import argparse -import m5 import sys -from m5.objects import SystemC_Kernel, Root +import m5 +from m5.objects import ( + Root, + SystemC_Kernel, +) # pylint:disable=unused-variable diff --git a/util/tlm/conf/tlm_elastic_slave.py b/util/tlm/conf/tlm_elastic_slave.py index 1007c5244b..8614eae26b 100644 --- a/util/tlm/conf/tlm_elastic_slave.py +++ b/util/tlm/conf/tlm_elastic_slave.py @@ -29,9 +29,11 @@ # SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. import m5 - from m5.objects import * -from m5.util import addToPath, fatal +from m5.util import ( + addToPath, + fatal, +) addToPath("../../../configs/common/") diff --git a/util/tlm/conf/tlm_master.py b/util/tlm/conf/tlm_master.py index a3782a72cc..a7e5d8b99e 100644 --- a/util/tlm/conf/tlm_master.py +++ b/util/tlm/conf/tlm_master.py @@ -29,11 +29,11 @@ # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS # SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +import os + import m5 from m5.objects import * -import os - # Base System Architecture: # +-----+ ^ # | TLM | | TLM World diff --git a/util/tlm/examples/tlm_elastic_slave_with_l2.py b/util/tlm/examples/tlm_elastic_slave_with_l2.py index 6b3f7b43fb..5bb15b520d 100644 --- a/util/tlm/examples/tlm_elastic_slave_with_l2.py +++ b/util/tlm/examples/tlm_elastic_slave_with_l2.py @@ -29,9 +29,11 @@ # SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. import m5 - from m5.objects import * -from m5.util import addToPath, fatal +from m5.util import ( + addToPath, + fatal, +) addToPath("../../../configs/common/") diff --git a/util/update-copyright.py b/util/update-copyright.py index 1c3fd611ac..3ad0c92466 100755 --- a/util/update-copyright.py +++ b/util/update-copyright.py @@ -41,7 +41,6 @@ import subprocess import sys import git_filter_repo - import update_copyright parser = argparse.ArgumentParser(