d11c40dcac
This ensures `isort` is applied to all files in the repo. Change-Id: Ib7ced1c924ef1639542bf0d1a01c5737f6ba43e9
62 lines
2.4 KiB
Python
Executable File
62 lines
2.4 KiB
Python
Executable File
# Copyright (c) 2022 Fraunhofer IESE
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# All rights reserved
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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import m5
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from m5.objects import *
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traffic_gen = PyTrafficGen()
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system = System()
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vd = VoltageDomain(voltage="1V")
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system.mem_mode = "timing"
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system.cpu = traffic_gen
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dramsys = DRAMSys(
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configuration="ext/dramsys/DRAMSys/configs/ddr4-example.json",
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resource_directory="ext/dramsys/DRAMSys/configs",
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)
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system.target = dramsys
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system.transactor = Gem5ToTlmBridge32()
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system.clk_domain = SrcClockDomain(clock="1.5GHz", voltage_domain=vd)
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# Connect everything:
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system.transactor.gem5 = system.cpu.port
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system.transactor.tlm = system.target.tlm
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kernel = SystemC_Kernel(system=system)
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root = Root(full_system=False, systemc_kernel=kernel)
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m5.instantiate()
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idle = traffic_gen.createIdle(100000)
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linear = traffic_gen.createLinear(10000000, 0, 16777216, 64, 500, 1500, 65, 0)
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random = traffic_gen.createRandom(10000000, 0, 16777216, 64, 500, 1500, 65, 0)
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traffic_gen.start([linear, idle, random])
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cause = m5.simulate(20000000).getCause()
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print(cause)
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