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arch-riscv: revert SyscallABI32 changes

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Change-Id: I07c3e4aee06a6f5576d4a3488a29673fdb0a09bf
This commit is contained in:
Robert Hauser
2024-03-16 09:04:36 +00:00
parent 3d2d960f10
commit bf63ec953a
3 changed files with 1 additions and 66 deletions
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1
src/arch/riscv/SConscript
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@@ -58,7 +58,6 @@ Source('pma_checker.cc', tags='riscv isa')
Source('pmp.cc', tags='riscv isa')
Source('reg_abi.cc', tags='riscv isa')
Source('remote_gdb.cc', tags='riscv isa')
Source('se_workload.cc', tags='riscv isa')
Source('tlb.cc', tags='riscv isa')
Source('linux/se_workload.cc', tags='riscv isa')

44
src/arch/riscv/se_workload.cc
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@@ -1,44 +0,0 @@
/*
* Copyright 2020 Google Inc.
* Copyright (c) 2024 University of Rostock
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met: redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer;
* redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution;
* neither the name of the copyright holders nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include <arch/riscv/se_workload.hh>
namespace gem5
{
namespace RiscvISA
{
const std::vector<RegId> SEWorkload::SyscallABI32::ArgumentRegs = {
int_reg::A0, int_reg::A1, int_reg::A2, int_reg::A3,
int_reg::A4, int_reg::A5, int_reg::A6
};
} // namespace RiscvISA
} // namespace gem5

22
src/arch/riscv/se_workload.hh
View File

@@ -1,6 +1,5 @@
/*
* Copyright 2020 Google Inc.
* Copyright (c) 2024 University of Rostock
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
@@ -62,12 +61,7 @@ class SEWorkload : public gem5::SEWorkload
loader::Arch getArch() const override { return loader::Riscv64; }
using SyscallABI64 = RegABI64;
struct SyscallABI32 : public GenericSyscallABI32
{
static const std::vector<RegId> ArgumentRegs;
};
using SyscallABI32 = RegABI32;
};
} // namespace RiscvISA
@@ -75,20 +69,6 @@ class SEWorkload : public gem5::SEWorkload
namespace guest_abi
{
template<typename ABI, typename Arg>
struct Argument<ABI, Arg,
std::enable_if_t<
std::is_base_of_v<ABI, RiscvISA::SEWorkload::SyscallABI32> &&
std::is_integral_v<Arg> &&
ABI::template IsWideV<Arg>>>
{
static Arg
get(ThreadContext *tc, typename ABI::State &state)
{
return (Arg) bits(tc->getReg(ABI::ArgumentRegs[state++]), 31, 0);
}
};
template <>
struct Result<RiscvISA::SEWorkload::SyscallABI64, SyscallReturn>
{