From bf63ec953a4ef29018b186e9154157e6270b0f0f Mon Sep 17 00:00:00 2001
From: Robert Hauser <robert.hauser@uni-rostock.de>
Date: Sat, 16 Mar 2024 09:04:36 +0000
Subject: [PATCH] arch-riscv: revert SyscallABI32 changes

Change-Id: I07c3e4aee06a6f5576d4a3488a29673fdb0a09bf
---
 src/arch/riscv/SConscript     |  1 -
 src/arch/riscv/se_workload.cc | 44 -----------------------------------
 src/arch/riscv/se_workload.hh | 22 +-----------------
 3 files changed, 1 insertion(+), 66 deletions(-)
 delete mode 100644 src/arch/riscv/se_workload.cc

diff --git a/src/arch/riscv/SConscript b/src/arch/riscv/SConscript
index 2231a0ffa1..78864523c7 100644
--- a/src/arch/riscv/SConscript
+++ b/src/arch/riscv/SConscript
@@ -58,7 +58,6 @@ Source('pma_checker.cc', tags='riscv isa')
 Source('pmp.cc', tags='riscv isa')
 Source('reg_abi.cc', tags='riscv isa')
 Source('remote_gdb.cc', tags='riscv isa')
-Source('se_workload.cc', tags='riscv isa')
 Source('tlb.cc', tags='riscv isa')
 
 Source('linux/se_workload.cc', tags='riscv isa')
diff --git a/src/arch/riscv/se_workload.cc b/src/arch/riscv/se_workload.cc
deleted file mode 100644
index 108bea9d86..0000000000
--- a/src/arch/riscv/se_workload.cc
+++ /dev/null
@@ -1,44 +0,0 @@
-/*
- * Copyright 2020 Google Inc.
- * Copyright (c) 2024 University of Rostock
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-
-#include <arch/riscv/se_workload.hh>
-
-namespace gem5
-{
-
-namespace RiscvISA
-{
-
-const std::vector<RegId> SEWorkload::SyscallABI32::ArgumentRegs = {
-    int_reg::A0, int_reg::A1, int_reg::A2, int_reg::A3,
-    int_reg::A4, int_reg::A5, int_reg::A6
-};
-
-} // namespace RiscvISA
-} // namespace gem5
diff --git a/src/arch/riscv/se_workload.hh b/src/arch/riscv/se_workload.hh
index 8357ab5ac6..dd18a92905 100644
--- a/src/arch/riscv/se_workload.hh
+++ b/src/arch/riscv/se_workload.hh
@@ -1,6 +1,5 @@
 /*
  * Copyright 2020 Google Inc.
- * Copyright (c) 2024 University of Rostock
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions are
@@ -62,12 +61,7 @@ class SEWorkload : public gem5::SEWorkload
     loader::Arch getArch() const override { return loader::Riscv64; }
 
     using SyscallABI64 = RegABI64;
-
-    struct SyscallABI32 : public GenericSyscallABI32
-    {
-        static const std::vector<RegId> ArgumentRegs;
-    };
-
+    using SyscallABI32 = RegABI32;
 };
 
 } // namespace RiscvISA
@@ -75,20 +69,6 @@ class SEWorkload : public gem5::SEWorkload
 namespace guest_abi
 {
 
-template<typename ABI, typename Arg>
-struct Argument<ABI, Arg,
-    std::enable_if_t<
-        std::is_base_of_v<ABI, RiscvISA::SEWorkload::SyscallABI32> &&
-        std::is_integral_v<Arg> &&
-        ABI::template IsWideV<Arg>>>
-{
-    static Arg
-    get(ThreadContext *tc, typename ABI::State &state)
-    {
-        return (Arg) bits(tc->getReg(ABI::ArgumentRegs[state++]), 31, 0);
-    }
-};
-
 template <>
 struct Result<RiscvISA::SEWorkload::SyscallABI64, SyscallReturn>
 {