arch-riscv: fix return value of pseudo instruction

Only the lower 32 bit of return values of pseudo instructions are
stored (in a0). Therefore, the upper 32 bit are stored in a1 to
enable a correct return value.

Change-Id: Idf33c325033281fc191a9285eb5d34fd4965cde9

src/arch/riscv/isa/formats/m5ops.isa

@@ -1,5 +1,6 @@
 //
 // Copyright (c) 2020 Barkhausen Institut
+// Copyright (c) 2024 University of Rostock
 // All rights reserved
 //
 // The license below extends only to copyright in the software and shall
@@ -40,10 +41,12 @@ def format M5Op() {{
             uint64_t result;
             if (machInst.rv_type == RV32) {
                 pseudo_inst::pseudoInst<RegABI32>(xc->tcBase(), M5FUNC, result);
+                a0 = bits(result, 31, 0);
+                a1 = bits(result, 63, 32);
             } else {
                 pseudo_inst::pseudoInst<RegABI64>(xc->tcBase(), M5FUNC, result);
-            }
-            a0 = rvSext(result)''',
+                a0 = rvSext(result);
+            }''',
             ['IsNonSpeculative', 'IsSerializeAfter'])
     header_output = BasicDeclare.subst(iop)
     decoder_output = BasicConstructor.subst(iop)

src/arch/riscv/isa/operands.isa

@@ -3,6 +3,7 @@
 // Copyright (c) 2015 RISC-V Foundation
 // Copyright (c) 2016 The University of Virginia
 // Copyright (c) 2020 Barkhausen Institut
+// Copyright (c) 2024 University of Rostock
 // All rights reserved.
 //
 // Redistribution and use in source and binary forms, with or without
@@ -71,6 +72,7 @@ def operands {{
     'sp': IntReg('ud', 'StackPointerReg', 'IsInteger', 2),
 
     'a0': IntReg('ud', '10', 'IsInteger', 1),
+    'a1': IntReg('ud', '11', 'IsInteger', 2),
 
     'Fd': FloatRegOp('df', 'FD', 'IsFloating', 1),
     'Fd_bits': FloatRegOp('ud', 'FD', 'IsFloating', 1),