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arch-riscv: fix vl in mask load/store (i.e vlm.v/vsm.v) (#830)

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The vlm.v and vsm.v unit-stride mask load/store instructions are
constructed with an incorrect VL when the current one is larger than
than VLEN/EEW (i.e. when LMUL > 1). This commit fixes the issue for both
instructions.
This commit is contained in:
Saúl
2024-02-08 23:06:49 +01:00
committed by GitHub
parent 7fe1588546
commit 7d80658a39
1 changed files with 2 additions and 4 deletions
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6
src/arch/riscv/isa/templates/vector_mem.isa
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@@ -464,8 +464,7 @@ def template VlmConstructor {{
%(set_reg_idx_arr)s;
%(constructor)s;
const uint32_t micro_vlmax = vlen / width_EEW(_machInst.width);
int32_t micro_vl = (std::min(this->vl, micro_vlmax) + 7) / 8;
int32_t micro_vl = (this->vl + 7) / 8;
StaticInstPtr microop;
if (micro_vl == 0) {
@@ -491,8 +490,7 @@ def template VsmConstructor {{
%(set_reg_idx_arr)s;
%(constructor)s;
const uint32_t micro_vlmax = vlen / width_EEW(_machInst.width);
int32_t micro_vl = (std::min(this->vl, micro_vlmax) + 7) / 8;
int32_t micro_vl = (this->vl + 7) / 8;
StaticInstPtr microop;
if (micro_vl == 0) {