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arch-riscv: Fix load and store to use EEW instead of SEW (#859)

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Vector unit-stride instructions have an EEW encoded directly in the
instruction, We should use that instead of SEW in vtype.

Ref:

https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#73-vector-loadstore-width-encoding
This commit is contained in:
Bobby R. Bruce
2024-02-08 12:14:11 -08:00
committed by GitHub
parent b2d13ee63a e685c072d1
commit 7fe1588546
1 changed files with 6 additions and 8 deletions
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14
src/arch/riscv/isa/templates/vector_mem.isa
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@@ -177,15 +177,14 @@ Fault
%(fault_code)s;
const size_t micro_vlmax = vtype_VLMAX(machInst.vtype8, vlen, true);
const size_t micro_elems = vlen / width_EEW(machInst.width);
const size_t micro_vlmax = vlen / width_EEW(machInst.width);
if (fault != NoFault)
return fault;
size_t ei;
for (size_t i = 0; i < micro_elems; i++) {
for (size_t i = 0; i < micro_vlmax; i++) {
ei = i + micro_vlmax * microIdx;
%(memacc_code)s;
}
@@ -257,11 +256,10 @@ Fault
memcpy(Mem.as<uint8_t>(), pkt->getPtr<uint8_t>(), pkt->getSize());
}
const size_t micro_vlmax = vtype_VLMAX(machInst.vtype8, vlen, true);
const size_t micro_elems = vlen / width_EEW(machInst.width);
const size_t micro_vlmax = vlen / width_EEW(machInst.width);
size_t ei;
for (size_t i = 0; i < micro_elems; i++) {
for (size_t i = 0; i < micro_vlmax; i++) {
ei = i + micro_vlmax * microIdx;
%(memacc_code)s;
}
@@ -374,7 +372,7 @@ Fault
%(set_vlen)s;
%(ea_code)s;
const size_t micro_vlmax = vtype_VLMAX(machInst.vtype8, vlen, true);
const size_t micro_vlmax = vlen / width_EEW(machInst.width);
const size_t eewb = width_EEW(machInst.width) / 8;
const size_t mem_size = eewb * microVl;
std::vector<bool> byte_enable(mem_size, false);
@@ -425,7 +423,7 @@ Fault
%(set_vlen)s;
%(ea_code)s;
const size_t micro_vlmax = vtype_VLMAX(machInst.vtype8, vlen, true);
const size_t micro_vlmax = vlen / width_EEW(machInst.width);
const size_t eewb = width_EEW(machInst.width) / 8;
const size_t mem_size = eewb * microVl;
std::vector<bool> byte_enable(mem_size, false);