From 7d80658a39b693a956e8afc717eb93a31a3e183e Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Sa=C3=BAl?= <33020671+saul44203@users.noreply.github.com>
Date: Thu, 8 Feb 2024 23:06:49 +0100
Subject: [PATCH] arch-riscv: fix vl in mask load/store (i.e vlm.v/vsm.v)
 (#830)

The vlm.v and vsm.v unit-stride mask load/store instructions are
constructed with an incorrect VL when the current one is larger than
than VLEN/EEW (i.e. when LMUL > 1). This commit fixes the issue for both
instructions.
---
 src/arch/riscv/isa/templates/vector_mem.isa | 6 ++----
 1 file changed, 2 insertions(+), 4 deletions(-)

diff --git a/src/arch/riscv/isa/templates/vector_mem.isa b/src/arch/riscv/isa/templates/vector_mem.isa
index 74d84dd69d..4013b2a5d0 100644
--- a/src/arch/riscv/isa/templates/vector_mem.isa
+++ b/src/arch/riscv/isa/templates/vector_mem.isa
@@ -464,8 +464,7 @@ def template VlmConstructor {{
     %(set_reg_idx_arr)s;
     %(constructor)s;
 
-    const uint32_t micro_vlmax = vlen / width_EEW(_machInst.width);
-    int32_t micro_vl = (std::min(this->vl, micro_vlmax) + 7) / 8;
+    int32_t micro_vl = (this->vl + 7) / 8;
     StaticInstPtr microop;
 
     if (micro_vl == 0) {
@@ -491,8 +490,7 @@ def template VsmConstructor {{
     %(set_reg_idx_arr)s;
     %(constructor)s;
 
-    const uint32_t micro_vlmax = vlen / width_EEW(_machInst.width);
-    int32_t micro_vl = (std::min(this->vl, micro_vlmax) + 7) / 8;
+    int32_t micro_vl = (this->vl + 7) / 8;
 
     StaticInstPtr microop;
     if (micro_vl == 0) {