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arch-arm: TLBIs targeting EL2 regime are executable from S state (#1176)

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Those AArch64 instructions/registers were labelled as executable
from EL3 only if SCR_EL3.NS == 1. This is not valid anymore
after the introduction of FEAT_SEL2
This commit is contained in:
Ivana Mitrovic
2024-05-28 10:54:18 -07:00
committed by GitHub
parent 1dfaa224ff 27c7647fee
commit 5ec1acaf5f
1 changed files with 21 additions and 21 deletions
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42
src/arch/arm/regs/misc.cc
View File

@@ -5348,47 +5348,47 @@ ISA::initializeMiscRegMetadata()
.faultWrite(EL1, faultHcrFgtInstEL1<&HCR::ttlb, &HFGITR::tlbivaale1>)
.writes(1).exceptUserMode();
InitReg(MISCREG_TLBI_IPAS2E1OS)
.hypWrite().monSecureWrite().monNonSecureWrite();
.monWrite().hypWrite();
InitReg(MISCREG_TLBI_IPAS2LE1OS)
.hypWrite().monSecureWrite().monNonSecureWrite();
.monWrite().hypWrite();
InitReg(MISCREG_TLBI_ALLE2OS)
.monNonSecureWrite().hypWrite();
.monWrite().hypWrite();
InitReg(MISCREG_TLBI_VAE2OS)
.monNonSecureWrite().hypWrite();
.monWrite().hypWrite();
InitReg(MISCREG_TLBI_ALLE1OS)
.hypWrite().monSecureWrite().monNonSecureWrite();
.monWrite().hypWrite();
InitReg(MISCREG_TLBI_VALE2OS)
.monNonSecureWrite().hypWrite();
.monWrite().hypWrite();
InitReg(MISCREG_TLBI_VMALLS12E1OS)
.hypWrite().monSecureWrite().monNonSecureWrite();
.monWrite().hypWrite();
InitReg(MISCREG_TLBI_IPAS2E1IS)
.hypWrite().monSecureWrite().monNonSecureWrite();
.monWrite().hypWrite();
InitReg(MISCREG_TLBI_IPAS2LE1IS)
.hypWrite().monSecureWrite().monNonSecureWrite();
.monWrite().hypWrite();
InitReg(MISCREG_TLBI_ALLE2IS)
.monNonSecureWrite().hypWrite();
.monWrite().hypWrite();
InitReg(MISCREG_TLBI_VAE2IS)
.monNonSecureWrite().hypWrite();
.monWrite().hypWrite();
InitReg(MISCREG_TLBI_ALLE1IS)
.hypWrite().monSecureWrite().monNonSecureWrite();
.monWrite().hypWrite();
InitReg(MISCREG_TLBI_VALE2IS)
.monNonSecureWrite().hypWrite();
.monWrite().hypWrite();
InitReg(MISCREG_TLBI_VMALLS12E1IS)
.hypWrite().monSecureWrite().monNonSecureWrite();
.monWrite().hypWrite();
InitReg(MISCREG_TLBI_IPAS2E1)
.hypWrite().monSecureWrite().monNonSecureWrite();
.monWrite().hypWrite();
InitReg(MISCREG_TLBI_IPAS2LE1)
.hypWrite().monSecureWrite().monNonSecureWrite();
.monWrite().hypWrite();
InitReg(MISCREG_TLBI_ALLE2)
.monNonSecureWrite().hypWrite();
.monWrite().hypWrite();
InitReg(MISCREG_TLBI_VAE2)
.monNonSecureWrite().hypWrite();
.monWrite().hypWrite();
InitReg(MISCREG_TLBI_ALLE1)
.hypWrite().monSecureWrite().monNonSecureWrite();
.monWrite().hypWrite();
InitReg(MISCREG_TLBI_VALE2)
.monNonSecureWrite().hypWrite();
.monWrite().hypWrite();
InitReg(MISCREG_TLBI_VMALLS12E1)
.hypWrite().monSecureWrite().monNonSecureWrite();
.monWrite().hypWrite();
InitReg(MISCREG_TLBI_ALLE3OS)
.monSecureWrite().monNonSecureWrite();
InitReg(MISCREG_TLBI_VAE3OS)