diff --git a/src/arch/arm/regs/misc.cc b/src/arch/arm/regs/misc.cc
index d29a8bc367..6cbbd2f6fe 100644
--- a/src/arch/arm/regs/misc.cc
+++ b/src/arch/arm/regs/misc.cc
@@ -5348,47 +5348,47 @@ ISA::initializeMiscRegMetadata()
       .faultWrite(EL1, faultHcrFgtInstEL1<&HCR::ttlb, &HFGITR::tlbivaale1>)
       .writes(1).exceptUserMode();
     InitReg(MISCREG_TLBI_IPAS2E1OS)
-      .hypWrite().monSecureWrite().monNonSecureWrite();
+      .monWrite().hypWrite();
     InitReg(MISCREG_TLBI_IPAS2LE1OS)
-      .hypWrite().monSecureWrite().monNonSecureWrite();
+      .monWrite().hypWrite();
     InitReg(MISCREG_TLBI_ALLE2OS)
-      .monNonSecureWrite().hypWrite();
+      .monWrite().hypWrite();
     InitReg(MISCREG_TLBI_VAE2OS)
-      .monNonSecureWrite().hypWrite();
+      .monWrite().hypWrite();
     InitReg(MISCREG_TLBI_ALLE1OS)
-      .hypWrite().monSecureWrite().monNonSecureWrite();
+      .monWrite().hypWrite();
     InitReg(MISCREG_TLBI_VALE2OS)
-      .monNonSecureWrite().hypWrite();
+      .monWrite().hypWrite();
     InitReg(MISCREG_TLBI_VMALLS12E1OS)
-      .hypWrite().monSecureWrite().monNonSecureWrite();
+      .monWrite().hypWrite();
     InitReg(MISCREG_TLBI_IPAS2E1IS)
-      .hypWrite().monSecureWrite().monNonSecureWrite();
+      .monWrite().hypWrite();
     InitReg(MISCREG_TLBI_IPAS2LE1IS)
-      .hypWrite().monSecureWrite().monNonSecureWrite();
+      .monWrite().hypWrite();
     InitReg(MISCREG_TLBI_ALLE2IS)
-      .monNonSecureWrite().hypWrite();
+      .monWrite().hypWrite();
     InitReg(MISCREG_TLBI_VAE2IS)
-      .monNonSecureWrite().hypWrite();
+      .monWrite().hypWrite();
     InitReg(MISCREG_TLBI_ALLE1IS)
-      .hypWrite().monSecureWrite().monNonSecureWrite();
+      .monWrite().hypWrite();
     InitReg(MISCREG_TLBI_VALE2IS)
-      .monNonSecureWrite().hypWrite();
+      .monWrite().hypWrite();
     InitReg(MISCREG_TLBI_VMALLS12E1IS)
-      .hypWrite().monSecureWrite().monNonSecureWrite();
+      .monWrite().hypWrite();
     InitReg(MISCREG_TLBI_IPAS2E1)
-      .hypWrite().monSecureWrite().monNonSecureWrite();
+      .monWrite().hypWrite();
     InitReg(MISCREG_TLBI_IPAS2LE1)
-      .hypWrite().monSecureWrite().monNonSecureWrite();
+      .monWrite().hypWrite();
     InitReg(MISCREG_TLBI_ALLE2)
-      .monNonSecureWrite().hypWrite();
+      .monWrite().hypWrite();
     InitReg(MISCREG_TLBI_VAE2)
-      .monNonSecureWrite().hypWrite();
+      .monWrite().hypWrite();
     InitReg(MISCREG_TLBI_ALLE1)
-      .hypWrite().monSecureWrite().monNonSecureWrite();
+      .monWrite().hypWrite();
     InitReg(MISCREG_TLBI_VALE2)
-      .monNonSecureWrite().hypWrite();
+      .monWrite().hypWrite();
     InitReg(MISCREG_TLBI_VMALLS12E1)
-      .hypWrite().monSecureWrite().monNonSecureWrite();
+      .monWrite().hypWrite();
     InitReg(MISCREG_TLBI_ALLE3OS)
       .monSecureWrite().monNonSecureWrite();
     InitReg(MISCREG_TLBI_VAE3OS)